|  | @@ -8,7 +8,7 @@
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				|  |  |  
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				|  |  |  // ========== irq BEGIN ===========
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				|  |  |  
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				|  |  | -#define XHCI_IRQ_DONE (1<<31)   // 当command trb 的status的第31位被驱动程序置位时,表明该trb已经执行完成(这是由于xhci规定,第31位可以由驱动程序自行决定用途)
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				|  |  | +#define XHCI_IRQ_DONE (1 << 31) // 当command trb 的status的第31位被驱动程序置位时,表明该trb已经执行完成(这是由于xhci规定,第31位可以由驱动程序自行决定用途)
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				|  |  |  /**
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				|  |  |   * @brief 每个xhci控制器的中断向量号
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				|  |  |   *
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				|  | @@ -188,6 +188,10 @@ struct xhci_ops_config_reg_t
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				|  |  |  #define XHCI_TRB_CYCLE_OFF 0
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				|  |  |  #define XHCI_TRB_CYCLE_ON 1
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				|  |  |  
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				|  |  | +// 获取、设置trb中的status部分的complete code
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				|  |  | +#define xhci_get_comp_code(status) (((status) >> 24) & 0x7f)
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				|  |  | +#define xhci_set_comp_code(code) ((code & 0x7f) << 24)
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				|  |  | +
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				|  |  |  /**
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				|  |  |   * @brief xhci通用TRB结构
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				|  |  |   *
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				|  | @@ -220,7 +224,7 @@ struct xhci_TRB_normal_t
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				|  |  |      uint16_t Reserved;     // 保留且置为0
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				|  |  |  } __attribute__((packed));
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				|  |  |  
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				|  |  | -struct xhci_TRB_setup_state_t
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				|  |  | +struct xhci_TRB_setup_stage_t
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				|  |  |  {
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				|  |  |      uint8_t bmRequestType;
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				|  |  |      uint8_t bRequest;
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				|  | @@ -229,14 +233,14 @@ struct xhci_TRB_setup_state_t
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				|  |  |      uint16_t wIndex;
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				|  |  |      uint16_t wLength;
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				|  |  |  
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				|  |  | -    unsigned transfer_legth : 17;
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				|  |  | -    unsigned resv1 : 5; // Reserved and zero'd
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				|  |  | +    unsigned transfer_legth : 17; // TRB transfer length
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				|  |  | +    unsigned resv1 : 5;           // Reserved and zero'd
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				|  |  |      unsigned intr_target : 10;
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				|  |  |  
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				|  |  |      unsigned cycle : 1;
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				|  |  |      unsigned resv2 : 4; // Reserved and zero'd
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				|  |  | -    unsigned ioc : 1;
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				|  |  | -    unsigned idt : 1;
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				|  |  | +    unsigned ioc : 1;   // interrupt on complete
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				|  |  | +    unsigned idt : 1;   // immediate data (should always set for setup TRB)
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				|  |  |      unsigned resv3 : 3; // Reserved and zero'd
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				|  |  |      unsigned TRB_type : 6;
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				|  |  |      unsigned trt : 2;    // Transfer type
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				|  | @@ -354,8 +358,132 @@ struct xhci_intr_moderation_t
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				|  |  |  
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				|  |  |  #define XHCI_PORTUSB_CHANGE_BITS ((1 << 17) | (1 << 18) | (1 << 20) | (1 << 21) | (1 << 22))
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				|  |  |  
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				|  |  | +// 存储于portsc中的端口速度的可用值
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				|  |  | +#define XHCI_PORT_SPEED_FULL 1
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				|  |  | +#define XHCI_PORT_SPEED_LOW 2
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				|  |  | +#define XHCI_PORT_SPEED_HI 3
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				|  |  | +#define XHCI_PORT_SPEED_SUPER 4
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				|  |  | +
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				|  |  |  // ======= Port status and control registers END ====
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				|  |  |  
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				|  |  | +// ======= Device Slot Context BEGIN ====
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				|  |  | +
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				|  |  | +/**
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				|  |  | + * @brief 设备上下文结构体
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				|  |  | + *
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				|  |  | + */
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				|  |  | +struct xhci_slot_context_t
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				|  |  | +{
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				|  |  | +    unsigned route_string : 20;
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				|  |  | +    unsigned speed : 4;
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				|  |  | +    unsigned Rsvd0 : 1; // Reserved and zero'd
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				|  |  | +    unsigned mtt : 1;   // multi-TT
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				|  |  | +    unsigned hub : 1;
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				|  |  | +    unsigned entries : 5; // count of context entries
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				|  |  | +
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				|  |  | +    uint16_t max_exit_latency;
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				|  |  | +    uint8_t rh_port_num; // root hub port number
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				|  |  | +    uint8_t num_ports;   // number of ports
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				|  |  | +
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				|  |  | +    uint8_t tt_hub_slot_id;
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				|  |  | +    uint8_t tt_port_num;
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				|  |  | +    unsigned ttt : 2; // TT Think Time
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				|  |  | +    unsigned Rsvd2 : 4;
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				|  |  | +    unsigned int_target : 10; // Interrupter target
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				|  |  | +
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				|  |  | +    uint8_t device_address;
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				|  |  | +    unsigned Rsvd1 : 19;
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				|  |  | +    unsigned slot_state : 5;
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				|  |  | +} __attribute__((packed));
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				|  |  | +
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				|  |  | +#define XHCI_SLOT_STATE_DISABLED_OR_ENABLED 0
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				|  |  | +#define XHCI_SLOT_STATE_DEFAULT 1
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				|  |  | +#define XHCI_SLOT_STATE_ADDRESSED 2
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				|  |  | +#define XHCI_SLOT_STATE_CONFIGURED 3
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				|  |  | +
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				|  |  | +// ======= Device Slot Context END ====
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				|  |  | +
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				|  |  | +// ======= Device Endpoint Context BEGIN ====
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				|  |  | +
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				|  |  | +#define XHCI_EP_STATE_DISABLED 0
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				|  |  | +#define XHCI_EP_STATE_RUNNING 1
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				|  |  | +#define XHCI_EP_STATE_HALTED 2
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				|  |  | +#define XHCI_EP_STATE_STOPPED 3
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				|  |  | +#define XHCI_EP_STATE_ERROR 4
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				|  |  | +
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				|  |  | +// End Point Doorbell numbers
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				|  |  | +#define XHCI_SLOT_CNTX 0
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				|  |  | +#define XHCI_EP_CONTROL 1
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				|  |  | +#define XHCI_EP1_OUT 2
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				|  |  | +#define XHCI_EP1_IN 3
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				|  |  | +#define XHCI_EP2_OUT 4
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				|  |  | +#define XHCI_EP2_IN 5
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				|  |  | +#define XHCI_EP3_OUT 6
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				|  |  | +#define XHCI_EP3_IN 7
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				|  |  | +#define XHCI_EP4_OUT 8
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				|  |  | +#define XHCI_EP4_IN 9
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				|  |  | +#define XHCI_EP5_OUT 10
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				|  |  | +#define XHCI_EP5_IN 11
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				|  |  | +#define XHCI_EP6_OUT 12
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				|  |  | +#define XHCI_EP6_IN 13
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				|  |  | +#define XHCI_EP7_OUT 14
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				|  |  | +#define XHCI_EP7_IN 15
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				|  |  | +#define XHCI_EP8_OUT 16
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				|  |  | +#define XHCI_EP8_IN 17
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				|  |  | +#define XHCI_EP9_OUT 18
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				|  |  | +#define XHCI_EP9_IN 19
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				|  |  | +#define XHCI_EP10_OUT 20
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				|  |  | +#define XHCI_EP10_IN 21
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				|  |  | +#define XHCI_EP11_OUT 22
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				|  |  | +#define XHCI_EP11_IN 23
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				|  |  | +#define XHCI_EP12_OUT 24
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				|  |  | +#define XHCI_EP12_IN 25
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				|  |  | +#define XHCI_EP13_OUT 26
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				|  |  | +#define XHCI_EP13_IN 27
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				|  |  | +#define XHCI_EP14_OUT 28
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				|  |  | +#define XHCI_EP14_IN 29
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				|  |  | +#define XHCI_EP15_OUT 30
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				|  |  | +#define XHCI_EP15_IN 31
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				|  |  | +
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				|  |  | +// xhci 传输方向(用于setup stage TRB)
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				|  |  | +#define XHCI_DIR_NO_DATA 0
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				|  |  | +#define XHCI_DIR_OUT 2
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				|  |  | +#define XHCI_DIR_IN 3
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				|  |  | +
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				|  |  | +// xhci传输方向(单个bit的表示)
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				|  |  | +#define XHCI_DIR_OUT_BIT 0
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				|  |  | +#define XHCI_DIR_IN_BIT 1
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				|  |  | +
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				|  |  | +/**
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				|  |  | + * @brief xhci 端点上下文结构体
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				|  |  | + *
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				|  |  | + */
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				|  |  | +struct xhci_ep_context_t
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				|  |  | +{
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				|  |  | +    unsigned ep_state : 3;
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				|  |  | +    unsigned Rsvd0 : 5; // Reserved and zero'd
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				|  |  | +    unsigned mult : 2;  // the maximum supported number of bursts within an interval
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				|  |  | +    unsigned max_primary_streams : 5;
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				|  |  | +    unsigned linear_stream_array : 1;
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				|  |  | +    uint8_t interval;
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				|  |  | +    uint8_t max_esti_payload_hi; // Max Endpoint Service Time Interval Payload (High 8bit)
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				|  |  | +
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				|  |  | +    unsigned Rsvd1 : 1;
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				|  |  | +    unsigned err_cnt : 2; // error count. 当错误发生时,该位会自减。当减为0时,控制器会把这个端点挂起
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				|  |  | +    unsigned ep_type : 3; // endpoint type
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				|  |  | +    unsigned Rsvd2 : 1;
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				|  |  | +    unsigned hid : 1; // Host Initiate Disable
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				|  |  | +    uint8_t max_burst_size;
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				|  |  | +    uint16_t max_packet_size;
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				|  |  | +
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				|  |  | +    uint64_t tr_dequeue_ptr; // 第0bit为dequeue cycle state, 第1~3bit应保留。
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				|  |  | +
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				|  |  | +    uint16_t average_trb_len;     // 平均TRB长度。该部分不应为0
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				|  |  | +    uint16_t max_esti_payload_lo; // Max Endpoint Service Time Interval Payload (Low 16bit)
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				|  |  | +} __attribute__((packed));
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				|  |  | +
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				|  |  | +// ======= Device Endpoint Context END ====
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				|  |  | +
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				|  |  |  // 端口信息标志位
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				|  |  |  #define XHCI_PROTOCOL_USB2 0
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				|  |  |  #define XHCI_PROTOCOL_USB3 1
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				|  | @@ -376,6 +504,12 @@ struct xhci_port_info_t
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				|  |  |      uint8_t reserved;
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				|  |  |  } __attribute__((packed));
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				|  |  |  
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				|  |  | +struct xhci_ep_ring_info_t
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				|  |  | +{
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				|  |  | +    uint64_t ep_ring_vbase;         // transfer ring的基地址
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				|  |  | +    uint64_t current_ep_ring_vaddr; // transfer ring下一个要写入的地址
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				|  |  | +    uint8_t current_ep_ring_cycle;  // 当前ep的cycle bit
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				|  |  | +};
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				|  |  |  struct xhci_host_controller_t
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				|  |  |  {
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				|  |  |      struct pci_device_structure_general_device_t *pci_dev_hdr; // 指向pci header结构体的指针
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				|  | @@ -385,7 +519,7 @@ struct xhci_host_controller_t
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				|  |  |      uint32_t rts_offset;                                       // Runtime Register Space offset
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				|  |  |      uint32_t db_offset;                                        // Doorbell offset
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				|  |  |      uint32_t ext_caps_off;                                     // 扩展能力寄存器偏移量
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				|  |  | -    uint8_t context_size;                                      // 上下文大小
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				|  |  | +    uint8_t context_size;                                      // 设备上下文大小
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				|  |  |      uint16_t port_num;                                         // 总的端口数量
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				|  |  |      uint8_t port_num_u2;                                       // usb 2.0端口数量
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				|  |  |      uint8_t port_num_u3;                                       // usb 3端口数量
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				|  | @@ -399,6 +533,7 @@ struct xhci_host_controller_t
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				|  |  |      uint8_t cmd_trb_cycle;                                     // 当前command ring cycle
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				|  |  |      uint8_t current_event_ring_cycle;                          // 当前event ring cycle
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				|  |  |      struct xhci_port_info_t ports[XHCI_MAX_ROOT_HUB_PORTS];    // 指向端口信息数组的指针(由于端口offset是从1开始的,因此该数组第0项为空)
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				|  |  | +    struct xhci_ep_ring_info_t control_ep_info;                // 控制端点的信息
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				|  |  |  };
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				|  |  |  
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				|  |  |  // Common TRB types
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