xhci.c 10 KB

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  1. #include "xhci.h"
  2. #include <common/kprint.h>
  3. #include <debug/bug.h>
  4. #include <process/spinlock.h>
  5. #include <mm/mm.h>
  6. #include <debug/traceback/traceback.h>
  7. #include <common/time.h>
  8. spinlock_t xhci_controller_init_lock; // xhci控制器初始化锁(在usb_init中被初始化)
  9. static int xhci_ctrl_count = 0; // xhci控制器计数
  10. static struct xhci_host_controller_t xhci_hc[XHCI_MAX_HOST_CONTROLLERS] = {0};
  11. /*
  12. 注意!!!
  13. 尽管采用MMI/O的方式访问寄存器,但是对于指定大小的寄存器,
  14. 在发起读请求的时候,只能从寄存器的起始地址位置开始读取。
  15. 例子:不能在一个32bit的寄存器中的偏移量8的位置开始读取1个字节
  16. 这种情况下,我们必须从32bit的寄存器的0地址处开始读取32bit,然后通过移位的方式得到其中的字节。
  17. */
  18. #define xhci_read_cap_reg8(id, offset) (*(uint8_t *)(xhci_hc[id].vbase + offset))
  19. #define xhci_get_ptr_cap_reg8(id, offset) ((uint8_t *)(xhci_hc[id].vbase + offset))
  20. #define xhci_write_cap_reg8(id, offset, value) (*(uint8_t *)(xhci_hc[id].vbase + offset) = (uint8_t)value)
  21. #define xhci_read_cap_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase + offset))
  22. #define xhci_get_ptr_cap_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase + offset))
  23. #define xhci_write_cap_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase + offset) = (uint32_t)value)
  24. #define xhci_read_cap_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase + offset))
  25. #define xhci_get_ptr_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase + offset))
  26. #define xhci_write_cap_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase + offset) = (uint64_t)value)
  27. #define xhci_read_op_reg8(id, offset) (*(uint8_t *)(xhci_hc[id].vbase_op + offset))
  28. #define xhci_get_ptr_op_reg8(id, offset) ((uint8_t *)(xhci_hc[id].vbase_op + offset))
  29. #define xhci_write_op_reg8(id, offset, value) (*(uint8_t *)(xhci_hc[id].vbase_op + offset) = (uint8_t)value)
  30. #define xhci_read_op_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase_op + offset))
  31. #define xhci_get_ptr_op_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase_op + offset))
  32. #define xhci_write_op_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase_op + offset) = (uint32_t)value)
  33. #define xhci_read_op_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase_op + offset))
  34. #define xhci_get_ptr_op_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase_op + offset))
  35. #define xhci_write_op_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase_op + offset) = (uint64_t)value)
  36. #define FAIL_ON(value, to) \
  37. do \
  38. { \
  39. if (unlikely(value != 0)) \
  40. goto to; \
  41. } while (0)
  42. /**
  43. * @brief 在controller数组之中寻找可用插槽
  44. *
  45. * 注意:该函数只能被获得init锁的进程所调用
  46. * @return int 可用id(无空位时返回-1)
  47. */
  48. static int xhci_hc_find_available_id()
  49. {
  50. if (unlikely(xhci_ctrl_count >= XHCI_MAX_HOST_CONTROLLERS))
  51. return -1;
  52. for (int i = 0; i < XHCI_MAX_HOST_CONTROLLERS; ++i)
  53. {
  54. if (xhci_hc[i].pci_dev_hdr == NULL)
  55. return i;
  56. }
  57. return -1;
  58. }
  59. /**
  60. * @brief 停止xhci主机控制器
  61. *
  62. * @param id 主机控制器id
  63. * @return int
  64. */
  65. static int xhci_hc_stop(int id)
  66. {
  67. // 判断是否已经停止
  68. if (unlikely((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 1))
  69. return 0;
  70. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, 0x00000000);
  71. char timeout = 17;
  72. while ((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 0)
  73. {
  74. usleep(1000);
  75. if (--timeout == 0)
  76. return -ETIMEDOUT;
  77. }
  78. return 0;
  79. }
  80. /**
  81. * @brief reset xHCI主机控制器
  82. *
  83. * @param id 主机控制器id
  84. * @return int
  85. */
  86. static int xhci_hc_reset(int id)
  87. {
  88. int retval = 0;
  89. // 判断HCHalted是否置位
  90. if ((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 0)
  91. {
  92. // 未置位,需要先尝试停止usb主机控制器
  93. retval = xhci_hc_stop(id);
  94. if (unlikely(retval))
  95. return retval;
  96. }
  97. int timeout = 500; // wait 500ms
  98. // reset
  99. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, (1 << 1));
  100. while (xhci_read_op_reg32(id, XHCI_OPS_USBCMD) & (1 << 1))
  101. {
  102. usleep(1000);
  103. if (--timeout == 0)
  104. return -ETIMEDOUT;
  105. }
  106. // kdebug("reset done!, timeout=%d", timeout);
  107. return retval;
  108. }
  109. /**
  110. * @brief 停止指定xhci控制器的legacy support
  111. *
  112. * @param id 控制器id
  113. * @return int
  114. */
  115. static int xhci_hc_stop_legacy(int id)
  116. {
  117. uint64_t current_offset = xhci_hc[id].ext_caps_off;
  118. do
  119. {
  120. // 判断当前entry是否为legacy support entry
  121. if (xhci_read_cap_reg8(id, current_offset) == XHCI_XECP_ID_LEGACY)
  122. {
  123. // 接管控制权
  124. xhci_write_cap_reg32(id, current_offset, xhci_read_cap_reg32(id, current_offset) | XHCI_XECP_LEGACY_OS_OWNED);
  125. // 等待响应完成
  126. int timeout = XHCI_XECP_LEGACY_TIMEOUT;
  127. while ((xhci_read_cap_reg32(id, current_offset) & XHCI_XECP_LEGACY_OWNING_MASK) != XHCI_XECP_LEGACY_OS_OWNED)
  128. {
  129. usleep(1000);
  130. if (--timeout == 0)
  131. {
  132. kerror("The BIOS doesn't stop legacy support.");
  133. return -ETIMEDOUT;
  134. }
  135. }
  136. // 处理完成
  137. return 0;
  138. }
  139. // 读取下一个entry的偏移增加量
  140. int next_off = ((xhci_read_cap_reg32(id, current_offset) & 0xff00) >> 8) << 2;
  141. // 将指针跳转到下一个entry
  142. current_offset = next_off ? (current_offset + next_off) : 0;
  143. } while (current_offset);
  144. // 当前controller不存在legacy支持,也问题不大,不影响
  145. return 0;
  146. }
  147. /**
  148. * @brief 配对xhci主机控制器的usb2、usb3端口
  149. *
  150. * @param id 主机控制器id
  151. * @return int 返回码
  152. */
  153. static int xhci_hc_pair_ports(int id)
  154. {
  155. struct xhci_caps_HCCPARAMS1_reg_t hcc1;
  156. struct xhci_caps_HCCPARAMS2_reg_t hcc2;
  157. struct xhci_caps_HCSPARAMS1_reg_t hcs1;
  158. struct xhci_caps_HCSPARAMS2_reg_t hcs2;
  159. memcpy(&hcc1, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCCPARAMS1), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  160. memcpy(&hcc2, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCCPARAMS2), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  161. memcpy(&hcs1, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCSPARAMS1), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  162. memcpy(&hcs2, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCSPARAMS2), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  163. // 从hcs1获取端口数量
  164. xhci_hc[id].port_num = hcs1.max_ports;
  165. kinfo("Found %d ports on xhci root hub.", hcs1.max_ports);
  166. // 找到所有的端口并标记其端口信息
  167. return 0;
  168. }
  169. /**
  170. * @brief 初始化xhci控制器
  171. *
  172. * @param header 指定控制器的pci device头部
  173. */
  174. void xhci_init(struct pci_device_structure_general_device_t *dev_hdr)
  175. {
  176. if (xhci_ctrl_count >= XHCI_MAX_HOST_CONTROLLERS)
  177. {
  178. kerror("Initialize xhci controller failed: exceed the limit of max controllers.");
  179. return;
  180. }
  181. spin_lock(&xhci_controller_init_lock);
  182. kinfo("Initializing xhci host controller: bus=%#02x, device=%#02x, func=%#02x, VendorID=%#04x, irq_line=%d, irq_pin=%d", dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, dev_hdr->header.Vendor_ID, dev_hdr->Interrupt_Line, dev_hdr->Interrupt_PIN);
  183. int cid = xhci_hc_find_available_id();
  184. if (cid < 0)
  185. {
  186. kerror("Initialize xhci controller failed: exceed the limit of max controllers.");
  187. goto failed_exceed_max;
  188. }
  189. memset(&xhci_hc[cid], 0, sizeof(struct xhci_host_controller_t));
  190. xhci_hc[cid].controller_id = cid;
  191. xhci_hc[cid].pci_dev_hdr = dev_hdr;
  192. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0x4, 0x0006); // mem I/O access enable and bus master enable
  193. // 为当前控制器映射寄存器地址空间
  194. xhci_hc[cid].vbase = SPECIAL_MEMOEY_MAPPING_VIRT_ADDR_BASE + XHCI_MAPPING_OFFSET + 65536 * xhci_hc[cid].controller_id;
  195. kdebug("dev_hdr->BAR0 & (~0xf)=%#018lx", dev_hdr->BAR0 & (~0xf));
  196. mm_map_phys_addr(xhci_hc[cid].vbase, dev_hdr->BAR0 & (~0xf), 65536, PAGE_KERNEL_PAGE | PAGE_PWT | PAGE_PCD, true);
  197. // 读取xhci控制寄存器
  198. uint16_t iversion = *(uint16_t *)(xhci_hc[cid].vbase + XHCI_CAPS_HCIVERSION);
  199. uint32_t hcc1 = xhci_read_cap_reg32(cid, XHCI_CAPS_HCCPARAMS1);
  200. // 计算operational registers的地址
  201. xhci_hc[cid].vbase_op = xhci_hc[cid].vbase + xhci_read_cap_reg8(cid, XHCI_CAPS_CAPLENGTH);
  202. xhci_hc[cid].db_offset = xhci_read_cap_reg32(cid, XHCI_CAPS_DBOFF) & (~0x3); // bits [1:0] reserved
  203. xhci_hc[cid].rts_offset = xhci_read_cap_reg32(cid, XHCI_CAPS_RTSOFF) & (~0x1f); // bits [4:0] reserved.
  204. xhci_hc[cid].ext_caps_off = ((hcc1 & 0xffff0000) >> 16) * 4;
  205. xhci_hc[cid].context_size = (hcc1 & (1 << 2)) ? 64 : 32;
  206. if (iversion < 0x95)
  207. {
  208. kwarn("Unsupported/Unknowned xHCI controller version: %#06x. This may cause unexpected behavior.", iversion);
  209. }
  210. // if it is a Panther Point device, make sure sockets are xHCI controlled.
  211. if (((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0) & 0xffff) == 0x8086) &&
  212. ((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 2) & 0xffff) == 0x1E31) &&
  213. ((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 8) & 0xff) == 4))
  214. {
  215. kdebug("Is a Panther Point device");
  216. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0xd8, 0xffffffff);
  217. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0xd0, 0xffffffff);
  218. }
  219. // 重置xhci控制器
  220. FAIL_ON(xhci_hc_reset(cid), failed);
  221. FAIL_ON(xhci_hc_stop_legacy(cid), failed);
  222. FAIL_ON(xhci_hc_pair_ports(cid), failed);
  223. ++xhci_ctrl_count;
  224. spin_unlock(&xhci_controller_init_lock);
  225. return;
  226. failed:;
  227. // 取消地址映射
  228. mm_unmap(xhci_hc[cid].vbase, 65536);
  229. // 清空数组
  230. memset((void *)&xhci_hc[cid], 0, sizeof(struct xhci_host_controller_t));
  231. failed_exceed_max:;
  232. kerror("Failed to initialize controller: bus=%d, dev=%d, func=%d", dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func);
  233. spin_unlock(&xhci_controller_init_lock);
  234. }