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- #pragma once
- #include <driver/usb/usb.h>
- #include <driver/pci/pci.h>
- #include <driver/pci/msi.h>
- #define XHCI_MAX_HOST_CONTROLLERS 4
- #define XHCI_MAX_ROOT_HUB_PORTS 128
- #define XHCI_IRQ_DONE (1 << 31)
- const uint8_t xhci_controller_irq_num[XHCI_MAX_HOST_CONTROLLERS] = {157, 158, 159, 160};
- #define xhci_find_hcid_by_irq_num(irq_num) ({ \
- int retval = -1; \
- for (int i = 0; i < XHCI_MAX_HOST_CONTROLLERS; ++i) \
- if (xhci_controller_irq_num[i] == irq_num) \
- retval = i; \
- retval; \
- })
- struct xhci_hc_irq_install_info_t
- {
- int processor;
- int8_t edge_trigger;
- int8_t assert;
- };
- #define XHCI_CAPS_CAPLENGTH 0x00
- #define XHCI_CAPS_RESERVED 0x01
- #define XHCI_CAPS_HCIVERSION 0x02
- #define XHCI_CAPS_HCSPARAMS1 0x04
- #define XHCI_CAPS_HCSPARAMS2 0x08
- #define XHCI_CAPS_HCSPARAMS3 0x0c
- #define XHCI_CAPS_HCCPARAMS1 0x10
- #define XHCI_CAPS_DBOFF 0x14
- #define XHCI_CAPS_RTSOFF 0x18
- #define XHCI_CAPS_HCCPARAMS2 0x1c
- struct xhci_caps_HCSPARAMS1_reg_t
- {
- unsigned max_slots : 8;
- unsigned max_intrs : 11;
- unsigned reserved : 5;
- unsigned max_ports : 8;
- } __attribute__((packed));
- struct xhci_caps_HCSPARAMS2_reg_t
- {
- unsigned ist : 4;
- unsigned ERST_Max : 4;
- unsigned Reserved : 13;
- unsigned max_scratchpad_buf_HI5 : 5;
- unsigned spr : 1;
- unsigned max_scratchpad_buf_LO5 : 5;
- } __attribute__((packed));
- struct xhci_caps_HCSPARAMS3_reg_t
- {
- uint8_t u1_device_exit_latency;
- uint8_t Reserved;
- uint16_t u2_device_exit_latency;
- } __attribute__((packed));
- struct xhci_caps_HCCPARAMS1_reg_t
- {
- unsigned int ac64 : 1;
- unsigned int bnc : 1;
- unsigned int csz : 1;
- unsigned int ppc : 1;
- unsigned int pind : 1;
- unsigned int lhrc : 1;
- unsigned int ltc : 1;
- unsigned int nss : 1;
- unsigned int pae : 1;
- unsigned int spc : 1;
- unsigned int sec : 1;
- unsigned int cfc : 1;
- unsigned int MaxPSASize : 4;
- uint16_t xECP;
- } __attribute__((packed));
- struct xhci_caps_HCCPARAMS2_reg_t
- {
- unsigned u3c : 1;
- unsigned cmc : 1;
- unsigned fsc : 1;
- unsigned ctc : 1;
- unsigned lec : 1;
- unsigned cic : 1;
- unsigned Reserved : 26;
- } __attribute__((packed));
- #define XHCI_OPS_USBCMD 0x00
- #define XHCI_OPS_USBSTS 0x04
- #define XHCI_OPS_PAGESIZE 0x08
- #define XHCI_OPS_DNCTRL 0x14
- #define XHCI_OPS_CRCR 0x18
- #define XHCI_OPS_DCBAAP 0x30
- #define XHCI_OPS_CONFIG 0x38
- #define XHCI_OPS_PRS 0x400
- struct xhci_ops_usbcmd_reg_t
- {
- unsigned rs : 1;
- unsigned hcrst : 1;
- unsigned inte : 1;
- unsigned hsee : 1;
- unsigned rsvd_psvd1 : 3;
- unsigned lhcrst : 1;
- unsigned css : 1;
- unsigned crs : 1;
- unsigned ewe : 1;
- unsigned ue3s : 1;
- unsigned spe : 1;
- unsigned cme : 1;
- unsigned rsvd_psvd2 : 18;
- } __attribute__((packed));
- struct xhci_ops_usbsts_reg_t
- {
- unsigned HCHalted : 1;
- unsigned rsvd_psvd1 : 1;
- unsigned hse : 1;
- unsigned eint : 1;
- unsigned pcd : 1;
- unsigned rsvd_zerod : 3;
- unsigned sss : 1;
- unsigned rss : 1;
- unsigned sre : 1;
- unsigned cnr : 1;
- unsigned hce : 1;
- unsigned rsvd_psvd2 : 19;
- } __attribute__((packed));
- struct xhci_ops_pagesize_reg_t
- {
- uint16_t page_size;
- uint16_t reserved;
- } __attribute__((packed));
- struct xhci_ops_dnctrl_reg_t
- {
- uint16_t value;
- uint16_t reserved;
- } __attribute__((packed));
- struct xhci_ops_config_reg_t
- {
- uint8_t MaxSlotsEn;
- unsigned u3e : 1;
- unsigned cie : 1;
- unsigned rsvd_psvd : 22;
- } __attribute__((packed));
- #define XHCI_TRB_TRT_NO_DATA 0
- #define XHCI_TRB_TRT_RESERVED 1
- #define XHCI_TRB_TRT_OUT_DATA 2
- #define XHCI_TRB_TRT_IN_DATA 3
- #define XHCI_CMND_RING_TRBS 128
- #define XHCI_TRBS_PER_RING 256
- #define XHCI_TRB_CYCLE_OFF 0
- #define XHCI_TRB_CYCLE_ON 1
- #define xhci_get_comp_code(status) (((status) >> 24) & 0x7f)
- #define xhci_set_comp_code(code) ((code & 0x7f) << 24)
- struct xhci_TRB_t
- {
- uint64_t param;
- uint32_t status;
- uint32_t command;
- } __attribute__((packed));
- struct xhci_TRB_normal_t
- {
- uint64_t buf_paddr;
- unsigned transfer_length : 17;
- unsigned TD_size : 5;
- unsigned intr_target : 10;
- unsigned cycle : 1;
- unsigned ent : 1;
- unsigned isp : 1;
- unsigned ns : 1;
- unsigned chain : 1;
-
- unsigned ioc : 1;
- unsigned idt : 1;
- unsigned resv : 2;
- unsigned bei : 1;
- unsigned TRB_type : 6;
- uint16_t Reserved;
- } __attribute__((packed));
- struct xhci_TRB_setup_stage_t
- {
- uint8_t bmRequestType;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
- unsigned transfer_legth : 17;
- unsigned resv1 : 5;
- unsigned intr_target : 10;
- unsigned cycle : 1;
- unsigned resv2 : 4;
- unsigned ioc : 1;
- unsigned idt : 1;
- unsigned resv3 : 3;
- unsigned TRB_type : 6;
- unsigned trt : 2;
- unsigned resv4 : 14;
- } __attribute__((packed));
- struct xhci_TRB_data_stage_t
- {
- uint64_t buf_paddr;
- unsigned transfer_length : 17;
- unsigned TD_size : 5;
- unsigned intr_target : 10;
- unsigned cycle : 1;
- unsigned ent : 1;
- unsigned isp : 1;
- unsigned ns : 1;
- unsigned chain : 1;
-
- unsigned ioc : 1;
- unsigned idt : 1;
- unsigned resv : 3;
- unsigned TRB_type : 6;
- unsigned dir : 1;
-
- unsigned Reserved : 15;
- } __attribute__((packed));
- struct xhci_TRB_status_stage_t
- {
- uint64_t resv1;
- unsigned resv2 : 22;
- unsigned intr_target : 10;
- unsigned cycle : 1;
- unsigned ent : 1;
- unsigned resv3 : 2;
- unsigned chain : 1;
-
- unsigned ioc : 1;
- unsigned resv4 : 4;
- unsigned TRB_type : 6;
- unsigned dir : 1;
-
- unsigned Reserved : 15;
- } __attribute__((packed));
- struct xhci_TRB_cmd_complete_t
- {
- uint64_t cmd_trb_pointer_paddr;
- unsigned resv1 : 24;
- uint8_t code;
- unsigned cycle : 1;
- unsigned resv2 : 9;
- unsigned TRB_type : 6;
- uint8_t VF_ID;
- uint8_t slot_id;
-
- } __attribute__((packed));
- #define XHCI_RT_IR0 0x20
- #define XHCI_IR_SIZE 32
- #define XHCI_IR_MAN 0x00
- #define XHCI_IR_MOD 0x04
- #define XHCI_IR_TABLE_SIZE 0x08
- #define XHCI_IR_TABLE_ADDR 0x10
- #define XHCI_IR_DEQUEUE 0x18
- #define XHCI_IR_IMR_PENDING (1 << 0)
- #define XHCI_IR_IMR_ENABLE (1 << 1)
- struct xhci_intr_moderation_t
- {
- uint16_t interval;
- uint16_t counter;
- } __attribute__((packed));
- #define XHCI_XECP_ID_RESERVED 0
- #define XHCI_XECP_ID_LEGACY 1
- #define XHCI_XECP_ID_PROTOCOL 2
- #define XHCI_XECP_ID_POWER 3
- #define XHCI_XECP_ID_IOVIRT 4
- #define XHCI_XECP_ID_MSG 5
- #define XHCI_XECP_ID_LOCAL_MEM 6
- #define XHCI_XECP_ID_DEBUG 10
- #define XHCI_XECP_ID_EXTMSG 17
- #define XHCI_XECP_LEGACY_TIMEOUT 10
- #define XHCI_XECP_LEGACY_BIOS_OWNED (1 << 16)
- #define XHCI_XECP_LEGACY_OS_OWNED (1 << 24)
- #define XHCI_XECP_LEGACY_OWNING_MASK (XHCI_XECP_LEGACY_BIOS_OWNED | XHCI_XECP_LEGACY_OS_OWNED)
- #define XHCI_PORT_PORTSC 0x00
- #define XHCI_PORT_PORTPMSC 0x04
- #define XHCI_PORT_PORTLI 0x08
- #define XHCI_PORT_PORTHLMPC 0x0c
- #define XHCI_PORTUSB_CHANGE_BITS ((1 << 17) | (1 << 18) | (1 << 20) | (1 << 21) | (1 << 22))
- #define XHCI_PORT_SPEED_FULL 1
- #define XHCI_PORT_SPEED_LOW 2
- #define XHCI_PORT_SPEED_HI 3
- #define XHCI_PORT_SPEED_SUPER 4
- struct xhci_slot_context_t
- {
- unsigned route_string : 20;
- unsigned speed : 4;
- unsigned Rsvd0 : 1;
- unsigned mtt : 1;
- unsigned hub : 1;
- unsigned entries : 5;
- uint16_t max_exit_latency;
- uint8_t rh_port_num;
- uint8_t num_ports;
- uint8_t tt_hub_slot_id;
- uint8_t tt_port_num;
- unsigned ttt : 2;
- unsigned Rsvd2 : 4;
- unsigned int_target : 10;
- uint8_t device_address;
- unsigned Rsvd1 : 19;
- unsigned slot_state : 5;
- } __attribute__((packed));
- #define XHCI_SLOT_STATE_DISABLED_OR_ENABLED 0
- #define XHCI_SLOT_STATE_DEFAULT 1
- #define XHCI_SLOT_STATE_ADDRESSED 2
- #define XHCI_SLOT_STATE_CONFIGURED 3
- #define XHCI_EP_STATE_DISABLED 0
- #define XHCI_EP_STATE_RUNNING 1
- #define XHCI_EP_STATE_HALTED 2
- #define XHCI_EP_STATE_STOPPED 3
- #define XHCI_EP_STATE_ERROR 4
- #define XHCI_SLOT_CNTX 0
- #define XHCI_EP_CONTROL 1
- #define XHCI_EP1_OUT 2
- #define XHCI_EP1_IN 3
- #define XHCI_EP2_OUT 4
- #define XHCI_EP2_IN 5
- #define XHCI_EP3_OUT 6
- #define XHCI_EP3_IN 7
- #define XHCI_EP4_OUT 8
- #define XHCI_EP4_IN 9
- #define XHCI_EP5_OUT 10
- #define XHCI_EP5_IN 11
- #define XHCI_EP6_OUT 12
- #define XHCI_EP6_IN 13
- #define XHCI_EP7_OUT 14
- #define XHCI_EP7_IN 15
- #define XHCI_EP8_OUT 16
- #define XHCI_EP8_IN 17
- #define XHCI_EP9_OUT 18
- #define XHCI_EP9_IN 19
- #define XHCI_EP10_OUT 20
- #define XHCI_EP10_IN 21
- #define XHCI_EP11_OUT 22
- #define XHCI_EP11_IN 23
- #define XHCI_EP12_OUT 24
- #define XHCI_EP12_IN 25
- #define XHCI_EP13_OUT 26
- #define XHCI_EP13_IN 27
- #define XHCI_EP14_OUT 28
- #define XHCI_EP14_IN 29
- #define XHCI_EP15_OUT 30
- #define XHCI_EP15_IN 31
- #define XHCI_DIR_NO_DATA 0
- #define XHCI_DIR_OUT 2
- #define XHCI_DIR_IN 3
- #define XHCI_DIR_OUT_BIT 0
- #define XHCI_DIR_IN_BIT 1
- struct xhci_ep_context_t
- {
- unsigned ep_state : 3;
- unsigned Rsvd0 : 5;
- unsigned mult : 2;
- unsigned max_primary_streams : 5;
- unsigned linear_stream_array : 1;
- uint8_t interval;
- uint8_t max_esti_payload_hi;
- unsigned Rsvd1 : 1;
- unsigned err_cnt : 2;
- unsigned ep_type : 3;
- unsigned Rsvd2 : 1;
- unsigned hid : 1;
- uint8_t max_burst_size;
- uint16_t max_packet_size;
- uint64_t tr_dequeue_ptr;
- uint16_t average_trb_len;
- uint16_t max_esti_payload_lo;
- } __attribute__((packed));
- #define XHCI_PROTOCOL_USB2 0
- #define XHCI_PROTOCOL_USB3 1
- #define XHCI_PROTOCOL_INFO (1 << 0) // 1->usb3, 0->usb2
- #define XHCI_PROTOCOL_HSO (1 << 1) // 1-> usb2 high speed only
- #define XHCI_PROTOCOL_HAS_PAIR (1 << 2)
- #define XHCI_PROTOCOL_ACTIVE (1 << 3)
- struct xhci_port_info_t
- {
- uint8_t flags;
- uint8_t paired_port_num;
- uint8_t offset;
- uint8_t reserved;
- } __attribute__((packed));
- struct xhci_ep_ring_info_t
- {
- uint64_t ep_ring_vbase;
- uint64_t current_ep_ring_vaddr;
- uint8_t current_ep_ring_cycle;
- };
- struct xhci_host_controller_t
- {
- struct pci_device_structure_general_device_t *pci_dev_hdr;
- int controller_id;
- uint64_t vbase;
- uint64_t vbase_op;
- uint32_t rts_offset;
- uint32_t db_offset;
- uint32_t ext_caps_off;
- uint8_t context_size;
- uint16_t port_num;
- uint8_t port_num_u2;
- uint8_t port_num_u3;
- uint32_t page_size;
- uint64_t dcbaap_vaddr;
- uint64_t cmd_ring_vaddr;
- uint64_t cmd_trb_vaddr;
- uint64_t event_ring_vaddr;
- uint64_t event_ring_table_vaddr;
- uint64_t current_event_ring_vaddr;
- uint8_t cmd_trb_cycle;
- uint8_t current_event_ring_cycle;
- struct xhci_port_info_t ports[XHCI_MAX_ROOT_HUB_PORTS];
- struct xhci_ep_ring_info_t control_ep_info;
- };
- enum
- {
- TRB_TYPE_NORMAL = 1,
- TRB_TYPE_SETUP_STAGE,
- TRB_TYPE_DATA_STAGE,
- TRB_TYPE_STATUS_STAGE,
- TRB_TYPE_ISOCH,
- TRB_TYPE_LINK,
- TRB_TYPE_EVENT_DATA,
- TRB_TYPE_NO_OP,
- TRB_TYPE_ENABLE_SLOT,
- TRB_TYPE_DISABLE_SLOT = 10,
- TRB_TYPE_ADDRESS_DEVICE = 11,
- TRB_TYPE_CONFIG_EP,
- TRB_TYPE_EVALUATE_CONTEXT,
- TRB_TYPE_RESET_EP,
- TRB_TYPE_STOP_EP = 15,
- TRB_TYPE_SET_TR_DEQUEUE,
- TRB_TYPE_RESET_DEVICE,
- TRB_TYPE_FORCE_EVENT,
- TRB_TYPE_DEG_BANDWIDTH,
- TRB_TYPE_SET_LAT_TOLERANCE = 20,
- TRB_TYPE_GET_PORT_BAND = 21,
- TRB_TYPE_FORCE_HEADER,
- TRB_TYPE_NO_OP_CMD,
- TRB_TYPE_TRANS_EVENT = 32,
- TRB_TYPE_COMMAND_COMPLETION,
- TRB_TYPE_PORT_STATUS_CHANGE,
- TRB_TYPE_BANDWIDTH_REQUEST,
- TRB_TYPE_DOORBELL_EVENT,
- TRB_TYPE_HOST_CONTROLLER_EVENT = 37,
- TRB_TYPE_DEVICE_NOTIFICATION,
- TRB_TYPE_MFINDEX_WRAP,
-
-
- };
- enum
- {
- TRB_COMP_TRB_SUCCESS = 1,
- TRB_COMP_DATA_BUFFER_ERROR,
- TRB_COMP_BABBLE_DETECTION,
- TRB_COMP_TRANSACTION_ERROR,
- TRB_COMP_TRB_ERROR,
- TRB_COMP_STALL_ERROR,
- TRB_COMP_RESOURCE_ERROR = 7,
- TRB_COMP_BANDWIDTH_ERROR,
- TRB_COMP_NO_SLOTS_ERROR,
- TRB_COMP_INVALID_STREAM_TYPE,
- TRB_COMP_SLOT_NOT_ENABLED,
- TRB_COMP_EP_NOT_ENABLED,
- TRB_COMP_SHORT_PACKET = 13,
- TRB_COMP_RING_UNDERRUN,
- TRB_COMP_RUNG_OVERRUN,
- TRB_COMP_VF_EVENT_RING_FULL,
- TRB_COMP_PARAMETER_ERROR,
- TRB_COMP_BANDWITDH_OVERRUN,
- TRB_COMP_CONTEXT_STATE_ERROR = 19,
- TRB_COMP_NO_PING_RESPONSE,
- TRB_COMP_EVENT_RING_FULL,
- TRB_COMP_INCOMPATIBLE_DEVICE,
- TRB_COMP_MISSED_SERVICE,
- TRB_COMP_COMMAND_RING_STOPPED = 24,
- TRB_COMP_COMMAND_ABORTED,
- TRB_COMP_STOPPED,
- TRB_COMP_STOPPER_LENGTH_ERROR,
- TRB_COMP_RESERVED,
- TRB_COMP_ISOCH_BUFFER_OVERRUN,
- TRB_COMP_EVERN_LOST = 32,
- TRB_COMP_UNDEFINED,
- TRB_COMP_INVALID_STREAM_ID,
- TRB_COMP_SECONDARY_BANDWIDTH,
- TRB_COMP_SPLIT_TRANSACTION
-
-
-
- };
- void xhci_init(struct pci_device_structure_general_device_t *header);
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