pci.c 21 KB

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  1. #include "pci.h"
  2. #include "../../common/kprint.h"
  3. #include "../../mm/slab.h"
  4. static uint count_device_list = 0;
  5. static void pci_checkBus(uint8_t bus);
  6. /**
  7. * @brief 将设备信息结构体加到链表里面
  8. *
  9. */
  10. #define ADD_DEVICE_STRUCT_TO_LIST(ret) \
  11. do \
  12. { \
  13. if (count_device_list > 0) \
  14. { \
  15. ++count_device_list; \
  16. list_add(pci_device_structure_list, &(ret->header.list)); \
  17. } \
  18. else \
  19. { \
  20. ++count_device_list; \
  21. list_init(&(ret->header.list)); \
  22. pci_device_structure_list = &(ret->header.list); \
  23. } \
  24. } while (0)
  25. /**
  26. * @brief 生成架构相关的msi的message address
  27. *
  28. */
  29. #define pci_get_arch_msi_message_address(processor) ((uint64_t)(0xfee00000UL | (processor << 12)))
  30. /**
  31. * @brief 生成架构相关的message data
  32. *
  33. */
  34. #define pci_get_arch_msi_message_data(vector, processor, edge_trigger, assert) ((uint32_t)((vector & 0xff) | (edge_trigger == 1 ? 0 : (1 << 15)) | (assert == 0 ? 0 : (1 << 14))))
  35. /**
  36. * @brief 从pci配置空间读取信息
  37. *
  38. * @param bus 总线号
  39. * @param slot 设备号
  40. * @param func 功能号
  41. * @param offset 字节偏移量
  42. * @return uint 寄存器值
  43. */
  44. uint32_t pci_read_config(uchar bus, uchar slot, uchar func, uchar offset)
  45. {
  46. uint lbus = (uint)bus;
  47. uint lslot = (uint)slot;
  48. uint lfunc = ((uint)func) & 7;
  49. // 构造pci配置空间地址
  50. uint address = (uint)((lbus << 16) | (lslot << 11) | (lfunc << 8) | (offset & 0xfc) | ((uint)0x80000000));
  51. io_out32(PORT_PCI_CONFIG_ADDRESS, address);
  52. // 读取返回的数据
  53. uint32_t ret = (uint)(io_in32(PORT_PCI_CONFIG_DATA));
  54. return ret;
  55. }
  56. /**
  57. * @brief 向pci配置空间写入信息
  58. *
  59. * @param bus 总线号
  60. * @param slot 设备号
  61. * @param func 功能号
  62. * @param offset 字节偏移量
  63. * @return uint 返回码
  64. */
  65. uint pci_write_config(uchar bus, uchar slot, uchar func, uchar offset, uint32_t data)
  66. {
  67. uint lbus = (uint)bus;
  68. uint lslot = (uint)slot;
  69. uint lfunc = ((uint)func) & 7;
  70. // 构造pci配置空间地址
  71. uint address = (uint)((lbus << 16) | (lslot << 11) | (lfunc << 8) | (offset & 0xfc) | ((uint)0x80000000));
  72. io_out32(PORT_PCI_CONFIG_ADDRESS, address);
  73. // 写入数据
  74. io_out32(PORT_PCI_CONFIG_DATA, data);
  75. return 0;
  76. }
  77. /**
  78. * @brief 读取type为0x0的pci设备的header
  79. * 本函数只应被 pci_read_header()调用
  80. * @param header 返回的header
  81. * @param bus 总线号
  82. * @param slot 插槽号
  83. * @param func 功能号
  84. */
  85. static void pci_read_general_device_header(struct pci_device_structure_general_device_t *header, uchar bus, uchar slot, uchar func)
  86. {
  87. uint32_t tmp32;
  88. header->BAR0 = pci_read_config(bus, slot, func, 0x10);
  89. header->BAR1 = pci_read_config(bus, slot, func, 0x14);
  90. header->BAR2 = pci_read_config(bus, slot, func, 0x18);
  91. header->BAR3 = pci_read_config(bus, slot, func, 0x1c);
  92. header->BAR4 = pci_read_config(bus, slot, func, 0x20);
  93. header->BAR5 = pci_read_config(bus, slot, func, 0x24);
  94. header->Cardbus_CIS_Pointer = pci_read_config(bus, slot, func, 0x28);
  95. tmp32 = pci_read_config(bus, slot, func, 0x2c);
  96. header->Subsystem_Vendor_ID = tmp32 & 0xffff;
  97. header->Subsystem_ID = (tmp32 >> 16) & 0xffff;
  98. header->Expansion_ROM_base_address = pci_read_config(bus, slot, func, 0x30);
  99. tmp32 = pci_read_config(bus, slot, func, 0x34);
  100. header->Capabilities_Pointer = tmp32 & 0xff;
  101. header->reserved0 = (tmp32 >> 8) & 0xff;
  102. header->reserved1 = (tmp32 >> 16) & 0xffff;
  103. header->reserved2 = pci_read_config(bus, slot, func, 0x38);
  104. tmp32 = pci_read_config(bus, slot, func, 0x3c);
  105. header->Interrupt_Line = tmp32 & 0xff;
  106. header->Interrupt_PIN = (tmp32 >> 8) & 0xff;
  107. header->Min_Grant = (tmp32 >> 16) & 0xff;
  108. header->Max_Latency = (tmp32 >> 24) & 0xff;
  109. }
  110. /**
  111. * @brief 读取type为0x1的pci_to_pci_bridge的header
  112. * 本函数只应被 pci_read_header()调用
  113. * @param header 返回的header
  114. * @param bus 总线号
  115. * @param slot 插槽号
  116. * @param func 功能号
  117. */
  118. static void pci_read_pci_to_pci_bridge_header(struct pci_device_structure_pci_to_pci_bridge_t *header, uchar bus, uchar slot, uchar func)
  119. {
  120. uint32_t tmp32;
  121. header->BAR0 = pci_read_config(bus, slot, func, 0x10);
  122. header->BAR1 = pci_read_config(bus, slot, func, 0x14);
  123. tmp32 = pci_read_config(bus, slot, func, 0x18);
  124. header->Primary_Bus_Number = tmp32 & 0xff;
  125. header->Secondary_Bus_Number = (tmp32 >> 8) & 0xff;
  126. header->Subordinate_Bus_Number = (tmp32 >> 16) & 0xff;
  127. header->Secondary_Latency_Timer = (tmp32 >> 24) & 0xff;
  128. tmp32 = pci_read_config(bus, slot, func, 0x1c);
  129. header->io_base = tmp32 & 0xff;
  130. header->io_limit = (tmp32 >> 8) & 0xff;
  131. header->Secondary_Status = (tmp32 >> 16) & 0xffff;
  132. tmp32 = pci_read_config(bus, slot, func, 0x20);
  133. header->Memory_Base = tmp32 & 0xffff;
  134. header->Memory_Limit = (tmp32 >> 16) & 0xffff;
  135. tmp32 = pci_read_config(bus, slot, func, 0x24);
  136. header->Prefetchable_Memory_Base = tmp32 & 0xffff;
  137. header->Prefetchable_Memory_Limit = (tmp32 >> 16) & 0xffff;
  138. header->Prefetchable_Base_Upper_32_Bits = pci_read_config(bus, slot, func, 0x28);
  139. header->Prefetchable_Limit_Upper_32_Bits = pci_read_config(bus, slot, func, 0x2c);
  140. tmp32 = pci_read_config(bus, slot, func, 0x30);
  141. header->io_Base_Upper_16_Bits = tmp32 & 0xffff;
  142. header->io_Limit_Upper_16_Bits = (tmp32 >> 16) & 0xffff;
  143. tmp32 = pci_read_config(bus, slot, func, 0x34);
  144. header->Capability_Pointer = tmp32 & 0xff;
  145. header->reserved0 = (tmp32 >> 8) & 0xff;
  146. header->reserved1 = (tmp32 >> 16) & 0xffff;
  147. header->Expansion_ROM_base_address = pci_read_config(bus, slot, func, 0x38);
  148. tmp32 = pci_read_config(bus, slot, func, 0x3c);
  149. header->Interrupt_Line = tmp32 & 0xff;
  150. header->Interrupt_PIN = (tmp32 >> 8) & 0xff;
  151. header->Bridge_Control = (tmp32 >> 16) & 0xffff;
  152. }
  153. /**
  154. * @brief 读取type为0x2的pci_to_cardbus_bridge的header
  155. * 本函数只应被 pci_read_header()调用
  156. * @param header 返回的header
  157. * @param bus 总线号
  158. * @param slot 插槽号
  159. * @param func 功能号
  160. */
  161. static void pci_read_pci_to_cardbus_bridge_header(struct pci_device_structure_pci_to_cardbus_bridge_t *header, uchar bus, uchar slot, uchar func)
  162. {
  163. uint32_t tmp32;
  164. header->CardBus_Socket_ExCa_base_address = pci_read_config(bus, slot, func, 0x10);
  165. tmp32 = pci_read_config(bus, slot, func, 0x14);
  166. header->Offset_of_capabilities_list = tmp32 & 0xff;
  167. header->Reserved = (tmp32 >> 8) & 0xff;
  168. header->Secondary_status = (tmp32 >> 16) & 0xff;
  169. tmp32 = pci_read_config(bus, slot, func, 0x18);
  170. header->PCI_bus_number = tmp32 & 0xff;
  171. header->CardBus_bus_number = (tmp32 >> 8) & 0xff;
  172. header->Subordinate_bus_number = (tmp32 >> 16) & 0xff;
  173. header->CardBus_latency_timer = (tmp32 >> 24) & 0xff;
  174. header->Memory_Base_Address0 = pci_read_config(bus, slot, func, 0x1c);
  175. header->Memory_Limit0 = pci_read_config(bus, slot, func, 0x20);
  176. header->Memory_Base_Address1 = pci_read_config(bus, slot, func, 0x24);
  177. header->Memory_Limit1 = pci_read_config(bus, slot, func, 0x28);
  178. header->IO_Base_Address0 = pci_read_config(bus, slot, func, 0x2c);
  179. header->IO_Limit0 = pci_read_config(bus, slot, func, 0x30);
  180. header->IO_Base_Address1 = pci_read_config(bus, slot, func, 0x34);
  181. header->IO_Limit1 = pci_read_config(bus, slot, func, 0x38);
  182. tmp32 = pci_read_config(bus, slot, func, 0x3c);
  183. header->Interrupt_Line = tmp32 & 0xff;
  184. header->Interrupt_PIN = (tmp32 >> 8) & 0xff;
  185. header->Bridge_Control = (tmp32 >> 16) & 0xffff;
  186. tmp32 = pci_read_config(bus, slot, func, 0x40);
  187. header->Subsystem_Device_ID = tmp32 & 0xffff;
  188. header->Subsystem_Vendor_ID = (tmp32 >> 16) & 0xffff;
  189. header->PC_Card_legacy_mode_base_address_16_bit = pci_read_config(bus, slot, func, 0x44);
  190. }
  191. /**
  192. * @brief 读取pci设备标头
  193. *
  194. * @param type 标头类型
  195. * @param bus 总线号
  196. * @param slot 插槽号
  197. * @param func 功能号
  198. * @param add_to_list 添加到链表
  199. * @return 返回的header
  200. */
  201. void *pci_read_header(int *type, uchar bus, uchar slot, uchar func, bool add_to_list)
  202. {
  203. struct pci_device_structure_header_t *common_header = (struct pci_device_structure_header_t *)kmalloc(127, 0);
  204. common_header->bus = bus;
  205. common_header->device = slot;
  206. common_header->func = func;
  207. uint32_t tmp32;
  208. // 先读取公共header
  209. tmp32 = pci_read_config(bus, slot, func, 0x0);
  210. common_header->Vendor_ID = tmp32 & 0xffff;
  211. common_header->Device_ID = (tmp32 >> 16) & 0xffff;
  212. tmp32 = pci_read_config(bus, slot, func, 0x4);
  213. common_header->Command = tmp32 & 0xffff;
  214. common_header->Status = (tmp32 >> 16) & 0xffff;
  215. tmp32 = pci_read_config(bus, slot, func, 0x8);
  216. common_header->RevisionID = tmp32 & 0xff;
  217. common_header->ProgIF = (tmp32 >> 8) & 0xff;
  218. common_header->SubClass = (tmp32 >> 16) & 0xff;
  219. common_header->Class_code = (tmp32 >> 24) & 0xff;
  220. tmp32 = pci_read_config(bus, slot, func, 0xc);
  221. common_header->CacheLineSize = tmp32 & 0xff;
  222. common_header->LatencyTimer = (tmp32 >> 8) & 0xff;
  223. common_header->HeaderType = (tmp32 >> 16) & 0xff;
  224. common_header->BIST = (tmp32 >> 24) & 0xff;
  225. void *ret;
  226. if (common_header->Vendor_ID == 0xffff)
  227. {
  228. *type = E_DEVICE_INVALID;
  229. kfree(common_header);
  230. return NULL;
  231. }
  232. // 根据公共头部,判断该结构所属的类型
  233. switch (common_header->HeaderType)
  234. {
  235. case 0x0: // general device
  236. ret = common_header;
  237. pci_read_general_device_header((struct pci_device_structure_general_device_t *)ret, bus, slot, func);
  238. if (add_to_list)
  239. ADD_DEVICE_STRUCT_TO_LIST(((struct pci_device_structure_general_device_t *)ret));
  240. *type = 0x0;
  241. return ret;
  242. break;
  243. case 0x1:
  244. ret = common_header;
  245. pci_read_pci_to_pci_bridge_header((struct pci_device_structure_pci_to_pci_bridge_t *)ret, bus, slot, func);
  246. if (add_to_list)
  247. ADD_DEVICE_STRUCT_TO_LIST(((struct pci_device_structure_pci_to_pci_bridge_t *)ret));
  248. *type = 0x1;
  249. return ret;
  250. break;
  251. case 0x2:
  252. ret = common_header;
  253. pci_read_pci_to_cardbus_bridge_header((struct pci_device_structure_pci_to_cardbus_bridge_t *)ret, bus, slot, func);
  254. if (add_to_list)
  255. ADD_DEVICE_STRUCT_TO_LIST(((struct pci_device_structure_pci_to_cardbus_bridge_t *)ret));
  256. *type = 0x2;
  257. return ret;
  258. break;
  259. default: // 错误的头类型 这里不应该被执行
  260. // kerror("PCI->pci_read_header(): Invalid header type.");
  261. *type = E_WRONG_HEADER_TYPE;
  262. // kerror("vendor id=%#010lx", common_header->Vendor_ID);
  263. // kerror("header type = %d", common_header->HeaderType);
  264. kfree(common_header);
  265. return NULL;
  266. break;
  267. }
  268. }
  269. static void pci_checkFunction(uint8_t bus, uint8_t device, uint8_t function)
  270. {
  271. int header_type;
  272. struct pci_device_structure_header_t *header = pci_read_header(&header_type, bus, device, function, true);
  273. if (header_type == E_WRONG_HEADER_TYPE)
  274. {
  275. // kerror("pci_checkFunction(): wrong header type!");
  276. // 此处内存已经在read header函数里面释放,不用重复释放
  277. return;
  278. }
  279. // header = ((struct pci_device_structure_general_device_t *)raw_header)->header;
  280. if ((header->Class_code == 0x6) && (header->SubClass == 0x4))
  281. {
  282. uint8_t SecondaryBus = ((struct pci_device_structure_pci_to_pci_bridge_t *)header)->Secondary_Bus_Number;
  283. pci_checkBus(SecondaryBus);
  284. }
  285. }
  286. static int pci_checkDevice(uint8_t bus, uint8_t device)
  287. {
  288. int header_type;
  289. struct pci_device_structure_header_t *header = pci_read_header(&header_type, bus, device, 0, false);
  290. if (header_type == E_WRONG_HEADER_TYPE)
  291. {
  292. // 此处内存已经在read header函数里面释放,不用重复释放
  293. return E_WRONG_HEADER_TYPE;
  294. }
  295. if (header_type == E_DEVICE_INVALID)
  296. {
  297. // kerror("DEVICE INVALID");
  298. return E_DEVICE_INVALID;
  299. }
  300. uint16_t vendorID = header->Vendor_ID;
  301. if (vendorID == 0xffff) // 设备不存在
  302. {
  303. kfree(header);
  304. return E_DEVICE_INVALID;
  305. }
  306. pci_checkFunction(bus, device, 0);
  307. header_type = header->HeaderType;
  308. if ((header_type & 0x80) != 0)
  309. {
  310. kdebug("Multi func device");
  311. // 这是一个多function的设备,因此查询剩余的function
  312. for (uint8_t func = 1; func < 8; ++func)
  313. {
  314. struct pci_device_structure_header_t *tmp_header;
  315. tmp_header = (struct pci_device_structure_header_t *)pci_read_header(&header_type, bus, device, func, false);
  316. if (tmp_header->Vendor_ID != 0xffff)
  317. pci_checkFunction(bus, device, func);
  318. // 释放内存
  319. kfree(tmp_header);
  320. }
  321. }
  322. kfree(header);
  323. return 0;
  324. }
  325. static void pci_checkBus(uint8_t bus)
  326. {
  327. for (uint8_t device = 0; device < 32; ++device)
  328. {
  329. pci_checkDevice(bus, device);
  330. }
  331. }
  332. /**
  333. * @brief 扫描所有pci总线上的所有设备
  334. *
  335. */
  336. void pci_checkAllBuses()
  337. {
  338. kinfo("Checking all devices in PCI bus...");
  339. int header_type;
  340. struct pci_device_structure_header_t *header = pci_read_header(&header_type, 0, 0, 0, false);
  341. if (header_type == E_WRONG_HEADER_TYPE)
  342. {
  343. kBUG("pci_checkAllBuses(): wrong header type!");
  344. // 此处内存已经在read header函数里面释放,不用重复释放
  345. return;
  346. }
  347. header_type = header->HeaderType;
  348. if ((header_type & 0x80) == 0) // Single pci host controller
  349. {
  350. pci_checkBus(0);
  351. }
  352. else
  353. {
  354. // Multiple PCI host controller
  355. // 那么总线0,设备0,功能1则是总线1的pci主机控制器,以此类推
  356. struct pci_device_structure_header_t *tmp_header;
  357. for (uint8_t func = 0; func < 8; ++func)
  358. {
  359. tmp_header = (struct pci_device_structure_header_t *)pci_read_header(&header_type, 0, 0, func, false);
  360. if (header->Vendor_ID != 0xffff) // @todo 这里的判断条件可能有点问题
  361. {
  362. kfree(tmp_header);
  363. break;
  364. }
  365. pci_checkBus(func);
  366. kfree(tmp_header);
  367. }
  368. }
  369. kfree(header);
  370. }
  371. void pci_init()
  372. {
  373. kinfo("Initializing PCI bus...");
  374. pci_checkAllBuses();
  375. kinfo("Total pci device and function num = %d", count_device_list);
  376. struct pci_device_structure_header_t *ptr = container_of(pci_device_structure_list, struct pci_device_structure_header_t, list);
  377. for (int i = 0; i < count_device_list; ++i)
  378. {
  379. if (ptr->HeaderType == 0x0)
  380. {
  381. if (ptr->Status & 0x10)
  382. {
  383. kinfo("[ pci device %d ] class code = %d\tsubclass=%d\tstatus=%#010lx\tcap_pointer=%#010lx", i, ptr->Class_code, ptr->SubClass, ptr->Status, ((struct pci_device_structure_general_device_t *)ptr)->Capabilities_Pointer);
  384. uint32_t tmp = pci_read_config(ptr->bus, ptr->device, ptr->func, ((struct pci_device_structure_general_device_t *)ptr)->Capabilities_Pointer);
  385. kdebug("cap+0x0 = %#010lx", tmp);
  386. }
  387. else
  388. {
  389. kinfo("[ pci device %d ] class code = %d\tsubclass=%d\tstatus=%#010lx\t", i, ptr->Class_code, ptr->SubClass, ptr->Status);
  390. }
  391. }
  392. else if (ptr->HeaderType == 0x1)
  393. {
  394. if (ptr->Status & 0x10)
  395. {
  396. kinfo("[ pci device %d ] class code = %d\tsubclass=%d\tstatus=%#010lx\tcap_pointer=%#010lx", i, ptr->Class_code, ptr->SubClass, ptr->Status, ((struct pci_device_structure_pci_to_pci_bridge_t *)ptr)->Capability_Pointer);
  397. }
  398. else
  399. {
  400. kinfo("[ pci device %d ] class code = %d\tsubclass=%d\tstatus=%#010lx\t", i, ptr->Class_code, ptr->SubClass, ptr->Status);
  401. }
  402. }
  403. else if (ptr->HeaderType == 0x2)
  404. {
  405. kinfo("[ pci device %d ] class code = %d\tsubclass=%d\tstatus=%#010lx\t", i, ptr->Class_code, ptr->SubClass, ptr->Status);
  406. }
  407. ptr = container_of(list_next(&(ptr->list)), struct pci_device_structure_header_t, list);
  408. }
  409. kinfo("PCI bus initialized.")
  410. }
  411. /**
  412. * @brief 启用 Message Signaled Interrupts
  413. *
  414. * @param header 设备header
  415. * @param vector 中断向量号
  416. * @param processor 要投递到的处理器
  417. * @param edge_trigger 是否边缘触发
  418. * @param assert 是否高电平触发
  419. *
  420. * @return 返回码
  421. */
  422. int pci_enable_msi(void *header, uint8_t vector, uint32_t processor, uint8_t edge_trigger, uint8_t assert)
  423. {
  424. struct pci_device_structure_header_t *ptr = (struct pci_device_structure_header_t *)header;
  425. uint32_t cap_ptr;
  426. uint32_t tmp;
  427. uint16_t message_control;
  428. uint64_t message_addr;
  429. switch (ptr->HeaderType)
  430. {
  431. case 0x00: // general device
  432. if (!(ptr->Status & 0x10))
  433. return E_NOT_SUPPORT_MSI;
  434. cap_ptr = ((struct pci_device_structure_general_device_t *)ptr)->Capabilities_Pointer;
  435. tmp = pci_read_config(ptr->bus, ptr->device, ptr->func, cap_ptr); // 读取cap+0x0处的值
  436. message_control = (tmp >> 16) & 0xffff;
  437. if (tmp & 0xff != 0x5)
  438. return E_NOT_SUPPORT_MSI;
  439. // 写入message address
  440. message_addr = pci_get_arch_msi_message_address(processor); // 获取message address
  441. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0x4, (uint32_t)(message_addr & 0xffffffff));
  442. if (message_control & (1 << 7)) // 64位
  443. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0x8, (uint32_t)((message_addr >> 32) & 0xffffffff));
  444. // 写入message data
  445. tmp = pci_get_arch_msi_message_data(vector, processor, edge_trigger, assert);
  446. if (message_control & (1 << 7)) // 64位
  447. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0xc, tmp);
  448. else
  449. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0x8, tmp);
  450. // 使能msi
  451. tmp = pci_read_config(ptr->bus, ptr->device, ptr->func, cap_ptr); // 读取cap+0x0处的值
  452. tmp |= (1 << 16);
  453. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr, tmp);
  454. break;
  455. case 0x01: // pci to pci bridge
  456. if (!(ptr->Status & 0x10))
  457. return E_NOT_SUPPORT_MSI;
  458. cap_ptr = ((struct pci_device_structure_pci_to_pci_bridge_t *)ptr)->Capability_Pointer;
  459. tmp = pci_read_config(ptr->bus, ptr->device, ptr->func, cap_ptr); // 读取cap+0x0处的值
  460. message_control = (tmp >> 16) & 0xffff;
  461. if (tmp & 0xff != 0x5)
  462. return E_NOT_SUPPORT_MSI;
  463. // 写入message address
  464. message_addr = pci_get_arch_msi_message_address(processor); // 获取message address
  465. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0x4, (uint32_t)(message_addr & 0xffffffff));
  466. if (message_control & (1 << 7)) // 64位
  467. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0x8, (uint32_t)((message_addr >> 32) & 0xffffffff));
  468. // 写入message data
  469. tmp = pci_get_arch_msi_message_data(vector, processor, edge_trigger, assert);
  470. if (message_control & (1 << 7)) // 64位
  471. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0xc, tmp);
  472. else
  473. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr + 0x8, tmp);
  474. // 使能msi
  475. tmp = pci_read_config(ptr->bus, ptr->device, ptr->func, cap_ptr); // 读取cap+0x0处的值
  476. tmp |= (1 << 16);
  477. pci_write_config(ptr->bus, ptr->device, ptr->func, cap_ptr, tmp);
  478. break;
  479. case 0x02: // pci to card bus bridge
  480. return E_NOT_SUPPORT_MSI;
  481. break;
  482. default: // 不应该到达这里
  483. return E_WRONG_HEADER_TYPE;
  484. break;
  485. }
  486. return 0;
  487. }
  488. /**
  489. * @brief 获取 device structure
  490. *
  491. * @param class_code
  492. * @param sub_class
  493. * @param res 返回的结果数组
  494. */
  495. void pci_get_device_structure(uint8_t class_code, uint8_t sub_class, struct pci_device_structure_header_t *res[], uint32_t *count_res)
  496. {
  497. struct pci_device_structure_header_t *ptr = container_of(pci_device_structure_list, struct pci_device_structure_header_t, list);
  498. *count_res = 0;
  499. for (int i = 0; i < count_device_list; ++i)
  500. {
  501. if ((ptr->Class_code == 1) && (ptr->SubClass == 6))
  502. {
  503. kdebug("[%d] class_code=%d, sub_class=%d, progIF=%d", i, ptr->Class_code, ptr->SubClass, ptr->ProgIF);
  504. res[*count_res] = ptr;
  505. ++(*count_res);
  506. }
  507. ptr = container_of(list_next(&(ptr->list)), struct pci_device_structure_header_t, list);
  508. }
  509. }