xhci.c 16 KB

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  1. #include "xhci.h"
  2. #include <common/kprint.h>
  3. #include <debug/bug.h>
  4. #include <process/spinlock.h>
  5. #include <mm/mm.h>
  6. #include <debug/traceback/traceback.h>
  7. #include <common/time.h>
  8. spinlock_t xhci_controller_init_lock; // xhci控制器初始化锁(在usb_init中被初始化)
  9. static int xhci_ctrl_count = 0; // xhci控制器计数
  10. static struct xhci_host_controller_t xhci_hc[XHCI_MAX_HOST_CONTROLLERS] = {0};
  11. /*
  12. 注意!!!
  13. 尽管采用MMI/O的方式访问寄存器,但是对于指定大小的寄存器,
  14. 在发起读请求的时候,只能从寄存器的起始地址位置开始读取。
  15. 例子:不能在一个32bit的寄存器中的偏移量8的位置开始读取1个字节
  16. 这种情况下,我们必须从32bit的寄存器的0地址处开始读取32bit,然后通过移位的方式得到其中的字节。
  17. */
  18. #define xhci_read_cap_reg8(id, offset) (*(uint8_t *)(xhci_hc[id].vbase + offset))
  19. #define xhci_get_ptr_cap_reg8(id, offset) ((uint8_t *)(xhci_hc[id].vbase + offset))
  20. #define xhci_write_cap_reg8(id, offset, value) (*(uint8_t *)(xhci_hc[id].vbase + offset) = (uint8_t)value)
  21. #define xhci_read_cap_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase + offset))
  22. #define xhci_get_ptr_cap_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase + offset))
  23. #define xhci_write_cap_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase + offset) = (uint32_t)value)
  24. #define xhci_read_cap_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase + offset))
  25. #define xhci_get_ptr_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase + offset))
  26. #define xhci_write_cap_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase + offset) = (uint64_t)value)
  27. #define xhci_read_op_reg8(id, offset) (*(uint8_t *)(xhci_hc[id].vbase_op + offset))
  28. #define xhci_get_ptr_op_reg8(id, offset) ((uint8_t *)(xhci_hc[id].vbase_op + offset))
  29. #define xhci_write_op_reg8(id, offset, value) (*(uint8_t *)(xhci_hc[id].vbase_op + offset) = (uint8_t)value)
  30. #define xhci_read_op_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase_op + offset))
  31. #define xhci_get_ptr_op_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase_op + offset))
  32. #define xhci_write_op_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase_op + offset) = (uint32_t)value)
  33. #define xhci_read_op_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase_op + offset))
  34. #define xhci_get_ptr_op_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase_op + offset))
  35. #define xhci_write_op_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase_op + offset) = (uint64_t)value)
  36. /**
  37. * @brief 判断端口信息
  38. * @param cid 主机控制器id
  39. * @param pid 端口id
  40. */
  41. #define XHCI_PORT_IS_USB2(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_INFO) == XHCI_PROTOCOL_USB2)
  42. #define XHCI_PORT_IS_USB3(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_INFO) == XHCI_PROTOCOL_USB3)
  43. #define XHCI_PORT_IS_USB2_HSO(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_HSO) == XHCI_PROTOCOL_HSO)
  44. #define XHCI_PORT_HAS_PAIR(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_HAS_PAIR) == XHCI_PROTOCOL_HAS_PAIR)
  45. #define XHCI_PORT_IS_ACTIVE(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_ACTIVE) == XHCI_PROTOCOL_ACTIVE)
  46. #define FAIL_ON(value, to) \
  47. do \
  48. { \
  49. if (unlikely(value != 0)) \
  50. goto to; \
  51. } while (0)
  52. /**
  53. * @brief 在controller数组之中寻找可用插槽
  54. *
  55. * 注意:该函数只能被获得init锁的进程所调用
  56. * @return int 可用id(无空位时返回-1)
  57. */
  58. static int xhci_hc_find_available_id()
  59. {
  60. if (unlikely(xhci_ctrl_count >= XHCI_MAX_HOST_CONTROLLERS))
  61. return -1;
  62. for (int i = 0; i < XHCI_MAX_HOST_CONTROLLERS; ++i)
  63. {
  64. if (xhci_hc[i].pci_dev_hdr == NULL)
  65. return i;
  66. }
  67. return -1;
  68. }
  69. /**
  70. * @brief 停止xhci主机控制器
  71. *
  72. * @param id 主机控制器id
  73. * @return int
  74. */
  75. static int xhci_hc_stop(int id)
  76. {
  77. // 判断是否已经停止
  78. if (unlikely((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 1))
  79. return 0;
  80. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, 0x00000000);
  81. char timeout = 17;
  82. while ((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 0)
  83. {
  84. usleep(1000);
  85. if (--timeout == 0)
  86. return -ETIMEDOUT;
  87. }
  88. return 0;
  89. }
  90. /**
  91. * @brief reset xHCI主机控制器
  92. *
  93. * @param id 主机控制器id
  94. * @return int
  95. */
  96. static int xhci_hc_reset(int id)
  97. {
  98. int retval = 0;
  99. // 判断HCHalted是否置位
  100. if ((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 0)
  101. {
  102. // 未置位,需要先尝试停止usb主机控制器
  103. retval = xhci_hc_stop(id);
  104. if (unlikely(retval))
  105. return retval;
  106. }
  107. int timeout = 500; // wait 500ms
  108. // reset
  109. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, (1 << 1));
  110. while (xhci_read_op_reg32(id, XHCI_OPS_USBCMD) & (1 << 1))
  111. {
  112. usleep(1000);
  113. if (--timeout == 0)
  114. return -ETIMEDOUT;
  115. }
  116. // kdebug("reset done!, timeout=%d", timeout);
  117. return retval;
  118. }
  119. /**
  120. * @brief 停止指定xhci控制器的legacy support
  121. *
  122. * @param id 控制器id
  123. * @return int
  124. */
  125. static int xhci_hc_stop_legacy(int id)
  126. {
  127. uint64_t current_offset = xhci_hc[id].ext_caps_off;
  128. do
  129. {
  130. // 判断当前entry是否为legacy support entry
  131. if (xhci_read_cap_reg8(id, current_offset) == XHCI_XECP_ID_LEGACY)
  132. {
  133. // 接管控制权
  134. xhci_write_cap_reg32(id, current_offset, xhci_read_cap_reg32(id, current_offset) | XHCI_XECP_LEGACY_OS_OWNED);
  135. // 等待响应完成
  136. int timeout = XHCI_XECP_LEGACY_TIMEOUT;
  137. while ((xhci_read_cap_reg32(id, current_offset) & XHCI_XECP_LEGACY_OWNING_MASK) != XHCI_XECP_LEGACY_OS_OWNED)
  138. {
  139. usleep(1000);
  140. if (--timeout == 0)
  141. {
  142. kerror("The BIOS doesn't stop legacy support.");
  143. return -ETIMEDOUT;
  144. }
  145. }
  146. // 处理完成
  147. return 0;
  148. }
  149. // 读取下一个entry的偏移增加量
  150. int next_off = ((xhci_read_cap_reg32(id, current_offset) & 0xff00) >> 8) << 2;
  151. // 将指针跳转到下一个entry
  152. current_offset = next_off ? (current_offset + next_off) : 0;
  153. } while (current_offset);
  154. // 当前controller不存在legacy支持,也问题不大,不影响
  155. return 0;
  156. }
  157. /**
  158. * @brief
  159. *
  160. * @return uint32_t
  161. */
  162. /**
  163. * @brief 在Ex capability list中寻找符合指定的协议号的寄存器offset、count、flag信息
  164. *
  165. * @param id 主机控制器id
  166. * @param list_off 列表项位置距离控制器虚拟基地址的偏移量
  167. * @param version 要寻找的端口版本号(2或3)
  168. * @param offset 返回的 Compatible Port Offset
  169. * @param count 返回的 Compatible Port Count
  170. * @param protocol_flag 返回的与协议相关的flag
  171. * @return uint32_t 下一个列表项的偏移量
  172. */
  173. static uint32_t xhci_hc_get_protocol_offset(int id, uint32_t list_off, const int version, uint32_t *offset, uint32_t *count, uint16_t *protocol_flag)
  174. {
  175. if (count)
  176. *count = 0;
  177. do
  178. {
  179. uint32_t dw0 = xhci_read_cap_reg32(id, list_off);
  180. uint32_t next_list_off = (dw0 >> 8) & 0xff;
  181. next_list_off = next_list_off ? (list_off + (next_list_off << 2)) : 0;
  182. if ((dw0 & 0xff) == XHCI_XECP_ID_PROTOCOL && ((dw0 & 0xff000000) >> 24) == version)
  183. {
  184. uint32_t dw2 = xhci_read_cap_reg32(id, list_off + 8);
  185. if (offset != NULL)
  186. *offset = (uint32_t)(dw2 & 0xff);
  187. if (count != NULL)
  188. *count = (uint32_t)((dw2 & 0xff00) >> 8);
  189. if (protocol_flag != NULL)
  190. *protocol_flag = (uint16_t)((dw2 >> 16) & 0xffff);
  191. return next_list_off;
  192. }
  193. list_off = next_list_off;
  194. } while (list_off);
  195. return 0;
  196. }
  197. /**
  198. * @brief 配对xhci主机控制器的usb2、usb3端口
  199. *
  200. * @param id 主机控制器id
  201. * @return int 返回码
  202. */
  203. static int xhci_hc_pair_ports(int id)
  204. {
  205. struct xhci_caps_HCCPARAMS1_reg_t hcc1;
  206. struct xhci_caps_HCCPARAMS2_reg_t hcc2;
  207. struct xhci_caps_HCSPARAMS1_reg_t hcs1;
  208. struct xhci_caps_HCSPARAMS2_reg_t hcs2;
  209. memcpy(&hcc1, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCCPARAMS1), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  210. memcpy(&hcc2, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCCPARAMS2), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  211. memcpy(&hcs1, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCSPARAMS1), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  212. memcpy(&hcs2, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCSPARAMS2), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  213. // 从hcs1获取端口数量
  214. xhci_hc[id].port_num = hcs1.max_ports;
  215. // 找到所有的端口并标记其端口信息
  216. xhci_hc[id].port_num_u2 = 0;
  217. xhci_hc[id].port_num_u3 = 0;
  218. uint32_t next_off = xhci_hc[id].ext_caps_off;
  219. uint32_t offset, cnt;
  220. uint16_t protocol_flags;
  221. // 寻找所有的usb2端口
  222. while (next_off)
  223. {
  224. next_off = xhci_hc_get_protocol_offset(id, next_off, 2, &offset, &cnt, &protocol_flags);
  225. if (cnt)
  226. {
  227. for (int i = 0; i < cnt; ++i)
  228. {
  229. xhci_hc[id].ports[offset + i].offset = ++xhci_hc[id].port_num_u2;
  230. xhci_hc[id].ports[offset + i].flags = XHCI_PROTOCOL_USB2;
  231. // usb2 high speed only
  232. if (protocol_flags & 2)
  233. xhci_hc[id].ports[offset + i].flags |= XHCI_PROTOCOL_HSO;
  234. }
  235. }
  236. }
  237. // 寻找所有的usb3端口
  238. next_off = xhci_hc[id].ext_caps_off;
  239. while (next_off)
  240. {
  241. next_off = xhci_hc_get_protocol_offset(id, next_off, 3, &offset, &cnt, &protocol_flags);
  242. if (cnt)
  243. {
  244. for (int i = 0; i < cnt; ++i)
  245. {
  246. xhci_hc[id].ports[offset + i].offset = ++xhci_hc[id].port_num_u3;
  247. xhci_hc[id].ports[offset + i].flags = XHCI_PROTOCOL_USB3;
  248. }
  249. }
  250. }
  251. // 将对应的USB2端口和USB3端口进行配对
  252. for (int i = 1; i <= xhci_hc[id].port_num; ++i)
  253. {
  254. for (int j = i; j <= xhci_hc[id].port_num; ++j)
  255. {
  256. if (unlikely(i == j))
  257. continue;
  258. if ((xhci_hc[id].ports[i].offset == xhci_hc[id].ports[j].offset) &&
  259. ((xhci_hc[id].ports[i].flags & XHCI_PROTOCOL_INFO) != (xhci_hc[id].ports[j].flags & XHCI_PROTOCOL_INFO)))
  260. {
  261. xhci_hc[id].ports[i].paired_port_num = j;
  262. xhci_hc[id].ports[i].flags |= XHCI_PROTOCOL_HAS_PAIR;
  263. xhci_hc[id].ports[j].paired_port_num = i;
  264. xhci_hc[id].ports[j].flags |= XHCI_PROTOCOL_HAS_PAIR;
  265. }
  266. }
  267. }
  268. // 标记所有的usb3端口为激活状态
  269. for (int i = 1; i <= xhci_hc[id].port_num; ++i)
  270. {
  271. if (XHCI_PORT_IS_USB3(id, i) ||
  272. (XHCI_PORT_IS_USB2(id, i) && (!XHCI_PORT_HAS_PAIR(id, i))))
  273. xhci_hc[id].ports[i].flags |= XHCI_PROTOCOL_ACTIVE;
  274. }
  275. kinfo("Found %d ports on root hub, usb2 ports:%d, usb3 ports:%d", xhci_hc[id].port_num, xhci_hc[id].port_num_u2, xhci_hc[id].port_num_u3);
  276. /*
  277. // 打印配对结果
  278. for (int i = 1; i <= xhci_hc[id].port_num; ++i)
  279. {
  280. if (XHCI_PORT_IS_USB3(id, i))
  281. {
  282. kdebug("USB3 port %d, offset=%d, pair with usb2 port %d, current port is %s", i, xhci_hc[id].ports[i].offset,
  283. xhci_hc[id].ports[i].paired_port_num, XHCI_PORT_IS_ACTIVE(id, i) ? "active" : "inactive");
  284. }
  285. else if (XHCI_PORT_IS_USB2(id, i) && (!XHCI_PORT_HAS_PAIR(id, i))) // 单独的2.0接口
  286. {
  287. kdebug("Stand alone USB2 port %d, offset=%d, current port is %s", i, xhci_hc[id].ports[i].offset,
  288. XHCI_PORT_IS_ACTIVE(id, i) ? "active" : "inactive");
  289. }
  290. else if (XHCI_PORT_IS_USB2(id, i))
  291. {
  292. kdebug("USB2 port %d, offset=%d, current port is %s, has pair=%s", i, xhci_hc[id].ports[i].offset,
  293. XHCI_PORT_IS_ACTIVE(id, i) ? "active" : "inactive", XHCI_PORT_HAS_PAIR(id, i)?"true":"false");
  294. }
  295. }
  296. */
  297. return 0;
  298. }
  299. /**
  300. * @brief 初始化xhci控制器
  301. *
  302. * @param header 指定控制器的pci device头部
  303. */
  304. void xhci_init(struct pci_device_structure_general_device_t *dev_hdr)
  305. {
  306. if (xhci_ctrl_count >= XHCI_MAX_HOST_CONTROLLERS)
  307. {
  308. kerror("Initialize xhci controller failed: exceed the limit of max controllers.");
  309. return;
  310. }
  311. spin_lock(&xhci_controller_init_lock);
  312. kinfo("Initializing xhci host controller: bus=%#02x, device=%#02x, func=%#02x, VendorID=%#04x, irq_line=%d, irq_pin=%d", dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, dev_hdr->header.Vendor_ID, dev_hdr->Interrupt_Line, dev_hdr->Interrupt_PIN);
  313. int cid = xhci_hc_find_available_id();
  314. if (cid < 0)
  315. {
  316. kerror("Initialize xhci controller failed: exceed the limit of max controllers.");
  317. goto failed_exceed_max;
  318. }
  319. memset(&xhci_hc[cid], 0, sizeof(struct xhci_host_controller_t));
  320. xhci_hc[cid].controller_id = cid;
  321. xhci_hc[cid].pci_dev_hdr = dev_hdr;
  322. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0x4, 0x0006); // mem I/O access enable and bus master enable
  323. // 为当前控制器映射寄存器地址空间
  324. xhci_hc[cid].vbase = SPECIAL_MEMOEY_MAPPING_VIRT_ADDR_BASE + XHCI_MAPPING_OFFSET + 65536 * xhci_hc[cid].controller_id;
  325. // kdebug("dev_hdr->BAR0 & (~0xf)=%#018lx", dev_hdr->BAR0 & (~0xf));
  326. mm_map_phys_addr(xhci_hc[cid].vbase, dev_hdr->BAR0 & (~0xf), 65536, PAGE_KERNEL_PAGE | PAGE_PWT | PAGE_PCD, true);
  327. // 读取xhci控制寄存器
  328. uint16_t iversion = *(uint16_t *)(xhci_hc[cid].vbase + XHCI_CAPS_HCIVERSION);
  329. uint32_t hcc1 = xhci_read_cap_reg32(cid, XHCI_CAPS_HCCPARAMS1);
  330. // 计算operational registers的地址
  331. xhci_hc[cid].vbase_op = xhci_hc[cid].vbase + xhci_read_cap_reg8(cid, XHCI_CAPS_CAPLENGTH);
  332. xhci_hc[cid].db_offset = xhci_read_cap_reg32(cid, XHCI_CAPS_DBOFF) & (~0x3); // bits [1:0] reserved
  333. xhci_hc[cid].rts_offset = xhci_read_cap_reg32(cid, XHCI_CAPS_RTSOFF) & (~0x1f); // bits [4:0] reserved.
  334. xhci_hc[cid].ext_caps_off = ((hcc1 & 0xffff0000) >> 16) * 4;
  335. xhci_hc[cid].context_size = (hcc1 & (1 << 2)) ? 64 : 32;
  336. if (iversion < 0x95)
  337. {
  338. kwarn("Unsupported/Unknowned xHCI controller version: %#06x. This may cause unexpected behavior.", iversion);
  339. }
  340. // if it is a Panther Point device, make sure sockets are xHCI controlled.
  341. if (((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0) & 0xffff) == 0x8086) &&
  342. ((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 2) & 0xffff) == 0x1E31) &&
  343. ((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 8) & 0xff) == 4))
  344. {
  345. kdebug("Is a Panther Point device");
  346. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0xd8, 0xffffffff);
  347. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0xd0, 0xffffffff);
  348. }
  349. // 重置xhci控制器
  350. FAIL_ON(xhci_hc_reset(cid), failed);
  351. FAIL_ON(xhci_hc_stop_legacy(cid), failed);
  352. FAIL_ON(xhci_hc_pair_ports(cid), failed);
  353. ++xhci_ctrl_count;
  354. spin_unlock(&xhci_controller_init_lock);
  355. return;
  356. failed:;
  357. // 取消地址映射
  358. mm_unmap(xhci_hc[cid].vbase, 65536);
  359. // 清空数组
  360. memset((void *)&xhci_hc[cid], 0, sizeof(struct xhci_host_controller_t));
  361. failed_exceed_max:;
  362. kerror("Failed to initialize controller: bus=%d, dev=%d, func=%d", dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func);
  363. spin_unlock(&xhci_controller_init_lock);
  364. }