xhci.c 38 KB

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  1. #include "xhci.h"
  2. #include <common/kprint.h>
  3. #include <debug/bug.h>
  4. #include <common/spinlock.h>
  5. #include <mm/mm.h>
  6. #include <mm/slab.h>
  7. #include <debug/traceback/traceback.h>
  8. #include <common/time.h>
  9. #include <exception/irq.h>
  10. #include <driver/interrupt/apic/apic.h>
  11. // 由于xhci寄存器读取需要对齐,因此禁用GCC优化选项
  12. #pragma GCC optimize("O0")
  13. spinlock_t xhci_controller_init_lock = {0}; // xhci控制器初始化锁(在usb_init中被初始化)
  14. static int xhci_ctrl_count = 0; // xhci控制器计数
  15. static struct xhci_host_controller_t xhci_hc[XHCI_MAX_HOST_CONTROLLERS] = {0};
  16. void xhci_hc_irq_enable(uint64_t irq_num);
  17. void xhci_hc_irq_disable(uint64_t irq_num);
  18. uint64_t xhci_hc_irq_install(uint64_t irq_num, void *arg);
  19. void xhci_hc_irq_uninstall(uint64_t irq_num);
  20. static int xhci_hc_find_available_id();
  21. static int xhci_hc_stop(int id);
  22. static int xhci_hc_reset(int id);
  23. static int xhci_hc_stop_legacy(int id);
  24. static int xhci_hc_start_sched(int id);
  25. static int xhci_hc_stop_sched(int id);
  26. static uint32_t xhci_hc_get_protocol_offset(int id, uint32_t list_off, const int version, uint32_t *offset, uint32_t *count, uint16_t *protocol_flag);
  27. static int xhci_hc_pair_ports(int id);
  28. static uint64_t xhci_create_ring(int trbs);
  29. static uint64_t xhci_create_event_ring(int trbs, uint64_t *ret_ring_addr);
  30. void xhci_hc_irq_handler(uint64_t irq_num, uint64_t cid, struct pt_regs *regs);
  31. static int xhci_hc_init_intr(int id);
  32. static int xhci_hc_start_ports(int id);
  33. static int xhci_send_command(int id, struct xhci_TRB_t *trb, const bool do_ring);
  34. hardware_intr_controller xhci_hc_intr_controller =
  35. {
  36. .enable = xhci_hc_irq_enable,
  37. .disable = xhci_hc_irq_disable,
  38. .install = xhci_hc_irq_install,
  39. .uninstall = xhci_hc_irq_uninstall,
  40. .ack = apic_local_apic_edge_ack,
  41. };
  42. /*
  43. 注意!!!
  44. 尽管采用MMI/O的方式访问寄存器,但是对于指定大小的寄存器,
  45. 在发起读请求的时候,只能从寄存器的起始地址位置开始读取。
  46. 例子:不能在一个32bit的寄存器中的偏移量8的位置开始读取1个字节
  47. 这种情况下,我们必须从32bit的寄存器的0地址处开始读取32bit,然后通过移位的方式得到其中的字节。
  48. */
  49. #define xhci_read_cap_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase + offset))
  50. #define xhci_get_ptr_cap_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase + offset))
  51. #define xhci_write_cap_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase + offset) = (uint32_t)value)
  52. #define xhci_read_cap_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase + offset))
  53. #define xhci_get_ptr_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase + offset))
  54. #define xhci_write_cap_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase + offset) = (uint64_t)value)
  55. #define xhci_read_op_reg8(id, offset) (*(uint8_t *)(xhci_hc[id].vbase_op + offset))
  56. #define xhci_get_ptr_op_reg8(id, offset) ((uint8_t *)(xhci_hc[id].vbase_op + offset))
  57. #define xhci_write_op_reg8(id, offset, value) (*(uint8_t *)(xhci_hc[id].vbase_op + offset) = (uint8_t)value)
  58. #define xhci_read_op_reg32(id, offset) (*(uint32_t *)(xhci_hc[id].vbase_op + offset))
  59. #define xhci_get_ptr_op_reg32(id, offset) ((uint32_t *)(xhci_hc[id].vbase_op + offset))
  60. #define xhci_write_op_reg32(id, offset, value) (*(uint32_t *)(xhci_hc[id].vbase_op + offset) = (uint32_t)value)
  61. #define xhci_read_op_reg64(id, offset) (*(uint64_t *)(xhci_hc[id].vbase_op + offset))
  62. #define xhci_get_ptr_op_reg64(id, offset) ((uint64_t *)(xhci_hc[id].vbase_op + offset))
  63. #define xhci_write_op_reg64(id, offset, value) (*(uint64_t *)(xhci_hc[id].vbase_op + offset) = (uint64_t)value)
  64. #define xhci_write_mem32(vaddr, value) (*(uint32_t *)(vaddr) = value)
  65. #define xhci_write_mem64(vaddr, value) (*(uint64_t *)(vaddr) = value)
  66. #define xhci_read_mem32(vaddr) (*(uint32_t *)(vaddr))
  67. #define xhci_read_mem64(vaddr) (*(uint64_t *)(vaddr))
  68. /**
  69. * @brief 计算中断寄存器组虚拟地址
  70. * @param id 主机控制器id
  71. * @param num xhci中断寄存器组号
  72. */
  73. #define xhci_calc_intr_vaddr(id, num) (xhci_hc[id].vbase + xhci_hc[id].rts_offset + XHCI_RT_IR0 + num * XHCI_IR_SIZE)
  74. /**
  75. * @brief 读取/写入中断寄存器
  76. * @param id 主机控制器id
  77. * @param num xhci中断寄存器组号
  78. * @param intr_offset 寄存器在当前寄存器组中的偏移量
  79. */
  80. #define xhci_read_intr_reg32(id, num, intr_offset) (*(uint32_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset))
  81. #define xhci_write_intr_reg32(id, num, intr_offset, value) (*(uint32_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset) = value)
  82. #define xhci_read_intr_reg64(id, num, intr_offset) (*(uint64_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset))
  83. #define xhci_write_intr_reg64(id, num, intr_offset, value) (*(uint64_t *)(xhci_calc_intr_vaddr(id, num) + intr_offset) = value)
  84. #define xhci_is_aligned64(addr) ((addr & 0x3f) == 0) // 是否64bytes对齐
  85. /**
  86. * @brief 判断端口信息
  87. * @param cid 主机控制器id
  88. * @param pid 端口id
  89. */
  90. #define XHCI_PORT_IS_USB2(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_INFO) == XHCI_PROTOCOL_USB2)
  91. #define XHCI_PORT_IS_USB3(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_INFO) == XHCI_PROTOCOL_USB3)
  92. #define XHCI_PORT_IS_USB2_HSO(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_HSO) == XHCI_PROTOCOL_HSO)
  93. #define XHCI_PORT_HAS_PAIR(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_HAS_PAIR) == XHCI_PROTOCOL_HAS_PAIR)
  94. #define XHCI_PORT_IS_ACTIVE(cid, pid) ((xhci_hc[cid].ports[pid].flags & XHCI_PROTOCOL_ACTIVE) == XHCI_PROTOCOL_ACTIVE)
  95. /**
  96. * @brief 设置link TRB的命令(dword3)
  97. *
  98. */
  99. #define xhci_TRB_set_link_cmd(trb_vaddr) \
  100. do \
  101. { \
  102. struct xhci_TRB_normal_t *ptr = (struct xhci_TRB_normal_t *)(trb_vaddr); \
  103. ptr->TRB_type = TRB_TYPE_LINK; \
  104. ptr->ioc = 0; \
  105. ptr->chain = 0; \
  106. ptr->ent = 0; \
  107. ptr->cycle = 1; \
  108. } while (0)
  109. // Common TRB types
  110. enum
  111. {
  112. TRB_TYPE_NORMAL = 1,
  113. TRB_TYPE_SETUP_STAGE,
  114. TRB_TYPE_DATA_STAGE,
  115. TRB_TYPE_STATUS_STAGE,
  116. TRB_TYPE_ISOCH,
  117. TRB_TYPE_LINK,
  118. TRB_TYPE_EVENT_DATA,
  119. TRB_TYPE_NO_OP,
  120. TRB_TYPE_ENABLE_SLOT,
  121. TRB_TYPE_DISABLE_SLOT = 10,
  122. TRB_TYPE_ADDRESS_DEVICE = 11,
  123. TRB_TYPE_CONFIG_EP,
  124. TRB_TYPE_EVALUATE_CONTEXT,
  125. TRB_TYPE_RESET_EP,
  126. TRB_TYPE_STOP_EP = 15,
  127. TRB_TYPE_SET_TR_DEQUEUE,
  128. TRB_TYPE_RESET_DEVICE,
  129. TRB_TYPE_FORCE_EVENT,
  130. TRB_TYPE_DEG_BANDWIDTH,
  131. TRB_TYPE_SET_LAT_TOLERANCE = 20,
  132. TRB_TYPE_GET_PORT_BAND = 21,
  133. TRB_TYPE_FORCE_HEADER,
  134. TRB_TYPE_NO_OP_CMD, // 24 - 31 = reserved
  135. TRB_TYPE_TRANS_EVENT = 32,
  136. TRB_TYPE_COMMAND_COMPLETION,
  137. TRB_TYPE_PORT_STATUS_CHANGE,
  138. TRB_TYPE_BANDWIDTH_REQUEST,
  139. TRB_TYPE_DOORBELL_EVENT,
  140. TRB_TYPE_HOST_CONTROLLER_EVENT = 37,
  141. TRB_TYPE_DEVICE_NOTIFICATION,
  142. TRB_TYPE_MFINDEX_WRAP,
  143. // 40 - 47 = reserved
  144. // 48 - 63 = Vendor Defined
  145. };
  146. /**
  147. * @brief 在controller数组之中寻找可用插槽
  148. *
  149. * 注意:该函数只能被获得init锁的进程所调用
  150. * @return int 可用id(无空位时返回-1)
  151. */
  152. static int xhci_hc_find_available_id()
  153. {
  154. if (unlikely(xhci_ctrl_count >= XHCI_MAX_HOST_CONTROLLERS))
  155. return -1;
  156. for (int i = 0; i < XHCI_MAX_HOST_CONTROLLERS; ++i)
  157. {
  158. if (xhci_hc[i].pci_dev_hdr == NULL)
  159. return i;
  160. }
  161. return -1;
  162. }
  163. /**
  164. * @brief 停止xhci主机控制器
  165. *
  166. * @param id 主机控制器id
  167. * @return int
  168. */
  169. static int xhci_hc_stop(int id)
  170. {
  171. // 判断是否已经停止
  172. if (unlikely((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 1))
  173. return 0;
  174. io_mfence();
  175. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, 0x00000000);
  176. io_mfence();
  177. char timeout = 17;
  178. while ((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 0)
  179. {
  180. io_mfence();
  181. usleep(1000);
  182. if (--timeout == 0)
  183. return -ETIMEDOUT;
  184. }
  185. return 0;
  186. }
  187. /**
  188. * @brief reset xHCI主机控制器
  189. *
  190. * @param id 主机控制器id
  191. * @return int
  192. */
  193. static int xhci_hc_reset(int id)
  194. {
  195. int retval = 0;
  196. kdebug("usbsts=%#010lx", xhci_read_op_reg32(id, XHCI_OPS_USBSTS));
  197. io_mfence();
  198. // 判断HCHalted是否置位
  199. if ((xhci_read_op_reg32(id, XHCI_OPS_USBSTS) & (1 << 0)) == 0)
  200. {
  201. io_mfence();
  202. kdebug("stopping usb hc...");
  203. // 未置位,需要先尝试停止usb主机控制器
  204. retval = xhci_hc_stop(id);
  205. if (unlikely(retval))
  206. return retval;
  207. }
  208. int timeout = 500; // wait 500ms
  209. // reset
  210. uint32_t cmd = xhci_read_op_reg32(id, XHCI_OPS_USBCMD);
  211. io_mfence();
  212. kdebug("cmd=%#010lx", cmd);
  213. cmd |= (1 << 1);
  214. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, cmd);
  215. io_mfence();
  216. kdebug("after rst, sts=%#010lx", xhci_read_op_reg32(id, XHCI_OPS_USBSTS));
  217. io_mfence();
  218. while (xhci_read_op_reg32(id, XHCI_OPS_USBCMD) & (1 << 1))
  219. {
  220. io_mfence();
  221. usleep(1000);
  222. if (--timeout == 0)
  223. return -ETIMEDOUT;
  224. }
  225. // kdebug("reset done!, timeout=%d", timeout);
  226. return retval;
  227. }
  228. /**
  229. * @brief 停止指定xhci控制器的legacy support
  230. *
  231. * @param id 控制器id
  232. * @return int
  233. */
  234. static int xhci_hc_stop_legacy(int id)
  235. {
  236. uint64_t current_offset = xhci_hc[id].ext_caps_off;
  237. do
  238. {
  239. // 判断当前entry是否为legacy support entry
  240. if ((xhci_read_cap_reg32(id, current_offset) & 0xff) == XHCI_XECP_ID_LEGACY)
  241. {
  242. io_mfence();
  243. // 接管控制权
  244. xhci_write_cap_reg32(id, current_offset, xhci_read_cap_reg32(id, current_offset) | XHCI_XECP_LEGACY_OS_OWNED);
  245. io_mfence();
  246. // 等待响应完成
  247. int timeout = XHCI_XECP_LEGACY_TIMEOUT;
  248. while ((xhci_read_cap_reg32(id, current_offset) & XHCI_XECP_LEGACY_OWNING_MASK) != XHCI_XECP_LEGACY_OS_OWNED)
  249. {
  250. io_mfence();
  251. usleep(1000);
  252. if (--timeout == 0)
  253. {
  254. kerror("The BIOS doesn't stop legacy support.");
  255. return -ETIMEDOUT;
  256. }
  257. }
  258. // 处理完成
  259. return 0;
  260. }
  261. io_mfence();
  262. // 读取下一个entry的偏移增加量
  263. int next_off = ((xhci_read_cap_reg32(id, current_offset) & 0xff00) >> 8) << 2;
  264. io_mfence();
  265. // 将指针跳转到下一个entry
  266. current_offset = next_off ? (current_offset + next_off) : 0;
  267. } while (current_offset);
  268. // 当前controller不存在legacy支持,也问题不大,不影响
  269. return 0;
  270. }
  271. /**
  272. * @brief 启用指定xhci控制器的调度
  273. *
  274. * @param id 控制器id
  275. * @return int
  276. */
  277. static int xhci_hc_start_sched(int id)
  278. {
  279. io_mfence();
  280. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, (1 << 0) | (1 << 2) | (1 << 3));
  281. io_mfence();
  282. usleep(100 * 1000);
  283. }
  284. /**
  285. * @brief 停止指定xhci控制器的调度
  286. *
  287. * @param id 控制器id
  288. * @return int
  289. */
  290. static int xhci_hc_stop_sched(int id)
  291. {
  292. io_mfence();
  293. xhci_write_op_reg32(id, XHCI_OPS_USBCMD, 0x00);
  294. io_mfence();
  295. }
  296. /**
  297. * @brief 在Ex capability list中寻找符合指定的协议号的寄存器offset、count、flag信息
  298. *
  299. * @param id 主机控制器id
  300. * @param list_off 列表项位置距离控制器虚拟基地址的偏移量
  301. * @param version 要寻找的端口版本号(2或3)
  302. * @param offset 返回的 Compatible Port Offset
  303. * @param count 返回的 Compatible Port Count
  304. * @param protocol_flag 返回的与协议相关的flag
  305. * @return uint32_t 下一个列表项的偏移量
  306. */
  307. static uint32_t xhci_hc_get_protocol_offset(int id, uint32_t list_off, const int version, uint32_t *offset, uint32_t *count, uint16_t *protocol_flag)
  308. {
  309. if (count)
  310. *count = 0;
  311. do
  312. {
  313. uint32_t dw0 = xhci_read_cap_reg32(id, list_off);
  314. io_mfence();
  315. uint32_t next_list_off = (dw0 >> 8) & 0xff;
  316. next_list_off = next_list_off ? (list_off + (next_list_off << 2)) : 0;
  317. if ((dw0 & 0xff) == XHCI_XECP_ID_PROTOCOL && ((dw0 & 0xff000000) >> 24) == version)
  318. {
  319. uint32_t dw2 = xhci_read_cap_reg32(id, list_off + 8);
  320. io_mfence();
  321. if (offset != NULL)
  322. *offset = (uint32_t)(dw2 & 0xff) - 1; // 使其转换为zero based
  323. if (count != NULL)
  324. *count = (uint32_t)((dw2 & 0xff00) >> 8);
  325. if (protocol_flag != NULL && version == 2)
  326. *protocol_flag = (uint16_t)((dw2 >> 16) & 0x0fff);
  327. return next_list_off;
  328. }
  329. list_off = next_list_off;
  330. } while (list_off);
  331. return 0;
  332. }
  333. /**
  334. * @brief 配对xhci主机控制器的usb2、usb3端口
  335. *
  336. * @param id 主机控制器id
  337. * @return int 返回码
  338. */
  339. static int xhci_hc_pair_ports(int id)
  340. {
  341. struct xhci_caps_HCSPARAMS1_reg_t hcs1;
  342. io_mfence();
  343. memcpy(&hcs1, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCSPARAMS1), sizeof(struct xhci_caps_HCSPARAMS1_reg_t));
  344. io_mfence();
  345. // 从hcs1获取端口数量
  346. xhci_hc[id].port_num = hcs1.max_ports;
  347. // 找到所有的端口并标记其端口信息
  348. xhci_hc[id].port_num_u2 = 0;
  349. xhci_hc[id].port_num_u3 = 0;
  350. uint32_t next_off = xhci_hc[id].ext_caps_off;
  351. uint32_t offset, cnt;
  352. uint16_t protocol_flags = 0;
  353. // 寻找所有的usb2端口
  354. while (next_off)
  355. {
  356. io_mfence();
  357. next_off = xhci_hc_get_protocol_offset(id, next_off, 2, &offset, &cnt, &protocol_flags);
  358. io_mfence();
  359. if (cnt)
  360. {
  361. for (int i = 0; i < cnt; ++i)
  362. {
  363. io_mfence();
  364. xhci_hc[id].ports[offset + i].offset = xhci_hc[id].port_num_u2++;
  365. xhci_hc[id].ports[offset + i].flags = XHCI_PROTOCOL_USB2;
  366. io_mfence();
  367. // usb2 high speed only
  368. if (protocol_flags & 2)
  369. xhci_hc[id].ports[offset + i].flags |= XHCI_PROTOCOL_HSO;
  370. }
  371. }
  372. }
  373. // 寻找所有的usb3端口
  374. next_off = xhci_hc[id].ext_caps_off;
  375. while (next_off)
  376. {
  377. io_mfence();
  378. next_off = xhci_hc_get_protocol_offset(id, next_off, 3, &offset, &cnt, &protocol_flags);
  379. io_mfence();
  380. if (cnt)
  381. {
  382. for (int i = 0; i < cnt; ++i)
  383. {
  384. io_mfence();
  385. xhci_hc[id].ports[offset + i].offset = xhci_hc[id].port_num_u3++;
  386. xhci_hc[id].ports[offset + i].flags = XHCI_PROTOCOL_USB3;
  387. }
  388. }
  389. }
  390. // 将对应的USB2端口和USB3端口进行配对
  391. for (int i = 0; i < xhci_hc[id].port_num; ++i)
  392. {
  393. for (int j = 0; j < xhci_hc[id].port_num; ++j)
  394. {
  395. if (unlikely(i == j))
  396. continue;
  397. io_mfence();
  398. if ((xhci_hc[id].ports[i].offset == xhci_hc[id].ports[j].offset) &&
  399. ((xhci_hc[id].ports[i].flags & XHCI_PROTOCOL_INFO) != (xhci_hc[id].ports[j].flags & XHCI_PROTOCOL_INFO)))
  400. {
  401. xhci_hc[id].ports[i].paired_port_num = j;
  402. xhci_hc[id].ports[i].flags |= XHCI_PROTOCOL_HAS_PAIR;
  403. io_mfence();
  404. xhci_hc[id].ports[j].paired_port_num = i;
  405. xhci_hc[id].ports[j].flags |= XHCI_PROTOCOL_HAS_PAIR;
  406. }
  407. }
  408. }
  409. // 标记所有的usb3、单独的usb2端口为激活状态
  410. for (int i = 0; i < xhci_hc[id].port_num; ++i)
  411. {
  412. io_mfence();
  413. if (XHCI_PORT_IS_USB3(id, i) ||
  414. (XHCI_PORT_IS_USB2(id, i) && (!XHCI_PORT_HAS_PAIR(id, i))))
  415. xhci_hc[id].ports[i].flags |= XHCI_PROTOCOL_ACTIVE;
  416. }
  417. kinfo("Found %d ports on root hub, usb2 ports:%d, usb3 ports:%d", xhci_hc[id].port_num, xhci_hc[id].port_num_u2, xhci_hc[id].port_num_u3);
  418. /*
  419. // 打印配对结果
  420. for (int i = 1; i <= xhci_hc[id].port_num; ++i)
  421. {
  422. if (XHCI_PORT_IS_USB3(id, i))
  423. {
  424. kdebug("USB3 port %d, offset=%d, pair with usb2 port %d, current port is %s", i, xhci_hc[id].ports[i].offset,
  425. xhci_hc[id].ports[i].paired_port_num, XHCI_PORT_IS_ACTIVE(id, i) ? "active" : "inactive");
  426. }
  427. else if (XHCI_PORT_IS_USB2(id, i) && (!XHCI_PORT_HAS_PAIR(id, i))) // 单独的2.0接口
  428. {
  429. kdebug("Stand alone USB2 port %d, offset=%d, current port is %s", i, xhci_hc[id].ports[i].offset,
  430. XHCI_PORT_IS_ACTIVE(id, i) ? "active" : "inactive");
  431. }
  432. else if (XHCI_PORT_IS_USB2(id, i))
  433. {
  434. kdebug("USB2 port %d, offset=%d, current port is %s, has pair=%s", i, xhci_hc[id].ports[i].offset,
  435. XHCI_PORT_IS_ACTIVE(id, i) ? "active" : "inactive", XHCI_PORT_HAS_PAIR(id, i) ? "true" : "false");
  436. }
  437. }
  438. */
  439. return 0;
  440. }
  441. /**
  442. * @brief 创建ring,并将最后一个trb指向头一个trb
  443. *
  444. * @param trbs 要创建的trb数量
  445. * @return uint64_t trb数组的起始虚拟地址
  446. */
  447. static uint64_t xhci_create_ring(int trbs)
  448. {
  449. int total_size = trbs * sizeof(struct xhci_TRB_t);
  450. const uint64_t vaddr = (uint64_t)kmalloc(total_size, 0);
  451. io_mfence();
  452. memset((void *)vaddr, 0, total_size);
  453. io_mfence();
  454. // 设置最后一个trb为link trb
  455. xhci_TRB_set_link_cmd(vaddr + total_size - sizeof(struct xhci_TRB_t));
  456. io_mfence();
  457. return vaddr;
  458. }
  459. /**
  460. * @brief 创建新的event ring table和对应的ring segment
  461. *
  462. * @param trbs 包含的trb的数量
  463. * @param ret_ring_addr 返回的第一个event ring segment的基地址(虚拟)
  464. * @return uint64_t trb table的虚拟地址
  465. */
  466. static uint64_t xhci_create_event_ring(int trbs, uint64_t *ret_ring_addr)
  467. {
  468. const uint64_t table_vaddr = (const uint64_t)kmalloc(64, 0); // table支持8个segment
  469. io_mfence();
  470. if (unlikely(table_vaddr == NULL))
  471. return -ENOMEM;
  472. memset((void *)table_vaddr, 0, 64);
  473. // 暂时只创建1个segment
  474. const uint64_t seg_vaddr = (const uint64_t)kmalloc(trbs * sizeof(struct xhci_TRB_t), 0);
  475. io_mfence();
  476. if (unlikely(seg_vaddr == NULL))
  477. return -ENOMEM;
  478. memset((void *)seg_vaddr, 0, trbs * sizeof(struct xhci_TRB_t));
  479. io_mfence();
  480. // 将segment地址和大小写入table
  481. *(uint64_t *)(table_vaddr) = virt_2_phys(seg_vaddr);
  482. *(uint64_t *)(table_vaddr + 8) = trbs;
  483. *ret_ring_addr = seg_vaddr;
  484. return table_vaddr;
  485. }
  486. void xhci_hc_irq_enable(uint64_t irq_num)
  487. {
  488. int cid = xhci_find_hcid_by_irq_num(irq_num);
  489. io_mfence();
  490. if (WARN_ON(cid == -1))
  491. return;
  492. kdebug("start msi");
  493. io_mfence();
  494. pci_start_msi(xhci_hc[cid].pci_dev_hdr);
  495. kdebug("start sched");
  496. io_mfence();
  497. xhci_hc_start_sched(cid);
  498. kdebug("start ports");
  499. io_mfence();
  500. xhci_hc_start_ports(cid);
  501. kdebug("enabled");
  502. }
  503. void xhci_hc_irq_disable(uint64_t irq_num)
  504. {
  505. int cid = xhci_find_hcid_by_irq_num(irq_num);
  506. io_mfence();
  507. if (WARN_ON(cid == -1))
  508. return;
  509. xhci_hc_stop_sched(cid);
  510. io_mfence();
  511. pci_disable_msi(xhci_hc[cid].pci_dev_hdr);
  512. io_mfence();
  513. }
  514. uint64_t xhci_hc_irq_install(uint64_t irq_num, void *arg)
  515. {
  516. int cid = xhci_find_hcid_by_irq_num(irq_num);
  517. io_mfence();
  518. if (WARN_ON(cid == -1))
  519. return -EINVAL;
  520. struct xhci_hc_irq_install_info_t *info = (struct xhci_hc_irq_install_info_t *)arg;
  521. struct msi_desc_t msi_desc;
  522. memset(&msi_desc, 0, sizeof(struct msi_desc_t));
  523. io_mfence();
  524. msi_desc.irq_num = irq_num;
  525. msi_desc.msi_index = 0;
  526. msi_desc.pci_dev = (struct pci_device_structure_header_t *)xhci_hc[cid].pci_dev_hdr;
  527. msi_desc.assert = info->assert;
  528. msi_desc.edge_trigger = info->edge_trigger;
  529. msi_desc.processor = info->processor;
  530. msi_desc.pci.msi_attribute.is_64 = 1;
  531. msi_desc.pci.msi_attribute.is_msix = 1;
  532. // todo: QEMU是使用msix的,因此要先在pci中实现msix
  533. io_mfence();
  534. int retval = pci_enable_msi(&msi_desc);
  535. kdebug("pci retval = %d", retval);
  536. kdebug("xhci irq %d installed.", irq_num);
  537. return 0;
  538. }
  539. void xhci_hc_irq_uninstall(uint64_t irq_num)
  540. {
  541. // todo
  542. int cid = xhci_find_hcid_by_irq_num(irq_num);
  543. io_mfence();
  544. if (WARN_ON(cid == -1))
  545. return;
  546. xhci_hc_stop(cid);
  547. io_mfence();
  548. }
  549. /**
  550. * @brief xhci主机控制器的中断处理函数
  551. *
  552. * @param irq_num 中断向量号
  553. * @param cid 控制器号
  554. * @param regs 寄存器值
  555. */
  556. void xhci_hc_irq_handler(uint64_t irq_num, uint64_t cid, struct pt_regs *regs)
  557. {
  558. // todo: handle irq
  559. kdebug("USB irq received.");
  560. }
  561. /**
  562. * @brief 重置端口
  563. *
  564. * @param id 控制器id
  565. * @param port 端口id
  566. * @return int
  567. */
  568. static int xhci_reset_port(const int id, const int port)
  569. {
  570. int retval = 0;
  571. // 相对于op寄存器基地址的偏移量
  572. uint64_t port_status_offset = XHCI_OPS_PRS + port * 16;
  573. // kdebug("to reset %d, offset=%#018lx", port, port_status_offset);
  574. io_mfence();
  575. // 检查端口电源状态
  576. if ((xhci_read_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC) & (1 << 9)) == 0)
  577. {
  578. kdebug("port is power off, starting...");
  579. io_mfence();
  580. xhci_write_cap_reg32(id, port_status_offset + XHCI_PORT_PORTSC, (1 << 9));
  581. io_mfence();
  582. usleep(2000);
  583. // 检测端口是否被启用, 若未启用,则报错
  584. if ((xhci_read_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC) & (1 << 9)) == 0)
  585. {
  586. kdebug("cannot power on %d", port);
  587. return -EAGAIN;
  588. }
  589. }
  590. // kdebug("port:%d, power check ok", port);
  591. io_mfence();
  592. // 确保端口的status被清0
  593. xhci_write_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC, (1 << 9) | XHCI_PORTUSB_CHANGE_BITS);
  594. io_mfence();
  595. // 重置当前端口
  596. if (XHCI_PORT_IS_USB3(id, port))
  597. xhci_write_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC, (1 << 9) | (1 << 31));
  598. else
  599. xhci_write_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC, (1 << 9) | (1 << 4));
  600. retval = -ETIMEDOUT;
  601. // 等待portsc的port reset change位被置位,说明reset完成
  602. int timeout = 200;
  603. while (timeout)
  604. {
  605. io_mfence();
  606. uint32_t val = xhci_read_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC);
  607. io_mfence();
  608. if (XHCI_PORT_IS_USB3(id, port) && (val & (1 << 31)) == 0)
  609. break;
  610. else if (XHCI_PORT_IS_USB2(id, port) && (val & (1 << 4)) == 0)
  611. break;
  612. else if (val & (1 << 21))
  613. break;
  614. --timeout;
  615. usleep(500);
  616. }
  617. // kdebug("timeout= %d", timeout);
  618. if (timeout > 0)
  619. {
  620. // 等待恢复
  621. usleep(USB_TIME_RST_REC * 1000);
  622. uint32_t val = xhci_read_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC);
  623. io_mfence();
  624. // 如果reset之后,enable bit仍然是1,那么说明reset成功
  625. if (val & (1 << 1))
  626. {
  627. io_mfence();
  628. // 清除status change bit
  629. xhci_write_op_reg32(id, port_status_offset + XHCI_PORT_PORTSC, (1 << 9) | XHCI_PORTUSB_CHANGE_BITS);
  630. io_mfence();
  631. }
  632. retval = 0;
  633. }
  634. // 如果usb2端口成功reset,则处理该端口的active状态
  635. if (retval == 0 && XHCI_PORT_IS_USB2(id, port))
  636. {
  637. xhci_hc[id].ports[port].flags |= XHCI_PROTOCOL_ACTIVE;
  638. if (XHCI_PORT_HAS_PAIR(id, port)) // 如果有对应的usb3端口,则将usb3端口设置为未激活
  639. xhci_hc[id].ports[xhci_hc[id].ports[port].paired_port_num].flags &= ~(XHCI_PROTOCOL_ACTIVE);
  640. }
  641. // 如果usb3端口reset失败,则启用与之配对的usb2端口
  642. if (retval != 0 && XHCI_PORT_IS_USB3(id, port))
  643. {
  644. xhci_hc[id].ports[port].flags &= ~XHCI_PROTOCOL_ACTIVE;
  645. xhci_hc[id].ports[xhci_hc[id].ports[port].paired_port_num].flags |= XHCI_PROTOCOL_ACTIVE;
  646. }
  647. return retval;
  648. }
  649. /**
  650. * @brief 启用xhci控制器的端口
  651. *
  652. * @param id 控制器id
  653. * @return int
  654. */
  655. static int xhci_hc_start_ports(int id)
  656. {
  657. int cnt = 0;
  658. // 注意,这两个循环应该不能合并到一起,因为可能存在usb2端口offset在前,usb3端口在后的情况,那样的话就会出错
  659. // 循环启动所有的usb3端口
  660. for (int i = 0; i < xhci_hc[id].port_num; ++i)
  661. {
  662. if (XHCI_PORT_IS_USB3(id, i) && XHCI_PORT_IS_ACTIVE(id, i))
  663. {
  664. io_mfence();
  665. // reset该端口
  666. if (likely(xhci_reset_port(id, i) == 0)) // 如果端口reset成功,就获取它的描述符
  667. // 否则,reset函数会把它给设置为未激活,并且标志配对的usb2端口是激活的
  668. {
  669. // xhci_hc_get_descriptor(id, i);
  670. ++cnt;
  671. }
  672. }
  673. }
  674. kdebug("active usb3 ports:%d", cnt);
  675. // 循环启动所有的usb2端口
  676. for (int i = 0; i < xhci_hc[id].port_num; ++i)
  677. {
  678. if (XHCI_PORT_IS_USB2(id, i) && XHCI_PORT_IS_ACTIVE(id, i))
  679. {
  680. // reset该端口
  681. if (likely(xhci_reset_port(id, i) == 0)) // 如果端口reset成功,就获取它的描述符
  682. // 否则,reset函数会把它给设置为未激活,并且标志配对的usb2端口是激活的
  683. {
  684. // xhci_hc_get_descriptor(id, i);
  685. ++cnt;
  686. }
  687. }
  688. }
  689. kinfo("xHCI controller %d: Started %d ports.", id, cnt);
  690. return 0;
  691. }
  692. /**
  693. * @brief 初始化xhci主机控制器的中断控制
  694. *
  695. * @param id 主机控制器id
  696. * @return int 返回码
  697. */
  698. static int xhci_hc_init_intr(int id)
  699. {
  700. uint64_t retval = 0;
  701. struct xhci_caps_HCSPARAMS1_reg_t hcs1;
  702. struct xhci_caps_HCSPARAMS2_reg_t hcs2;
  703. io_mfence();
  704. memcpy(&hcs1, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCSPARAMS1), sizeof(struct xhci_caps_HCSPARAMS1_reg_t));
  705. io_mfence();
  706. memcpy(&hcs2, xhci_get_ptr_cap_reg32(id, XHCI_CAPS_HCSPARAMS2), sizeof(struct xhci_caps_HCSPARAMS2_reg_t));
  707. io_mfence();
  708. uint32_t max_segs = (1 << (uint32_t)(hcs2.ERST_Max));
  709. uint32_t max_interrupters = hcs1.max_intrs;
  710. // 创建 event ring
  711. retval = xhci_create_event_ring(4096, &xhci_hc[id].event_ring_vaddr);
  712. io_mfence();
  713. if (unlikely((int64_t)(retval) == -ENOMEM))
  714. return -ENOMEM;
  715. xhci_hc[id].event_ring_table_vaddr = retval;
  716. retval = 0;
  717. xhci_hc[id].current_event_ring_cycle = 1;
  718. // 写入第0个中断寄存器组
  719. io_mfence();
  720. xhci_write_intr_reg32(id, 0, XHCI_IR_MAN, 0x3); // 使能中断并清除pending位(这个pending位是写入1就清0的)
  721. io_mfence();
  722. xhci_write_intr_reg32(id, 0, XHCI_IR_MOD, 0); // 关闭中断管制
  723. io_mfence();
  724. xhci_write_intr_reg32(id, 0, XHCI_IR_TABLE_SIZE, 1); // 当前只有1个segment
  725. io_mfence();
  726. xhci_write_intr_reg64(id, 0, XHCI_IR_DEQUEUE, virt_2_phys(xhci_hc[id].event_ring_vaddr) | (1 << 3)); // 写入dequeue寄存器,并清除busy位(写1就会清除)
  727. io_mfence();
  728. xhci_write_intr_reg64(id, 0, XHCI_IR_TABLE_ADDR, virt_2_phys(xhci_hc[id].event_ring_table_vaddr)); // 写入table地址
  729. io_mfence();
  730. // 清除状态位
  731. xhci_write_op_reg32(id, XHCI_OPS_USBSTS, (1 << 10) | (1 << 4) | (1 << 3) | (1 << 2));
  732. io_mfence();
  733. // 开启usb中断
  734. // 注册中断处理程序
  735. struct xhci_hc_irq_install_info_t install_info;
  736. install_info.assert = 1;
  737. install_info.edge_trigger = 1;
  738. install_info.processor = 0; // 投递到bsp
  739. char *buf = (char *)kmalloc(16, 0);
  740. memset(buf, 0, 16);
  741. sprintk(buf, "xHCI HC%d", id);
  742. io_mfence();
  743. irq_register(xhci_controller_irq_num[id], &install_info, &xhci_hc_irq_handler, id, &xhci_hc_intr_controller, buf);
  744. io_mfence();
  745. kfree(buf);
  746. kdebug("xhci host controller %d: interrupt registered. irq num=%d", id, xhci_controller_irq_num[id]);
  747. return 0;
  748. }
  749. /**
  750. * @brief 写入doorbell寄存器
  751. *
  752. * @param id 主机控制器id
  753. * @param slot_id usb控制器插槽id(0用作命令门铃,其他的用于具体的设备的门铃)
  754. * @param value 要写入的值
  755. */
  756. static __always_inline void __xhci_write_doorbell(const int id, const uint16_t slot_id, const uint32_t value)
  757. {
  758. // 确保写入门铃寄存器之前,所有的写操作均已完成
  759. io_sfence();
  760. xhci_write_cap_reg32(id, xhci_hc[id].db_offset + slot_id * sizeof(uint32_t), value);
  761. io_sfence();
  762. }
  763. /**
  764. * @brief 往xhci控制器发送命令
  765. *
  766. * @param id xhci控制器号
  767. * @param trb 传输请求块
  768. * @param do_ring 是否通知doorbell register
  769. * @return int 错误码
  770. */
  771. static int xhci_send_command(int id, struct xhci_TRB_t *trb, const bool do_ring)
  772. {
  773. uint64_t origin_trb_vaddr = xhci_hc[id].cmd_trb_vaddr;
  774. // 必须先写入参数和状态数据,最后写入command
  775. xhci_write_mem64(xhci_hc[id].cmd_trb_vaddr, trb->param); // 参数
  776. xhci_write_mem32(xhci_hc[id].cmd_trb_vaddr + 8, trb->status); // 状态
  777. xhci_write_mem32(xhci_hc[id].cmd_trb_vaddr + 12, trb->command); // 命令
  778. xhci_hc[id].cmd_trb_vaddr += sizeof(struct xhci_TRB_t); // 跳转到下一个trb
  779. {
  780. // 如果下一个trb是link trb,则将下一个要操作的地址是设置为第一个trb
  781. struct xhci_TRB_normal_t *ptr = (struct xhci_TRB_normal_t *)xhci_hc[id].cmd_trb_vaddr;
  782. if (ptr->TRB_type == TRB_TYPE_LINK)
  783. {
  784. ptr->cycle = xhci_hc[id].cmd_trb_cycle;
  785. xhci_hc[id].cmd_trb_vaddr = xhci_hc[id].cmd_ring_vaddr;
  786. xhci_hc[id].cmd_trb_cycle ^= 1;
  787. }
  788. }
  789. if (do_ring) // 按响命令门铃
  790. {
  791. kdebug("to ring..");
  792. __xhci_write_doorbell(id, 0, 0);
  793. kdebug("ring..");
  794. // 等待中断产生
  795. int timer = 20;
  796. // Now wait for the interrupt to happen
  797. // We use bit 31 of the command dword since it is reserved
  798. while (timer && ((xhci_read_mem32(origin_trb_vaddr + 12) & (1 << 31)) == 0))
  799. {
  800. usleep(1000);
  801. --timer;
  802. }
  803. uint32_t x = xhci_read_cap_reg32(id, xhci_hc[id].rts_offset + 0x20);
  804. kdebug("ip=%#010lx", x);
  805. if (timer == 0)
  806. kwarn("USB xHCI Command Interrupt wait timed out.");
  807. else
  808. {
  809. kdebug("interrupt done");
  810. }
  811. }
  812. return 0;
  813. }
  814. /**
  815. * @brief 初始化xhci控制器
  816. *
  817. * @param header 指定控制器的pci device头部
  818. */
  819. void xhci_init(struct pci_device_structure_general_device_t *dev_hdr)
  820. {
  821. if (xhci_ctrl_count >= XHCI_MAX_HOST_CONTROLLERS)
  822. {
  823. kerror("Initialize xhci controller failed: exceed the limit of max controllers.");
  824. return;
  825. }
  826. spin_lock(&xhci_controller_init_lock);
  827. kinfo("Initializing xhci host controller: bus=%#02x, device=%#02x, func=%#02x, VendorID=%#04x, irq_line=%d, irq_pin=%d", dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, dev_hdr->header.Vendor_ID, dev_hdr->Interrupt_Line, dev_hdr->Interrupt_PIN);
  828. io_mfence();
  829. int cid = xhci_hc_find_available_id();
  830. if (cid < 0)
  831. {
  832. kerror("Initialize xhci controller failed: exceed the limit of max controllers.");
  833. goto failed_exceed_max;
  834. }
  835. memset(&xhci_hc[cid], 0, sizeof(struct xhci_host_controller_t));
  836. xhci_hc[cid].controller_id = cid;
  837. xhci_hc[cid].pci_dev_hdr = dev_hdr;
  838. io_mfence();
  839. {
  840. uint32_t tmp = pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0x4);
  841. tmp |= 0x6;
  842. // mem I/O access enable and bus master enable
  843. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0x4, tmp);
  844. }
  845. io_mfence();
  846. // 为当前控制器映射寄存器地址空间
  847. xhci_hc[cid].vbase = SPECIAL_MEMOEY_MAPPING_VIRT_ADDR_BASE + XHCI_MAPPING_OFFSET + 65536 * xhci_hc[cid].controller_id;
  848. // kdebug("dev_hdr->BAR0 & (~0xf)=%#018lx", dev_hdr->BAR0 & (~0xf));
  849. mm_map_phys_addr(xhci_hc[cid].vbase, dev_hdr->BAR0 & (~0xf), 65536, PAGE_KERNEL_PAGE | PAGE_PWT | PAGE_PCD, true);
  850. io_mfence();
  851. // 读取xhci控制寄存器
  852. uint16_t iversion = *(uint16_t *)(xhci_hc[cid].vbase + XHCI_CAPS_HCIVERSION);
  853. struct xhci_caps_HCCPARAMS1_reg_t hcc1;
  854. struct xhci_caps_HCCPARAMS2_reg_t hcc2;
  855. struct xhci_caps_HCSPARAMS1_reg_t hcs1;
  856. struct xhci_caps_HCSPARAMS2_reg_t hcs2;
  857. memcpy(&hcc1, xhci_get_ptr_cap_reg32(cid, XHCI_CAPS_HCCPARAMS1), sizeof(struct xhci_caps_HCCPARAMS1_reg_t));
  858. memcpy(&hcc2, xhci_get_ptr_cap_reg32(cid, XHCI_CAPS_HCCPARAMS2), sizeof(struct xhci_caps_HCCPARAMS2_reg_t));
  859. memcpy(&hcs1, xhci_get_ptr_cap_reg32(cid, XHCI_CAPS_HCSPARAMS1), sizeof(struct xhci_caps_HCSPARAMS1_reg_t));
  860. memcpy(&hcs2, xhci_get_ptr_cap_reg32(cid, XHCI_CAPS_HCSPARAMS2), sizeof(struct xhci_caps_HCSPARAMS2_reg_t));
  861. // kdebug("hcc1.xECP=%#010lx", hcc1.xECP);
  862. // 计算operational registers的地址
  863. xhci_hc[cid].vbase_op = xhci_hc[cid].vbase + (xhci_read_cap_reg32(cid, XHCI_CAPS_CAPLENGTH) & 0xff);
  864. io_mfence();
  865. xhci_hc[cid].db_offset = xhci_read_cap_reg32(cid, XHCI_CAPS_DBOFF) & (~0x3); // bits [1:0] reserved
  866. io_mfence();
  867. xhci_hc[cid].rts_offset = xhci_read_cap_reg32(cid, XHCI_CAPS_RTSOFF) & (~0x1f); // bits [4:0] reserved.
  868. io_mfence();
  869. xhci_hc[cid].ext_caps_off = 1UL * (hcc1.xECP) * 4;
  870. xhci_hc[cid].context_size = (hcc1.csz) ? 64 : 32;
  871. if (iversion < 0x95)
  872. kwarn("Unsupported/Unknowned xHCI controller version: %#06x. This may cause unexpected behavior.", iversion);
  873. {
  874. // Write to the FLADJ register incase the BIOS didn't
  875. uint32_t tmp = pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0x60);
  876. tmp |= (0x20 << 8);
  877. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0x60, tmp);
  878. }
  879. // if it is a Panther Point device, make sure sockets are xHCI controlled.
  880. if (((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0) & 0xffff) == 0x8086) &&
  881. (((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0) >> 16) & 0xffff) == 0x1E31) &&
  882. ((pci_read_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 8) & 0xff) == 4))
  883. {
  884. kdebug("Is a Panther Point device");
  885. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0xd8, 0xffffffff);
  886. pci_write_config(dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func, 0xd0, 0xffffffff);
  887. }
  888. io_mfence();
  889. // 关闭legacy支持
  890. FAIL_ON_TO(xhci_hc_stop_legacy(cid), failed);
  891. io_mfence();
  892. // 重置xhci控制器
  893. FAIL_ON_TO(xhci_hc_reset(cid), failed);
  894. io_mfence();
  895. // 端口配对
  896. FAIL_ON_TO(xhci_hc_pair_ports(cid), failed);
  897. io_mfence();
  898. // ========== 设置USB host controller =========
  899. // 获取页面大小
  900. kdebug("ops pgsize=%#010lx", xhci_read_op_reg32(cid, XHCI_OPS_PAGESIZE));
  901. xhci_hc[cid].page_size = (xhci_read_op_reg32(cid, XHCI_OPS_PAGESIZE) & 0xffff) << 12;
  902. kdebug("page size=%d", xhci_hc[cid].page_size);
  903. io_mfence();
  904. // 获取设备上下文空间
  905. xhci_hc[cid].dcbaap_vaddr = (uint64_t)kmalloc(2048, 0); // 分配2KB的设备上下文地址数组空间
  906. memset((void *)xhci_hc[cid].dcbaap_vaddr, 0, 2048);
  907. io_mfence();
  908. kdebug("dcbaap_vaddr=%#018lx", xhci_hc[cid].dcbaap_vaddr);
  909. if (unlikely(!xhci_is_aligned64(xhci_hc[cid].dcbaap_vaddr))) // 地址不是按照64byte对齐
  910. {
  911. kerror("dcbaap isn't 64 byte aligned.");
  912. goto failed_free_dyn;
  913. }
  914. // 写入dcbaap
  915. xhci_write_op_reg64(cid, XHCI_OPS_DCBAAP, virt_2_phys(xhci_hc[cid].dcbaap_vaddr));
  916. io_mfence();
  917. // 创建command ring
  918. xhci_hc[cid].cmd_ring_vaddr = xhci_create_ring(XHCI_CMND_RING_TRBS);
  919. xhci_hc[cid].cmd_trb_vaddr = xhci_hc[cid].cmd_ring_vaddr;
  920. if (unlikely(!xhci_is_aligned64(xhci_hc[cid].cmd_ring_vaddr))) // 地址不是按照64byte对齐
  921. {
  922. kerror("cmd ring isn't 64 byte aligned.");
  923. goto failed_free_dyn;
  924. }
  925. // 设置初始cycle bit为1
  926. xhci_hc[cid].cmd_trb_cycle = XHCI_TRB_CYCLE_ON;
  927. io_mfence();
  928. // 写入command ring控制寄存器
  929. xhci_write_op_reg64(cid, XHCI_OPS_CRCR, virt_2_phys(xhci_hc[cid].cmd_ring_vaddr) | xhci_hc[cid].cmd_trb_cycle);
  930. // 写入配置寄存器
  931. uint32_t max_slots = hcs1.max_slots;
  932. kdebug("max slots = %d", max_slots);
  933. io_mfence();
  934. xhci_write_op_reg32(cid, XHCI_OPS_CONFIG, max_slots);
  935. io_mfence();
  936. // 写入设备通知控制寄存器
  937. xhci_write_op_reg32(cid, XHCI_OPS_DNCTRL, (1 << 1)); // 目前只有N1被支持
  938. io_mfence();
  939. FAIL_ON_TO(xhci_hc_init_intr(cid), failed_free_dyn);
  940. io_mfence();
  941. ++xhci_ctrl_count;
  942. io_mfence();
  943. spin_unlock(&xhci_controller_init_lock);
  944. io_mfence();
  945. // 发送nop
  946. struct xhci_TRB_normal_t nop_trb = {0};
  947. nop_trb.cycle = xhci_hc[cid].cmd_trb_cycle;
  948. nop_trb.TRB_type = TRB_TYPE_NO_OP;
  949. // nop_trb.ioc = 1;
  950. kdebug("to send nop TRB");
  951. xhci_send_command(cid, &nop_trb, true);
  952. xhci_send_command(cid, &nop_trb, true);
  953. kdebug("nop TRB send OK");
  954. return;
  955. failed_free_dyn:; // 释放动态申请的内存
  956. if (xhci_hc[cid].dcbaap_vaddr)
  957. kfree((void *)xhci_hc[cid].dcbaap_vaddr);
  958. if (xhci_hc[cid].cmd_ring_vaddr)
  959. kfree((void *)xhci_hc[cid].cmd_ring_vaddr);
  960. if (xhci_hc[cid].event_ring_table_vaddr)
  961. kfree((void *)xhci_hc[cid].event_ring_table_vaddr);
  962. if (xhci_hc[cid].event_ring_vaddr)
  963. kfree((void *)xhci_hc[cid].event_ring_vaddr);
  964. failed:;
  965. io_mfence();
  966. // 取消地址映射
  967. mm_unmap_addr(xhci_hc[cid].vbase, 65536);
  968. io_mfence();
  969. // 清空数组
  970. memset((void *)&xhci_hc[cid], 0, sizeof(struct xhci_host_controller_t));
  971. failed_exceed_max:;
  972. kerror("Failed to initialize controller: bus=%d, dev=%d, func=%d", dev_hdr->header.bus, dev_hdr->header.device, dev_hdr->header.func);
  973. spin_unlock(&xhci_controller_init_lock);
  974. }