|
@@ -11,14 +11,13 @@ pub enum Resource {
|
|
|
AddressSpace(AddressSpaceDescriptor),
|
|
|
MemoryRange(MemoryRangeDescriptor),
|
|
|
IOPort(IOPortDescriptor),
|
|
|
- Dma(DMADescriptor)
|
|
|
+ Dma(DMADescriptor),
|
|
|
}
|
|
|
|
|
|
-
|
|
|
/// Parse a `ResourceDescriptor` into a list of resources. Returns `AmlError::IncompatibleValueConversion` if the passed value is not a
|
|
|
/// `Buffer`.
|
|
|
pub fn resource_descriptor_list(descriptor: &AmlValue) -> Result<Vec<Resource>, AmlError> {
|
|
|
- if let AmlValue::Buffer { bytes, size: _ } = descriptor {
|
|
|
+ if let AmlValue::Buffer(bytes) = descriptor {
|
|
|
let mut descriptors = Vec::new();
|
|
|
let mut bytes = bytes.as_slice();
|
|
|
|
|
@@ -43,38 +42,38 @@ pub fn resource_descriptor_list(descriptor: &AmlValue) -> Result<Vec<Resource>,
|
|
|
/// `Buffer`.
|
|
|
fn resource_descriptor(bytes: &[u8]) -> Result<(Option<Resource>, &[u8]), AmlError> {
|
|
|
/*
|
|
|
- * If bit 7 of Byte 0 is set, it's a large descriptor. If not, it's a small descriptor.
|
|
|
- */
|
|
|
+ * If bit 7 of Byte 0 is set, it's a large descriptor. If not, it's a small descriptor.
|
|
|
+ */
|
|
|
if bytes[0].get_bit(7) {
|
|
|
/*
|
|
|
- * We're parsing a large item. The descriptor type is encoded in Bits 0-6 of Byte 0. Valid types:
|
|
|
- * 0x00: Reserved
|
|
|
- * 0x01: 24-bit Memory Range Descriptor
|
|
|
- * 0x02: Generic Register Descriptor
|
|
|
- * 0x03: Reserved
|
|
|
- * 0x04: Vendor-defined Descriptor
|
|
|
- * 0x05: 32-bit Memory Range Descriptor
|
|
|
- * 0x06: 32-bit Fixed Memory Range Descriptor
|
|
|
- * 0x07: Address Space Resource Descriptor
|
|
|
- * 0x08: Word Address Space Descriptor
|
|
|
- * 0x09: Extended Interrupt Descriptor
|
|
|
- * 0x0a: QWord Address Space Descriptor
|
|
|
- * 0x0b: Extended Address Space Descriptor
|
|
|
- * 0x0c: GPIO Connection Descriptor
|
|
|
- * 0x0d: Pin Function Descriptor
|
|
|
- * 0x0e: GenericSerialBus Connection Descriptor
|
|
|
- * 0x0f: Pin Configuration Descriptor
|
|
|
- * 0x10: Pin Group Descriptor
|
|
|
- * 0x11: Pin Group Function Descriptor
|
|
|
- * 0x12: Pin Group Configuration Descriptor
|
|
|
- * 0x13-0x7f: Reserved
|
|
|
- *
|
|
|
- * Byte 1 contains bits 0-7 of the length, and Byte 2 contains bits 8-15 of the length. Subsequent
|
|
|
- * bytes contain the actual data items.
|
|
|
- */
|
|
|
+ * We're parsing a large item. The descriptor type is encoded in Bits 0-6 of Byte 0. Valid types:
|
|
|
+ * 0x00: Reserved
|
|
|
+ * 0x01: 24-bit Memory Range Descriptor
|
|
|
+ * 0x02: Generic Register Descriptor
|
|
|
+ * 0x03: Reserved
|
|
|
+ * 0x04: Vendor-defined Descriptor
|
|
|
+ * 0x05: 32-bit Memory Range Descriptor
|
|
|
+ * 0x06: 32-bit Fixed Memory Range Descriptor
|
|
|
+ * 0x07: Address Space Resource Descriptor
|
|
|
+ * 0x08: Word Address Space Descriptor
|
|
|
+ * 0x09: Extended Interrupt Descriptor
|
|
|
+ * 0x0a: QWord Address Space Descriptor
|
|
|
+ * 0x0b: Extended Address Space Descriptor
|
|
|
+ * 0x0c: GPIO Connection Descriptor
|
|
|
+ * 0x0d: Pin Function Descriptor
|
|
|
+ * 0x0e: GenericSerialBus Connection Descriptor
|
|
|
+ * 0x0f: Pin Configuration Descriptor
|
|
|
+ * 0x10: Pin Group Descriptor
|
|
|
+ * 0x11: Pin Group Function Descriptor
|
|
|
+ * 0x12: Pin Group Configuration Descriptor
|
|
|
+ * 0x13-0x7f: Reserved
|
|
|
+ *
|
|
|
+ * Byte 1 contains bits 0-7 of the length, and Byte 2 contains bits 8-15 of the length. Subsequent
|
|
|
+ * bytes contain the actual data items.
|
|
|
+ */
|
|
|
let descriptor_type = bytes[0].get_bits(0..7);
|
|
|
let length = LittleEndian::read_u16(&bytes[1..=2]) as usize;
|
|
|
- let (descriptor_bytes, remaining_bytes)= bytes.split_at(length+3);
|
|
|
+ let (descriptor_bytes, remaining_bytes) = bytes.split_at(length + 3);
|
|
|
|
|
|
let descriptor = match descriptor_type {
|
|
|
0x01 => unimplemented!("24-bit Memory Range Descriptor"),
|
|
@@ -99,33 +98,33 @@ fn resource_descriptor(bytes: &[u8]) -> Result<(Option<Resource>, &[u8]), AmlErr
|
|
|
0x00 | 0x13..=0x7f => Err(AmlError::ReservedResourceType),
|
|
|
0x80..=0xff => unreachable!(),
|
|
|
}?;
|
|
|
-
|
|
|
+
|
|
|
Ok((Some(descriptor), remaining_bytes))
|
|
|
} else {
|
|
|
/*
|
|
|
- * We're parsing a small descriptor. Byte 0 has the format:
|
|
|
- * | Bits | Field |
|
|
|
- * |-------------|-------------------|
|
|
|
- * | 0-2 | Length - n bytes |
|
|
|
- * | 3-6 | Small item type |
|
|
|
- * | 7 | 0 = small item |
|
|
|
- *
|
|
|
- * The valid types are:
|
|
|
- * 0x00-0x03: Reserved
|
|
|
- * 0x04: IRQ Format Descriptor
|
|
|
- * 0x05: DMA Format Descriptor
|
|
|
- * 0x06: Start Dependent Functions Descriptor
|
|
|
- * 0x07: End Dependent Functions Descriptor
|
|
|
- * 0x08: IO Port Descriptor
|
|
|
- * 0x09: Fixed Location IO Port Descriptor
|
|
|
- * 0x0A: Fixed DMA Descriptor
|
|
|
- * 0x0B-0x0D: Reserved
|
|
|
- * 0x0E: Vendor Defined Descriptor
|
|
|
- * 0x0F: End Tag Descriptor
|
|
|
- */
|
|
|
+ * We're parsing a small descriptor. Byte 0 has the format:
|
|
|
+ * | Bits | Field |
|
|
|
+ * |-------------|-------------------|
|
|
|
+ * | 0-2 | Length - n bytes |
|
|
|
+ * | 3-6 | Small item type |
|
|
|
+ * | 7 | 0 = small item |
|
|
|
+ *
|
|
|
+ * The valid types are:
|
|
|
+ * 0x00-0x03: Reserved
|
|
|
+ * 0x04: IRQ Format Descriptor
|
|
|
+ * 0x05: DMA Format Descriptor
|
|
|
+ * 0x06: Start Dependent Functions Descriptor
|
|
|
+ * 0x07: End Dependent Functions Descriptor
|
|
|
+ * 0x08: IO Port Descriptor
|
|
|
+ * 0x09: Fixed Location IO Port Descriptor
|
|
|
+ * 0x0A: Fixed DMA Descriptor
|
|
|
+ * 0x0B-0x0D: Reserved
|
|
|
+ * 0x0E: Vendor Defined Descriptor
|
|
|
+ * 0x0F: End Tag Descriptor
|
|
|
+ */
|
|
|
let descriptor_type = bytes[0].get_bits(3..=6);
|
|
|
let length: usize = bytes[0].get_bits(0..=2) as usize;
|
|
|
- let (descriptor_bytes, remaining_bytes) = bytes.split_at(length+1);
|
|
|
+ let (descriptor_bytes, remaining_bytes) = bytes.split_at(length + 1);
|
|
|
|
|
|
let descriptor = match descriptor_type {
|
|
|
0x00..=0x03 => Err(AmlError::ReservedResourceType),
|
|
@@ -139,7 +138,7 @@ fn resource_descriptor(bytes: &[u8]) -> Result<(Option<Resource>, &[u8]), AmlErr
|
|
|
0x0B..=0x0D => Err(AmlError::ReservedResourceType),
|
|
|
0x0E => unimplemented!("Vendor Defined Descriptor"),
|
|
|
0x0F => return Ok((None, &[])),
|
|
|
- 0x10..=0xFF => unreachable!()
|
|
|
+ 0x10..=0xFF => unreachable!(),
|
|
|
}?;
|
|
|
|
|
|
Ok((Some(descriptor), remaining_bytes))
|
|
@@ -162,13 +161,13 @@ pub enum InterruptPolarity {
|
|
|
pub enum AddressSpaceResourceType {
|
|
|
MemoryRange,
|
|
|
IORange,
|
|
|
- BusNumberRange
|
|
|
+ BusNumberRange,
|
|
|
}
|
|
|
|
|
|
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
|
|
|
pub enum AddressSpaceDecodeType {
|
|
|
Additive,
|
|
|
- Subtractive
|
|
|
+ Subtractive,
|
|
|
}
|
|
|
|
|
|
#[derive(Debug, PartialEq, Eq)]
|
|
@@ -181,33 +180,29 @@ pub struct AddressSpaceDescriptor {
|
|
|
granularity: u64,
|
|
|
address_range: (u64, u64),
|
|
|
translation_offset: u64,
|
|
|
- length: u64
|
|
|
+ length: u64,
|
|
|
}
|
|
|
|
|
|
#[derive(Debug, PartialEq, Eq)]
|
|
|
pub enum MemoryRangeDescriptor {
|
|
|
- FixedLocation {
|
|
|
- is_writable: bool,
|
|
|
- base_address: u32,
|
|
|
- range_length: u32
|
|
|
- }
|
|
|
+ FixedLocation { is_writable: bool, base_address: u32, range_length: u32 },
|
|
|
}
|
|
|
|
|
|
fn fixed_memory_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
/*
|
|
|
* -- 32-bit Fixed Memory Descriptor ---
|
|
|
- * Offset Field Name Definition
|
|
|
+ * Offset Field Name Definition
|
|
|
* Byte 0 32-bit Fixed Memory Range Descriptor Value = 0x86 (10000110B) – Type = 1, Large item name = 0x06
|
|
|
* Byte 1 Length, bits [7:0] Value = 0x09 (9)
|
|
|
* Byte 2 Length, bits [15:8] Value = 0x00
|
|
|
- * Byte 3 Information This field provides extra information about this memory.
|
|
|
+ * Byte 3 Information This field provides extra information about this memory.
|
|
|
* Bit [7:1] Ignored
|
|
|
* Bit [0] Write status, _RW
|
|
|
* 1 writeable (read/write)
|
|
|
* 0 non-writeable (read-only)
|
|
|
- * Byte 4 Range base address, _BAS bits [7:0] Address bits [7:0] of the base memory address for which the card may be configured.
|
|
|
+ * Byte 4 Range base address, _BAS bits [7:0] Address bits [7:0] of the base memory address for which the card may be configured.
|
|
|
* Byte 5 Range base address, _BAS bits [15:8] Address bits [15:8] of the base memory address for which the card may be configured.
|
|
|
- * Byte 6 Range base address, _BAS bits [23:16] Address bits [23:16] of the base memory address for which the card may be configured.
|
|
|
+ * Byte 6 Range base address, _BAS bits [23:16] Address bits [23:16] of the base memory address for which the card may be configured.
|
|
|
* Byte 7 Range base address, _BAS bits [31:24] Address bits [31:24] of the base memory address for which the card may be configured.
|
|
|
* Byte 8 Range length, _LEN bits [7:0] This field contains bits [7:0] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
|
|
|
* Byte 9 Range length, _LEN bits [15:8] This field contains bits [15:8] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
|
|
@@ -228,11 +223,7 @@ fn fixed_memory_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
let base_address = LittleEndian::read_u32(&bytes[4..=7]);
|
|
|
let range_length = LittleEndian::read_u32(&bytes[8..=11]);
|
|
|
|
|
|
- Ok(Resource::MemoryRange(MemoryRangeDescriptor::FixedLocation {
|
|
|
- is_writable,
|
|
|
- base_address,
|
|
|
- range_length
|
|
|
- }))
|
|
|
+ Ok(Resource::MemoryRange(MemoryRangeDescriptor::FixedLocation { is_writable, base_address, range_length }))
|
|
|
}
|
|
|
|
|
|
fn address_space_descriptor<T>(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
@@ -243,8 +234,8 @@ fn address_space_descriptor<T>(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
* Offset Field Name Definition
|
|
|
* Byte 0 WORD Address Space Descriptor Value = 0x88 (10001000B) – Type = 1, Large item name = 0x08
|
|
|
* Byte 1 Length, bits [7:0] Variable length, minimum value = 0x0D (13)
|
|
|
- * Byte 2 Length, bits [15:8] Variable length, minimum value = 0x00
|
|
|
- * Byte 3 Resource Type Indicates which type of resource this descriptor describes. Defined values are:
|
|
|
+ * Byte 2 Length, bits [15:8] Variable length, minimum value = 0x00
|
|
|
+ * Byte 3 Resource Type Indicates which type of resource this descriptor describes. Defined values are:
|
|
|
* 0 Memory range
|
|
|
* 1 I/O range
|
|
|
* 2 Bus number range
|
|
@@ -252,16 +243,16 @@ fn address_space_descriptor<T>(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
* 192-255 Hardware Vendor Defined
|
|
|
* Byte 4 General Flags Flags that are common to all resource types:
|
|
|
* Bits [7:4] Reserved (must be 0)
|
|
|
- * Bit [3] Max Address Fixed, _MAF:
|
|
|
- * 1 The specified maximum address is fixed
|
|
|
+ * Bit [3] Max Address Fixed, _MAF:
|
|
|
+ * 1 The specified maximum address is fixed
|
|
|
* 0 The specified maximum address is not fixed
|
|
|
* and can be changed
|
|
|
- * Bit [2] Min Address Fixed,_MIF:
|
|
|
- * 1 The specified minimum address is fixed
|
|
|
+ * Bit [2] Min Address Fixed,_MIF:
|
|
|
+ * 1 The specified minimum address is fixed
|
|
|
* 0 The specified minimum address is not fixed
|
|
|
* and can be changed
|
|
|
- * Bit [1] Decode Type, _DEC:
|
|
|
- * 1 This bridge subtractively decodes this address (top level bridges only)
|
|
|
+ * Bit [1] Decode Type, _DEC:
|
|
|
+ * 1 This bridge subtractively decodes this address (top level bridges only)
|
|
|
* 0 This bridge positively decodes this address
|
|
|
* Bit [0] Ignored
|
|
|
* Byte 5 Type Specific Flags Flags that are specific to each resource type. The meaning of the flags in this field depends on the value of the Resource Type field (see above).
|
|
@@ -272,15 +263,15 @@ fn address_space_descriptor<T>(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
* Byte 10 Address range maximum, _MAX, bits [7:0] For bridges that translate addresses, this is the address space on the secondary side of the bridge.
|
|
|
* Byte 11 Address range maximum, _MAX, bits [15:8]
|
|
|
* Byte 12 Address Translation offset, _TRA, bits [7:0] For bridges that translate addresses across the bridge, this is the offset that must be added to the address on the secondary side to obtain the address on the primary side. Non-bridge devices must list 0 for all Address Translation offset bits.
|
|
|
- * Byte 13 Address Translation offset, _TRA, bits [15:8]
|
|
|
- * Byte 14 Address Length, _LEN, bits [7:0]
|
|
|
+ * Byte 13 Address Translation offset, _TRA, bits [15:8]
|
|
|
+ * Byte 14 Address Length, _LEN, bits [7:0]
|
|
|
* Byte 15 Address Length, _LEN, bits [15:8]
|
|
|
* Byte 16 Resource Source Index (Optional) Only present if Resource Source (below) is present. This field gives an index to the specific resource descriptor that this device consumes from in the current resource template for the device object pointed to in Resource Source.
|
|
|
- * String Resource Source (Optional) If present, the device that uses this descriptor consumes its resources from the resources produced by the named device object. If not present, the device consumes its resources out of a global pool. If not present, the device consumes this resource from its hierarchical parent.
|
|
|
+ * String Resource Source (Optional) If present, the device that uses this descriptor consumes its resources from the resources produced by the named device object. If not present, the device consumes its resources out of a global pool. If not present, the device consumes this resource from its hierarchical parent.
|
|
|
*/
|
|
|
let size = mem::size_of::<T>();
|
|
|
|
|
|
- if bytes.len() < 6 + size*5 {
|
|
|
+ if bytes.len() < 6 + size * 5 {
|
|
|
return Err(AmlError::ResourceDescriptorTooShort);
|
|
|
}
|
|
|
|
|
@@ -289,7 +280,7 @@ fn address_space_descriptor<T>(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
1 => AddressSpaceResourceType::IORange,
|
|
|
2 => AddressSpaceResourceType::BusNumberRange,
|
|
|
3..=191 => return Err(AmlError::ReservedResourceType),
|
|
|
- 192..=255 => unimplemented!()
|
|
|
+ 192..=255 => unimplemented!(),
|
|
|
};
|
|
|
|
|
|
let general_flags = bytes[4];
|
|
@@ -304,11 +295,11 @@ fn address_space_descriptor<T>(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
let mut address_fields = bytes[6..].chunks_exact(size);
|
|
|
|
|
|
// it's safe to unwrap because we check the length at the top
|
|
|
- let granularity = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
- let address_range_min = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
- let address_range_max = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
+ let granularity = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
+ let address_range_min = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
+ let address_range_max = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
let translation_offset = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
- let length = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
+ let length = LittleEndian::read_uint(address_fields.next().unwrap(), size);
|
|
|
|
|
|
Ok(Resource::AddressSpace(AddressSpaceDescriptor {
|
|
|
resource_type,
|
|
@@ -318,7 +309,7 @@ fn address_space_descriptor<T>(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
granularity,
|
|
|
address_range: (address_range_min, address_range_max),
|
|
|
translation_offset,
|
|
|
- length
|
|
|
+ length,
|
|
|
}))
|
|
|
}
|
|
|
|
|
@@ -346,30 +337,31 @@ fn irq_format_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
* Bit [0] represents IRQ0, bit[1] is IRQ1, and so on.
|
|
|
* Byte 2 IRQ mask bits[15:8], _INT
|
|
|
* Bit [0] represents IRQ8, bit[1] is IRQ9, and so on.
|
|
|
- * Byte 3 IRQ Information. Each bit, when set, indicates this device is capable of driving a certain type of interrupt.
|
|
|
- * (Optional—if not included then assume edge sensitive, high true interrupts.)
|
|
|
+ * Byte 3 IRQ Information. Each bit, when set, indicates this device is capable of driving a certain type of interrupt.
|
|
|
+ * (Optional—if not included then assume edge sensitive, high true interrupts.)
|
|
|
* These bits can be used both for reporting and setting IRQ resources.
|
|
|
* Note: This descriptor is meant for describing interrupts that are connected to PIC-compatible interrupt controllers, which can only be programmed for Active-High-Edge-Triggered or Active-Low-Level-Triggered interrupts. Any other combination is invalid. The Extended Interrupt Descriptor can be used to describe other combinations.
|
|
|
* Bit [7:6] Reserved (must be 0)
|
|
|
- * Bit [5] Wake Capability, _WKC
|
|
|
- * 0x0 = Not Wake Capable: This interrupt is not capable of waking the system.
|
|
|
+ * Bit [5] Wake Capability, _WKC
|
|
|
+ * 0x0 = Not Wake Capable: This interrupt is not capable of waking the system.
|
|
|
* 0x1 = Wake Capable: This interrupt is capable of waking the system from a
|
|
|
* low-power idle state or a system sleep state.
|
|
|
- * Bit [4] Interrupt Sharing, _SHR
|
|
|
+ * Bit [4] Interrupt Sharing, _SHR
|
|
|
* 0x0 = Exclusive: This interrupt is not shared with other devices.
|
|
|
* 0x1 = Shared: This interrupt is shared with other devices.
|
|
|
- * Bit [3] Interrupt Polarity, _LL
|
|
|
+ * Bit [3] Interrupt Polarity, _LL
|
|
|
* 0 Active-High – This interrupt is sampled when the signal is high, or true
|
|
|
* 1 Active-Low – This interrupt is sampled when the signal is low, or false.
|
|
|
* Bit [2:1] Ignored
|
|
|
- * Bit [0] Interrupt Mode, _HE
|
|
|
+ * Bit [0] Interrupt Mode, _HE
|
|
|
* 0 Level-Triggered – Interrupt is triggered in response to signal in a low state.
|
|
|
* 1 Edge-Triggered – Interrupt is triggered in response to a change in signal state from low to high.
|
|
|
*/
|
|
|
|
|
|
- match bytes.len() {
|
|
|
+ match bytes.len() {
|
|
|
0..=2 => Err(AmlError::ResourceDescriptorTooShort),
|
|
|
- 3 => { // no IRQ information ("length 2" in spec)
|
|
|
+ 3 => {
|
|
|
+ // no IRQ information ("length 2" in spec)
|
|
|
let irq = LittleEndian::read_u16(&bytes[1..=2]);
|
|
|
|
|
|
Ok(Resource::Irq(IrqDescriptor {
|
|
@@ -379,10 +371,11 @@ fn irq_format_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
polarity: InterruptPolarity::ActiveHigh,
|
|
|
trigger: InterruptTrigger::Edge,
|
|
|
|
|
|
- is_consumer: false // assumed to be producer
|
|
|
+ is_consumer: false, // assumed to be producer
|
|
|
}))
|
|
|
- },
|
|
|
- 4 => { // with IRQ information ("length 3" in spec)
|
|
|
+ }
|
|
|
+ 4 => {
|
|
|
+ // with IRQ information ("length 3" in spec)
|
|
|
let irq = LittleEndian::read_u16(&bytes[1..=2]);
|
|
|
|
|
|
let information = bytes[3];
|
|
@@ -390,11 +383,11 @@ fn irq_format_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
let is_shared = information.get_bit(4);
|
|
|
let polarity = match information.get_bit(3) {
|
|
|
false => InterruptPolarity::ActiveHigh,
|
|
|
- true => InterruptPolarity::ActiveLow
|
|
|
+ true => InterruptPolarity::ActiveLow,
|
|
|
};
|
|
|
let trigger = match information.get_bit(0) {
|
|
|
false => InterruptTrigger::Level,
|
|
|
- true => InterruptTrigger::Edge
|
|
|
+ true => InterruptTrigger::Edge,
|
|
|
};
|
|
|
|
|
|
Ok(Resource::Irq(IrqDescriptor {
|
|
@@ -404,10 +397,10 @@ fn irq_format_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
polarity,
|
|
|
trigger,
|
|
|
|
|
|
- is_consumer: false // assumed to be producer
|
|
|
+ is_consumer: false, // assumed to be producer
|
|
|
}))
|
|
|
- },
|
|
|
- _ => Err(AmlError::ResourceDescriptorTooLong)
|
|
|
+ }
|
|
|
+ _ => Err(AmlError::ResourceDescriptorTooLong),
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -416,14 +409,14 @@ pub enum DMASupportedSpeed {
|
|
|
CompatibilityMode,
|
|
|
TypeA, // as described by the EISA
|
|
|
TypeB,
|
|
|
- TypeF
|
|
|
+ TypeF,
|
|
|
}
|
|
|
|
|
|
#[derive(Debug, PartialEq, Eq)]
|
|
|
pub enum DMATransferTypePreference {
|
|
|
_8BitOnly,
|
|
|
_8And16Bit,
|
|
|
- _16Bit
|
|
|
+ _16Bit,
|
|
|
}
|
|
|
|
|
|
#[derive(Debug, PartialEq, Eq)]
|
|
@@ -431,7 +424,7 @@ pub struct DMADescriptor {
|
|
|
channel_mask: u8,
|
|
|
supported_speeds: DMASupportedSpeed,
|
|
|
is_bus_master: bool,
|
|
|
- transfer_type_preference: DMATransferTypePreference
|
|
|
+ transfer_type_preference: DMATransferTypePreference,
|
|
|
}
|
|
|
|
|
|
pub fn dma_format_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
@@ -472,7 +465,7 @@ pub fn dma_format_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
1 => DMASupportedSpeed::TypeA,
|
|
|
2 => DMASupportedSpeed::TypeB,
|
|
|
3 => DMASupportedSpeed::TypeF,
|
|
|
- _ => unreachable!()
|
|
|
+ _ => unreachable!(),
|
|
|
};
|
|
|
let is_bus_master = options.get_bit(2);
|
|
|
let transfer_type_preference = match options.get_bits(0..=1) {
|
|
@@ -480,15 +473,10 @@ pub fn dma_format_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
1 => DMATransferTypePreference::_8And16Bit,
|
|
|
2 => DMATransferTypePreference::_16Bit,
|
|
|
3 => unimplemented!("Reserved DMA transfer type preference"),
|
|
|
- _ => unreachable!()
|
|
|
+ _ => unreachable!(),
|
|
|
};
|
|
|
|
|
|
- Ok(Resource::Dma(DMADescriptor {
|
|
|
- channel_mask,
|
|
|
- supported_speeds,
|
|
|
- is_bus_master,
|
|
|
- transfer_type_preference
|
|
|
- }))
|
|
|
+ Ok(Resource::Dma(DMADescriptor { channel_mask, supported_speeds, is_bus_master, transfer_type_preference }))
|
|
|
}
|
|
|
|
|
|
#[derive(Debug, PartialEq, Eq)]
|
|
@@ -496,20 +484,20 @@ pub struct IOPortDescriptor {
|
|
|
decodes_full_address: bool,
|
|
|
memory_range: (u16, u16),
|
|
|
base_alignment: u8,
|
|
|
- range_length: u8
|
|
|
+ range_length: u8,
|
|
|
}
|
|
|
|
|
|
fn io_port_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
/*
|
|
|
* I/O Port Descriptor Definition
|
|
|
* Offset Field Name Definition
|
|
|
- * Byte 0 I/O Port Descriptor Value = 0x47 (01000111B) –
|
|
|
+ * Byte 0 I/O Port Descriptor Value = 0x47 (01000111B) –
|
|
|
* Type = 0, Small item name = 0x8, Length = 7
|
|
|
* Byte 1 Information Bits [7:1] Reserved and must be 0
|
|
|
- * Bit [0] (_DEC)
|
|
|
+ * Bit [0] (_DEC)
|
|
|
* 1 The logical device decodes 16-bit addresses
|
|
|
* 0 The logical device only decodes address bits[9:0]
|
|
|
- * Byte 2 Range minimum base address, _MIN bits[7:0] Address bits [7:0] of the minimum base I/O address that the card may be configured for.
|
|
|
+ * Byte 2 Range minimum base address, _MIN bits[7:0] Address bits [7:0] of the minimum base I/O address that the card may be configured for.
|
|
|
* Byte 3 Range minimum base address, _MIN bits[15:8] Address bits [15:8] of the minimum base I/O address that the card may be configured for.
|
|
|
* Byte 4 Range maximum base address, _MAX bits[7:0] Address bits [7:0] of the maximum base I/O address that the card may be configured for.
|
|
|
* Byte 5 Range maximum base address, _MAX bits[15:8] Address bits [15:8] of the maximum base I/O address that the card may be configured for.
|
|
@@ -534,12 +522,7 @@ fn io_port_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
let base_alignment = bytes[6];
|
|
|
let range_length = bytes[7];
|
|
|
|
|
|
- Ok(Resource::IOPort(IOPortDescriptor {
|
|
|
- decodes_full_address,
|
|
|
- memory_range,
|
|
|
- base_alignment,
|
|
|
- range_length
|
|
|
- }))
|
|
|
+ Ok(Resource::IOPort(IOPortDescriptor { decodes_full_address, memory_range, base_alignment, range_length }))
|
|
|
}
|
|
|
|
|
|
fn extended_interrupt_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
@@ -577,7 +560,6 @@ fn extended_interrupt_descriptor(bytes: &[u8]) -> Result<Resource, AmlError> {
|
|
|
}))
|
|
|
}
|
|
|
|
|
|
-
|
|
|
#[cfg(test)]
|
|
|
mod tests {
|
|
|
use super::*;
|
|
@@ -593,40 +575,55 @@ mod tests {
|
|
|
// 318: 0x01, // Alignment
|
|
|
// 319: 0x01, // Length
|
|
|
// 320: )
|
|
|
-
|
|
|
+
|
|
|
// 0000040A: 47 01 60 00 60 00 01 01 "G.`.`..."
|
|
|
0x47, 0x01, 0x60, 0x00, 0x60, 0x00, 0x01, 0x01,
|
|
|
-
|
|
|
// 321: IO (Decode16,
|
|
|
// 322: 0x0064, // Range Minimum
|
|
|
// 323: 0x0064, // Range Maximum
|
|
|
// 324: 0x01, // Alignment
|
|
|
// 325: 0x01, // Length
|
|
|
// 326: )
|
|
|
-
|
|
|
+
|
|
|
// 00000412: 47 01 64 00 64 00 01 01 "G.d.d..."
|
|
|
0x47, 0x01, 0x64, 0x00, 0x64, 0x00, 0x01, 0x01,
|
|
|
-
|
|
|
// 327: IRQNoFlags ()
|
|
|
// 328: {1}
|
|
|
-
|
|
|
+
|
|
|
// 0000041A: 22 02 00 ............... "".."
|
|
|
- 0x22, 0x02, 0x00,
|
|
|
-
|
|
|
- // 0000041D: 79 00 .................. "y."
|
|
|
+ 0x22, 0x02, 0x00, // 0000041D: 79 00 .................. "y."
|
|
|
0x79, 0x00,
|
|
|
- ].to_vec();
|
|
|
-
|
|
|
- let size: u64 = bytes.len() as u64;
|
|
|
- let value: AmlValue = AmlValue::Buffer { bytes, size };
|
|
|
+ ]
|
|
|
+ .to_vec();
|
|
|
|
|
|
+ let value: AmlValue = AmlValue::Buffer(bytes);
|
|
|
let resources = resource_descriptor_list(&value).unwrap();
|
|
|
|
|
|
- assert_eq!(resources, Vec::from([
|
|
|
- Resource::IOPort(IOPortDescriptor { decodes_full_address: true, memory_range: (0x60, 0x60), base_alignment: 1, range_length: 1 }),
|
|
|
- Resource::IOPort(IOPortDescriptor { decodes_full_address: true, memory_range: (0x64, 0x64), base_alignment: 1, range_length: 1 }),
|
|
|
- Resource::Irq(IrqDescriptor { is_consumer: false, trigger: InterruptTrigger::Edge, polarity: InterruptPolarity::ActiveHigh, is_shared: false, is_wake_capable: false, irq: (1<<1) })
|
|
|
- ]));
|
|
|
+ assert_eq!(
|
|
|
+ resources,
|
|
|
+ Vec::from([
|
|
|
+ Resource::IOPort(IOPortDescriptor {
|
|
|
+ decodes_full_address: true,
|
|
|
+ memory_range: (0x60, 0x60),
|
|
|
+ base_alignment: 1,
|
|
|
+ range_length: 1
|
|
|
+ }),
|
|
|
+ Resource::IOPort(IOPortDescriptor {
|
|
|
+ decodes_full_address: true,
|
|
|
+ memory_range: (0x64, 0x64),
|
|
|
+ base_alignment: 1,
|
|
|
+ range_length: 1
|
|
|
+ }),
|
|
|
+ Resource::Irq(IrqDescriptor {
|
|
|
+ is_consumer: false,
|
|
|
+ trigger: InterruptTrigger::Edge,
|
|
|
+ polarity: InterruptPolarity::ActiveHigh,
|
|
|
+ is_shared: false,
|
|
|
+ is_wake_capable: false,
|
|
|
+ irq: (1 << 1)
|
|
|
+ })
|
|
|
+ ])
|
|
|
+ );
|
|
|
}
|
|
|
|
|
|
#[test]
|
|
@@ -641,22 +638,19 @@ mod tests {
|
|
|
// 102: 0x0000, // Translation Offset
|
|
|
// 103: 0x0100, // Length
|
|
|
// 104: ,, )
|
|
|
-
|
|
|
+
|
|
|
// 000000F3: 88 0D 00 02 0C 00 00 00 "........"
|
|
|
// 000000FB: 00 00 FF 00 00 00 00 01 "........"
|
|
|
- 0x88, 0x0D, 0x00, 0x02, 0x0C, 0x00, 0x00, 0x00,
|
|
|
- 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x01,
|
|
|
-
|
|
|
+ 0x88, 0x0D, 0x00, 0x02, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x01,
|
|
|
// 105: IO (Decode16,
|
|
|
// 106: 0x0CF8, // Range Minimum
|
|
|
// 107: 0x0CF8, // Range Maximum
|
|
|
// 108: 0x01, // Alignment
|
|
|
// 109: 0x08, // Length
|
|
|
// 110: )
|
|
|
-
|
|
|
+
|
|
|
// 00000103: 47 01 F8 0C F8 0C 01 08 "G......."
|
|
|
0x47, 0x01, 0xF8, 0x0C, 0xF8, 0x0C, 0x01, 0x08,
|
|
|
-
|
|
|
// 111: WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
|
|
// 112: 0x0000, // Granularity
|
|
|
// 113: 0x0000, // Range Minimum
|
|
@@ -664,12 +658,10 @@ mod tests {
|
|
|
// 115: 0x0000, // Translation Offset
|
|
|
// 116: 0x0CF8, // Length
|
|
|
// 117: ,, , TypeStatic, DenseTranslation)
|
|
|
-
|
|
|
+
|
|
|
// 0000010B: 88 0D 00 01 0C 03 00 00 "........"
|
|
|
// 00000113: 00 00 F7 0C 00 00 F8 0C "........"
|
|
|
- 0x88, 0x0D, 0x00, 0x01, 0x0C, 0x03, 0x00, 0x00,
|
|
|
- 0x00, 0x00, 0xF7, 0x0C, 0x00, 0x00, 0xF8, 0x0C,
|
|
|
-
|
|
|
+ 0x88, 0x0D, 0x00, 0x01, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF7, 0x0C, 0x00, 0x00, 0xF8, 0x0C,
|
|
|
// 118: WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
|
|
// 119: 0x0000, // Granularity
|
|
|
// 120: 0x0D00, // Range Minimum
|
|
@@ -677,12 +669,10 @@ mod tests {
|
|
|
// 122: 0x0000, // Translation Offset
|
|
|
// 123: 0xF300, // Length
|
|
|
// 124: ,, , TypeStatic, DenseTranslation)
|
|
|
-
|
|
|
+
|
|
|
// 0000011B: 88 0D 00 01 0C 03 00 00 "........"
|
|
|
// 00000123: 00 0D FF FF 00 00 00 F3 "........"
|
|
|
- 0x88, 0x0D, 0x00, 0x01, 0x0C, 0x03, 0x00, 0x00,
|
|
|
- 0x00, 0x0D, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xF3,
|
|
|
-
|
|
|
+ 0x88, 0x0D, 0x00, 0x01, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x0D, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xF3,
|
|
|
// 125: DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
|
|
// 126: 0x00000000, // Granularity
|
|
|
// 127: 0x000A0000, // Range Minimum
|
|
@@ -690,16 +680,13 @@ mod tests {
|
|
|
// 129: 0x00000000, // Translation Offset
|
|
|
// 130: 0x00020000, // Length
|
|
|
// 131: ,, , AddressRangeMemory, TypeStatic)
|
|
|
-
|
|
|
+
|
|
|
// 0000012B: 87 17 00 00 0C 03 00 00 "........"
|
|
|
// 00000133: 00 00 00 00 0A 00 FF FF "........"
|
|
|
// 0000013B: 0B 00 00 00 00 00 00 00 "........"
|
|
|
// 00000143: 02 00 .................. ".."
|
|
|
- 0x87, 0x17, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00,
|
|
|
- 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0xFF, 0xFF,
|
|
|
- 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
- 0x02, 0x00,
|
|
|
-
|
|
|
+ 0x87, 0x17, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0xFF, 0xFF, 0x0B,
|
|
|
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
|
|
|
// 132: DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
|
|
|
// 133: 0x00000000, // Granularity
|
|
|
// 134: 0xE0000000, // Range Minimum
|
|
@@ -707,33 +694,82 @@ mod tests {
|
|
|
// 136: 0x00000000, // Translation Offset
|
|
|
// 137: 0x1EC00000, // Length
|
|
|
// 138: ,, _Y00, AddressRangeMemory, TypeStatic)
|
|
|
-
|
|
|
+
|
|
|
// 00000145: 87 17 00 00 0C 01 00 00 "........"
|
|
|
// 0000014D: 00 00 00 00 00 E0 FF FF "........"
|
|
|
// 00000155: BF FE 00 00 00 00 00 00 "........"
|
|
|
// 0000015D: C0 1E .................. ".."
|
|
|
- 0x87, 0x17, 0x00, 0x00, 0x0C, 0x01, 0x00, 0x00,
|
|
|
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF,
|
|
|
- 0xBF, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
- 0xC0, 0x1E,
|
|
|
-
|
|
|
+ 0x87, 0x17, 0x00, 0x00, 0x0C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xBF,
|
|
|
+ 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1E,
|
|
|
// 0000015F: 79 00 .................. "y."
|
|
|
0x79, 0x00,
|
|
|
- ].to_vec();
|
|
|
-
|
|
|
- let size: u64 = bytes.len() as u64;
|
|
|
- let value: AmlValue = AmlValue::Buffer { bytes, size };
|
|
|
+ ]
|
|
|
+ .to_vec();
|
|
|
|
|
|
+ let value: AmlValue = AmlValue::Buffer(bytes);
|
|
|
let resources = resource_descriptor_list(&value).unwrap();
|
|
|
|
|
|
- assert_eq!(resources, Vec::from([
|
|
|
- Resource::AddressSpace(AddressSpaceDescriptor { resource_type: AddressSpaceResourceType::BusNumberRange, is_maximum_address_fixed: true, is_minimum_address_fixed: true, decode_type: AddressSpaceDecodeType::Additive, granularity: 0, address_range: (0x00, 0xFF), translation_offset: 0, length: 0x100 }),
|
|
|
- Resource::IOPort(IOPortDescriptor { decodes_full_address: true, memory_range: (0xCF8, 0xCF8), base_alignment: 1, range_length: 8 }),
|
|
|
- Resource::AddressSpace(AddressSpaceDescriptor { resource_type: AddressSpaceResourceType::IORange, is_maximum_address_fixed: true, is_minimum_address_fixed: true, decode_type: AddressSpaceDecodeType::Additive, granularity: 0, address_range: (0x0000, 0x0CF7), translation_offset: 0, length: 0xCF8 }),
|
|
|
- Resource::AddressSpace(AddressSpaceDescriptor { resource_type: AddressSpaceResourceType::IORange, is_maximum_address_fixed: true, is_minimum_address_fixed: true, decode_type: AddressSpaceDecodeType::Additive, granularity: 0, address_range: (0x0D00, 0xFFFF), translation_offset: 0, length: 0xF300 }),
|
|
|
- Resource::AddressSpace(AddressSpaceDescriptor { resource_type: AddressSpaceResourceType::MemoryRange, is_maximum_address_fixed: true, is_minimum_address_fixed: true, decode_type: AddressSpaceDecodeType::Additive, granularity: 0, address_range: (0xA0000, 0xBFFFF), translation_offset: 0, length: 0x20000 }),
|
|
|
- Resource::AddressSpace(AddressSpaceDescriptor { resource_type: AddressSpaceResourceType::MemoryRange, is_maximum_address_fixed: true, is_minimum_address_fixed: true, decode_type: AddressSpaceDecodeType::Additive, granularity: 0, address_range: (0xE0000000, 0xFEBFFFFF), translation_offset: 0, length: 0x1EC00000 }),
|
|
|
- ]));
|
|
|
+ assert_eq!(
|
|
|
+ resources,
|
|
|
+ Vec::from([
|
|
|
+ Resource::AddressSpace(AddressSpaceDescriptor {
|
|
|
+ resource_type: AddressSpaceResourceType::BusNumberRange,
|
|
|
+ is_maximum_address_fixed: true,
|
|
|
+ is_minimum_address_fixed: true,
|
|
|
+ decode_type: AddressSpaceDecodeType::Additive,
|
|
|
+ granularity: 0,
|
|
|
+ address_range: (0x00, 0xFF),
|
|
|
+ translation_offset: 0,
|
|
|
+ length: 0x100
|
|
|
+ }),
|
|
|
+ Resource::IOPort(IOPortDescriptor {
|
|
|
+ decodes_full_address: true,
|
|
|
+ memory_range: (0xCF8, 0xCF8),
|
|
|
+ base_alignment: 1,
|
|
|
+ range_length: 8
|
|
|
+ }),
|
|
|
+ Resource::AddressSpace(AddressSpaceDescriptor {
|
|
|
+ resource_type: AddressSpaceResourceType::IORange,
|
|
|
+ is_maximum_address_fixed: true,
|
|
|
+ is_minimum_address_fixed: true,
|
|
|
+ decode_type: AddressSpaceDecodeType::Additive,
|
|
|
+ granularity: 0,
|
|
|
+ address_range: (0x0000, 0x0CF7),
|
|
|
+ translation_offset: 0,
|
|
|
+ length: 0xCF8
|
|
|
+ }),
|
|
|
+ Resource::AddressSpace(AddressSpaceDescriptor {
|
|
|
+ resource_type: AddressSpaceResourceType::IORange,
|
|
|
+ is_maximum_address_fixed: true,
|
|
|
+ is_minimum_address_fixed: true,
|
|
|
+ decode_type: AddressSpaceDecodeType::Additive,
|
|
|
+ granularity: 0,
|
|
|
+ address_range: (0x0D00, 0xFFFF),
|
|
|
+ translation_offset: 0,
|
|
|
+ length: 0xF300
|
|
|
+ }),
|
|
|
+ Resource::AddressSpace(AddressSpaceDescriptor {
|
|
|
+ resource_type: AddressSpaceResourceType::MemoryRange,
|
|
|
+ is_maximum_address_fixed: true,
|
|
|
+ is_minimum_address_fixed: true,
|
|
|
+ decode_type: AddressSpaceDecodeType::Additive,
|
|
|
+ granularity: 0,
|
|
|
+ address_range: (0xA0000, 0xBFFFF),
|
|
|
+ translation_offset: 0,
|
|
|
+ length: 0x20000
|
|
|
+ }),
|
|
|
+ Resource::AddressSpace(AddressSpaceDescriptor {
|
|
|
+ resource_type: AddressSpaceResourceType::MemoryRange,
|
|
|
+ is_maximum_address_fixed: true,
|
|
|
+ is_minimum_address_fixed: true,
|
|
|
+ decode_type: AddressSpaceDecodeType::Additive,
|
|
|
+ granularity: 0,
|
|
|
+ address_range: (0xE0000000, 0xFEBFFFFF),
|
|
|
+ translation_offset: 0,
|
|
|
+ length: 0x1EC00000
|
|
|
+ }),
|
|
|
+ ])
|
|
|
+ );
|
|
|
}
|
|
|
|
|
|
#[test]
|
|
@@ -745,45 +781,65 @@ mod tests {
|
|
|
// 368: 0x00, // Alignment
|
|
|
// 369: 0x04, // Length
|
|
|
// 370: )
|
|
|
-
|
|
|
+
|
|
|
// 0000047C: 47 01 F2 03 F2 03 00 04 "G......."
|
|
|
0x47, 0x01, 0xF2, 0x03, 0xF2, 0x03, 0x00, 0x04,
|
|
|
-
|
|
|
// 371: IO (Decode16,
|
|
|
// 372: 0x03F7, // Range Minimum
|
|
|
// 373: 0x03F7, // Range Maximum
|
|
|
// 374: 0x00, // Alignment
|
|
|
// 375: 0x01, // Length
|
|
|
// 376: )
|
|
|
-
|
|
|
+
|
|
|
// 00000484: 47 01 F7 03 F7 03 00 01 "G......."
|
|
|
0x47, 0x01, 0xF7, 0x03, 0xF7, 0x03, 0x00, 0x01,
|
|
|
-
|
|
|
// 377: IRQNoFlags ()
|
|
|
// 378: {6}
|
|
|
-
|
|
|
+
|
|
|
// 0000048C: 22 40 00 ............... ""@."
|
|
|
0x22, 0x40, 0x00,
|
|
|
-
|
|
|
// 379: DMA (Compatibility, NotBusMaster, Transfer8, )
|
|
|
// 380: {2}
|
|
|
-
|
|
|
- // 0000048F: 2A 04 00 ............... "*.."
|
|
|
- 0x2A, 0x04, 0x00,
|
|
|
|
|
|
- // 00000492: 79 00 .................. "y."
|
|
|
+ // 0000048F: 2A 04 00 ............... "*.."
|
|
|
+ 0x2A, 0x04, 0x00, // 00000492: 79 00 .................. "y."
|
|
|
0x79, 0x00,
|
|
|
- ].to_vec();
|
|
|
- let size: u64 = bytes.len() as u64;
|
|
|
- let value: AmlValue = AmlValue::Buffer { bytes, size };
|
|
|
+ ]
|
|
|
+ .to_vec();
|
|
|
|
|
|
+ let value: AmlValue = AmlValue::Buffer(bytes);
|
|
|
let resources = resource_descriptor_list(&value).unwrap();
|
|
|
|
|
|
- assert_eq!(resources, Vec::from([
|
|
|
- Resource::IOPort(IOPortDescriptor { decodes_full_address: true, memory_range: (0x03F2, 0x03F2), base_alignment: 0, range_length: 4 }),
|
|
|
- Resource::IOPort(IOPortDescriptor { decodes_full_address: true, memory_range: (0x03F7, 0x03F7), base_alignment: 0, range_length: 1 }),
|
|
|
- Resource::Irq(IrqDescriptor { is_consumer: false, trigger: InterruptTrigger::Edge, polarity: InterruptPolarity::ActiveHigh, is_shared: false, is_wake_capable: false, irq: (1<<6) }),
|
|
|
- Resource::Dma(DMADescriptor { channel_mask: 1<<2, supported_speeds: DMASupportedSpeed::CompatibilityMode, is_bus_master: false, transfer_type_preference: DMATransferTypePreference::_8BitOnly })
|
|
|
- ]));
|
|
|
+ assert_eq!(
|
|
|
+ resources,
|
|
|
+ Vec::from([
|
|
|
+ Resource::IOPort(IOPortDescriptor {
|
|
|
+ decodes_full_address: true,
|
|
|
+ memory_range: (0x03F2, 0x03F2),
|
|
|
+ base_alignment: 0,
|
|
|
+ range_length: 4
|
|
|
+ }),
|
|
|
+ Resource::IOPort(IOPortDescriptor {
|
|
|
+ decodes_full_address: true,
|
|
|
+ memory_range: (0x03F7, 0x03F7),
|
|
|
+ base_alignment: 0,
|
|
|
+ range_length: 1
|
|
|
+ }),
|
|
|
+ Resource::Irq(IrqDescriptor {
|
|
|
+ is_consumer: false,
|
|
|
+ trigger: InterruptTrigger::Edge,
|
|
|
+ polarity: InterruptPolarity::ActiveHigh,
|
|
|
+ is_shared: false,
|
|
|
+ is_wake_capable: false,
|
|
|
+ irq: (1 << 6)
|
|
|
+ }),
|
|
|
+ Resource::Dma(DMADescriptor {
|
|
|
+ channel_mask: 1 << 2,
|
|
|
+ supported_speeds: DMASupportedSpeed::CompatibilityMode,
|
|
|
+ is_bus_master: false,
|
|
|
+ transfer_type_preference: DMATransferTypePreference::_8BitOnly
|
|
|
+ })
|
|
|
+ ])
|
|
|
+ );
|
|
|
}
|
|
|
-}
|
|
|
+}
|