0011-j2.diff 13 KB

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  1. diff --git a/gcc/config.gcc b/gcc/config.gcc
  2. index b8bb4d65825..2c827512533 100644
  3. --- a/gcc/config.gcc
  4. +++ b/gcc/config.gcc
  5. @@ -474,7 +474,7 @@ s390*-*-*)
  6. extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
  7. ;;
  8. # Note the 'l'; we need to be able to match e.g. "shle" or "shl".
  9. -sh[123456789lbe]*-*-* | sh-*-*)
  10. +sh[123456789lbej]*-*-* | sh-*-*)
  11. cpu_type=sh
  12. extra_options="${extra_options} fused-madd.opt"
  13. extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
  14. @@ -2646,18 +2646,18 @@ s390x-ibm-tpf*)
  15. extra_options="${extra_options} s390/tpf.opt"
  16. tmake_file="${tmake_file} s390/t-s390"
  17. ;;
  18. -sh-*-elf* | sh[12346l]*-*-elf* | \
  19. - sh-*-linux* | sh[2346lbe]*-*-linux* | \
  20. +sh-*-elf* | sh[12346lj]*-*-elf* | \
  21. + sh-*-linux* | sh[2346lbej]*-*-linux* | \
  22. sh-*-netbsdelf* | shl*-*-netbsdelf*)
  23. tmake_file="${tmake_file} sh/t-sh sh/t-elf"
  24. if test x${with_endian} = x; then
  25. case ${target} in
  26. - sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
  27. + sh[j1234]*be-*-* | sh[n1234]*eb-*-*) with_endian=big ;;
  28. shbe-*-* | sheb-*-*) with_endian=big,little ;;
  29. sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
  30. shl* | sh*-*-linux* | \
  31. sh-superh-elf) with_endian=little,big ;;
  32. - sh[1234]*-*-*) with_endian=big ;;
  33. + sh[j1234]*-*-*) with_endian=big ;;
  34. *) with_endian=big,little ;;
  35. esac
  36. fi
  37. @@ -2724,6 +2724,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
  38. sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
  39. sh2a*) sh_cpu_target=sh2a ;;
  40. sh2e*) sh_cpu_target=sh2e ;;
  41. + shj2*) sh_cpu_target=shj2;;
  42. sh2*) sh_cpu_target=sh2 ;;
  43. *) sh_cpu_target=sh1 ;;
  44. esac
  45. @@ -2745,7 +2746,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
  46. sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
  47. sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
  48. sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
  49. - sh3e | sh3 | sh2e | sh2 | sh1) ;;
  50. + sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
  51. "") sh_cpu_default=${sh_cpu_target} ;;
  52. *) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
  53. esac
  54. @@ -2754,9 +2755,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
  55. case ${target} in
  56. sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
  57. sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
  58. - sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
  59. + sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
  60. sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
  61. - *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
  62. + *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
  63. esac
  64. if test x$with_fp = xno; then
  65. sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
  66. @@ -2771,7 +2772,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
  67. m1 | m2 | m2e | m3 | m3e | \
  68. m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
  69. m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
  70. - m2a | m2a-single | m2a-single-only | m2a-nofpu)
  71. + m2a | m2a-single | m2a-single-only | m2a-nofpu | \
  72. + mj2)
  73. # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
  74. # It is passed to MULTIILIB_OPTIONS verbatim.
  75. TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
  76. @@ -2788,7 +2790,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
  77. done
  78. TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
  79. if test x${enable_incomplete_targets} = xyes ; then
  80. - tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
  81. + tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
  82. fi
  83. tm_file="$tm_file ./sysroot-suffix.h"
  84. tmake_file="$tmake_file t-sysroot-suffix"
  85. @@ -4362,6 +4364,8 @@ case "${target}" in
  86. ;;
  87. m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
  88. ;;
  89. + mj2)
  90. + ;;
  91. *)
  92. echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
  93. echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
  94. @@ -4571,7 +4575,7 @@ case ${target} in
  95. tmake_file="rs6000/t-rs6000 ${tmake_file}"
  96. ;;
  97. - sh[123456ble]*-*-* | sh-*-*)
  98. + sh[123456blej]*-*-* | sh-*-*)
  99. c_target_objs="${c_target_objs} sh-c.o"
  100. cxx_target_objs="${cxx_target_objs} sh-c.o"
  101. ;;
  102. diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
  103. index b08120d..63b77fa 100644
  104. --- a/gcc/config/sh/sh-protos.h
  105. +++ b/gcc/config/sh/sh-protos.h
  106. @@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
  107. #define TARGET_ATOMIC_SOFT_IMASK \
  108. (selected_atomic_model ().type == sh_atomic_model::soft_imask)
  109. +#define TARGET_ATOMIC_HARD_CAS \
  110. + (selected_atomic_model ().type == sh_atomic_model::hard_cas)
  111. +
  112. #ifdef RTX_CODE
  113. extern rtx sh_fsca_sf2int (void);
  114. extern rtx sh_fsca_int2sf (void);
  115. diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
  116. index b18e59b..88520e8 100644
  117. --- a/gcc/config/sh/sh.c
  118. +++ b/gcc/config/sh/sh.c
  119. @@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str)
  120. model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
  121. model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
  122. model_names[sh_atomic_model::soft_imask] = "soft-imask";
  123. + model_names[sh_atomic_model::hard_cas] = "hard-cas";
  124. const char* model_cdef_names[sh_atomic_model::num_models];
  125. model_cdef_names[sh_atomic_model::none] = "NONE";
  126. @@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str)
  127. model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
  128. model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
  129. model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
  130. + model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
  131. sh_atomic_model ret;
  132. ret.type = sh_atomic_model::none;
  133. @@ -780,6 +782,9 @@ got_mode_name:;
  134. if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
  135. err_ret ("cannot use atomic model %s in user mode", ret.name);
  136. + if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
  137. + err_ret ("atomic model %s is only available J2 targets", ret.name);
  138. +
  139. return ret;
  140. #undef err_ret
  141. @@ -845,6 +850,8 @@ sh_option_override (void)
  142. sh_cpu = PROCESSOR_SH2E;
  143. if (TARGET_SH2A)
  144. sh_cpu = PROCESSOR_SH2A;
  145. + if (TARGET_SHJ2)
  146. + sh_cpu = PROCESSOR_SHJ2;
  147. if (TARGET_SH3)
  148. sh_cpu = PROCESSOR_SH3;
  149. if (TARGET_SH3E)
  150. diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
  151. index b13d1b3c943..8f483635747 100644
  152. --- a/gcc/config/sh/sh.h
  153. +++ b/gcc/config/sh/sh.h
  154. @@ -83,6 +83,7 @@ extern int code_for_indirect_jump_scratch;
  155. #define SUPPORT_SH4_SINGLE 1
  156. #define SUPPORT_SH2A 1
  157. #define SUPPORT_SH2A_SINGLE 1
  158. +#define SUPPORT_SHJ2 1
  159. #endif
  160. #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
  161. @@ -115,6 +116,7 @@ extern int code_for_indirect_jump_scratch;
  162. #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
  163. #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
  164. #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
  165. +#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
  166. #if SUPPORT_SH1
  167. #define SUPPORT_SH2 1
  168. @@ -122,6 +124,7 @@ extern int code_for_indirect_jump_scratch;
  169. #if SUPPORT_SH2
  170. #define SUPPORT_SH3 1
  171. #define SUPPORT_SH2A_NOFPU 1
  172. +#define SUPPORT_SHJ2 1
  173. #endif
  174. #if SUPPORT_SH3
  175. #define SUPPORT_SH4_NOFPU 1
  176. @@ -154,7 +157,7 @@ extern int code_for_indirect_jump_scratch;
  177. #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
  178. | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
  179. | MASK_HARD_SH4 | MASK_FPU_SINGLE \
  180. - | MASK_FPU_SINGLE_ONLY)
  181. + | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
  182. /* This defaults us to big-endian. */
  183. #ifndef TARGET_ENDIAN_DEFAULT
  184. @@ -229,7 +232,8 @@ extern int code_for_indirect_jump_scratch;
  185. %{m2a-single:--isa=sh2a} \
  186. %{m2a-single-only:--isa=sh2a} \
  187. %{m2a-nofpu:--isa=sh2a-nofpu} \
  188. -%{m4al:-dsp}"
  189. +%{m4al:-dsp} \
  190. +%{mj2:-isa=j2}"
  191. #define ASM_SPEC SH_ASM_SPEC
  192. @@ -345,6 +349,7 @@ struct sh_atomic_model
  193. hard_llcs,
  194. soft_tcb,
  195. soft_imask,
  196. + hard_cas,
  197. num_models
  198. };
  199. @@ -1568,7 +1573,7 @@ extern bool current_function_interrupt;
  200. /* Nonzero if the target supports dynamic shift instructions
  201. like shad and shld. */
  202. -#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
  203. +#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
  204. /* The cost of using the dynamic shift insns (shad, shld) are the same
  205. if they are available. If they are not available a library function will
  206. @@ -1833,6 +1838,7 @@ enum processor_type {
  207. PROCESSOR_SH2,
  208. PROCESSOR_SH2E,
  209. PROCESSOR_SH2A,
  210. + PROCESSOR_SHJ2,
  211. PROCESSOR_SH3,
  212. PROCESSOR_SH3E,
  213. PROCESSOR_SH4,
  214. diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
  215. index 1026c73..bac47ed 100644
  216. --- a/gcc/config/sh/sh.opt
  217. +++ b/gcc/config/sh/sh.opt
  218. @@ -71,6 +71,10 @@ m2e
  219. Target RejectNegative Condition(SUPPORT_SH2E)
  220. Generate SH2e code.
  221. +mj2
  222. +Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
  223. +Generate J2 code.
  224. +
  225. m3
  226. Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
  227. Generate SH3 code.
  228. diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
  229. index 6f1337b..7cfd9ef 100644
  230. --- a/gcc/config/sh/sync.md
  231. +++ b/gcc/config/sh/sync.md
  232. @@ -240,6 +240,9 @@
  233. || (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
  234. atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
  235. exp_val, new_val);
  236. + else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
  237. + atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
  238. + exp_val, new_val);
  239. else if (TARGET_ATOMIC_SOFT_GUSA)
  240. atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
  241. exp_val, new_val);
  242. @@ -306,6 +309,57 @@
  243. }
  244. [(set_attr "length" "14")])
  245. +(define_expand "atomic_compare_and_swapsi_cas"
  246. + [(set (match_operand:SI 0 "register_operand" "=r")
  247. + (unspec_volatile:SI
  248. + [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
  249. + (match_operand:SI 2 "register_operand" "r")
  250. + (match_operand:SI 3 "register_operand" "r")]
  251. + UNSPECV_CMPXCHG_1))]
  252. + "TARGET_ATOMIC_HARD_CAS"
  253. +{
  254. + rtx mem = gen_rtx_REG (SImode, 0);
  255. + emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
  256. + emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
  257. + DONE;
  258. +})
  259. +
  260. +(define_insn "shj2_cas"
  261. + [(set (match_operand:SI 0 "register_operand" "=&r")
  262. + (unspec_volatile:SI
  263. + [(match_operand:SI 1 "register_operand" "=r")
  264. + (match_operand:SI 2 "register_operand" "r")
  265. + (match_operand:SI 3 "register_operand" "0")]
  266. + UNSPECV_CMPXCHG_1))
  267. + (set (reg:SI T_REG)
  268. + (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
  269. + "TARGET_ATOMIC_HARD_CAS"
  270. + "cas.l %2,%0,@%1"
  271. + [(set_attr "length" "2")]
  272. +)
  273. +
  274. +(define_expand "atomic_compare_and_swapqi_cas"
  275. + [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
  276. + (unspec_volatile:SI
  277. + [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
  278. + (match_operand:SI 2 "arith_operand" "rI08")
  279. + (match_operand:SI 3 "arith_operand" "rI08")]
  280. + UNSPECV_CMPXCHG_1))]
  281. + "TARGET_ATOMIC_HARD_CAS"
  282. +{FAIL;}
  283. +)
  284. +
  285. +(define_expand "atomic_compare_and_swaphi_cas"
  286. + [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
  287. + (unspec_volatile:SI
  288. + [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
  289. + (match_operand:SI 2 "arith_operand" "rI08")
  290. + (match_operand:SI 3 "arith_operand" "rI08")]
  291. + UNSPECV_CMPXCHG_1))]
  292. + "TARGET_ATOMIC_HARD_CAS"
  293. +{FAIL;}
  294. +)
  295. +
  296. ;; The QIHImode llcs patterns modify the address register of the memory
  297. ;; operand. In order to express that, we have to open code the memory
  298. ;; operand. Initially the insn is expanded like every other atomic insn
  299. diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
  300. index 409554a8c8d..d354c11c8f2 100644
  301. --- a/gcc/config/sh/t-sh
  302. +++ b/gcc/config/sh/t-sh
  303. @@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
  304. m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
  305. m2a-single,m2a-single-only \
  306. m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
  307. - m4,m4-100,m4-200,m4-300,m4a; do \
  308. + m4,m4-100,m4-200,m4-300,m4a \
  309. + mj2; do \
  310. subst= ; \
  311. for lib in `echo $$abi|tr , ' '` ; do \
  312. if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
  313. @@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
  314. # SH1 and SH2A support big endian only.
  315. ifeq ($(DEFAULT_ENDIAN),ml)
  316. -MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  317. +MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  318. else
  319. -MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  320. +MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
  321. endif
  322. MULTILIB_OSDIRNAMES = \
  323. @@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
  324. m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
  325. m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
  326. m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
  327. - m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
  328. + m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
  329. + mj2=!j2
  330. $(out_object_file): gt-sh.h
  331. gt-sh.h : s-gtype ; @true