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0002-cas.diff

0002-cas.diff 49 KB
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  1. diff --git a/bfd/archures.c b/bfd/archures.c
    2. 

  2. index 51068b9..c67d76b 100644
    3. 

  3. --- a/bfd/archures.c
    4. 

  4. +++ b/bfd/archures.c
    5. 

  5. @@ -294,10 +294,12 @@ DESCRIPTION
    6. 

  6.  .#define bfd_mach_sh_dsp     0x2d
    7. 

  7.  .#define bfd_mach_sh2a       0x2a
    8. 

  8.  .#define bfd_mach_sh2a_nofpu 0x2b
    9. 

  9. +.#define bfd_mach_shj2       0x2c
    10. 

  10.  .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
    11. 

  11.  .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
    12. 

  12.  .#define bfd_mach_sh2a_or_sh4  0x2a3
    13. 

  13.  .#define bfd_mach_sh2a_or_sh3e 0x2a4
    14. 

  14. +.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
    15. 

  15.  .#define bfd_mach_sh2e       0x2e
    16. 

  16.  .#define bfd_mach_sh3        0x30
    17. 

  17.  .#define bfd_mach_sh3_nommu  0x31
    18. 

  18. diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
    19. 

  19. index ca0cafd..99e92c6 100644
    20. 

  20. --- a/bfd/bfd-in2.h
    21. 

  21. +++ b/bfd/bfd-in2.h
    22. 

  22. @@ -2109,10 +2109,12 @@ enum bfd_architecture
    23. 

  23.  #define bfd_mach_sh_dsp     0x2d
    24. 

  24.  #define bfd_mach_sh2a       0x2a
    25. 

  25.  #define bfd_mach_sh2a_nofpu 0x2b
    26. 

  26. +#define bfd_mach_shj2       0x2c
    27. 

  27.  #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
    28. 

  28.  #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
    29. 

  29.  #define bfd_mach_sh2a_or_sh4  0x2a3
    30. 

  30.  #define bfd_mach_sh2a_or_sh3e 0x2a4
    31. 

  31. +#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
    32. 

  32.  #define bfd_mach_sh2e       0x2e
    33. 

  33.  #define bfd_mach_sh3        0x30
    34. 

  34.  #define bfd_mach_sh3_nommu  0x31
    35. 

  35. diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c
    36. 

  36. index d516d66..66d21a5 100644
    37. 

  37. --- a/bfd/cpu-sh.c
    38. 

  38. +++ b/bfd/cpu-sh.c
    39. 

  39. @@ -44,7 +44,9 @@
    40. 

  40.  #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT       arch_info_struct + 17
    41. 

  41.  #define SH2A_OR_SH4_NEXT                   arch_info_struct + 18
    42. 

  42.  #define SH2A_OR_SH3E_NEXT                  arch_info_struct + 19
    43. 

  43. -#define SH64_NEXT                          NULL
    44. 

  44. +#define SH64_NEXT                          arch_info_struct + 20
    45. 

  45. +#define SHJ2_NEXT       		   arch_info_struct + 21
    46. 

  46. +#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT       NULL
    47. 

  47.  
    48. 

  48.  static const bfd_arch_info_type arch_info_struct[] =
    49. 

  49.  {
    50. 

  50. @@ -348,6 +350,36 @@ static const bfd_arch_info_type arch_info_struct[] =
    51. 

  51.      bfd_arch_default_fill,
    52. 

  52.      SH64_NEXT
    53. 

  53.    },
    54. 

  54. +  {
    55. 

  55. +    32,				/* 32 bits in a word.  */
    56. 

  56. +    32,				/* 32 bits in an address.  */
    57. 

  57. +    8,				/* 8 bits in a byte.  */
    58. 

  58. +    bfd_arch_sh,
    59. 

  59. +    bfd_mach_shj2,
    60. 

  60. +    "sh",			/* Architecture name. .  */
    61. 

  61. +    "j2",			/* Machine name.  */
    62. 

  62. +    1,
    63. 

  63. +    FALSE,			/* Not the default.  */
    64. 

  64. +    bfd_default_compatible,
    65. 

  65. +    bfd_default_scan,
    66. 

  66. +    bfd_arch_default_fill,
    67. 

  67. +    SHJ2_NEXT
    68. 

  68. +  },
    69. 

  69. +  {
    70. 

  70. +    32,				/* 32 bits in a word.  */
    71. 

  71. +    32,				/* 32 bits in an address.  */
    72. 

  72. +    8,				/* 8 bits in a byte.  */
    73. 

  73. +    bfd_arch_sh,
    74. 

  74. +    bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
    75. 

  75. +    "sh",			/* Architecture name. .  */
    76. 

  76. +    "sh2a-or-sh3e-or-j2",	/* Machine name.  */
    77. 

  77. +    1,
    78. 

  78. +    FALSE,			/* Not the default.  */
    79. 

  79. +    bfd_default_compatible,
    80. 

  80. +    bfd_default_scan,
    81. 

  81. +    bfd_arch_default_fill,
    82. 

  82. +    SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
    83. 

  83. +  },
    84. 

  84.  };
    85. 

  85.  
    86. 

  86.  const bfd_arch_info_type bfd_sh_arch =
    87. 

  87. @@ -398,6 +430,8 @@ static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] =
    88. 

  88.    { bfd_mach_sh4_nofpu,       arch_sh4_nofpu,       arch_sh4_nofpu_up },
    89. 

  89.    { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
    90. 

  90.    { bfd_mach_sh4a_nofpu,      arch_sh4a_nofpu,      arch_sh4a_nofpu_up },
    91. 

  91. +  { bfd_mach_shj2,            arch_shj2,            arch_shj2_up },
    92. 

  92. +  { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
    93. 

  93.    { 0, 0, 0 }   /* Terminator.  */
    94. 

  94.  };
    95. 

  95.  
    96. 

  96. diff --git a/binutils/readelf.c b/binutils/readelf.c
    97. 

  97. index a31db52..5ec21b0 100644
    98. 

  98. --- a/binutils/readelf.c
    99. 

  99. +++ b/binutils/readelf.c
    100. 

  100. @@ -3217,6 +3217,8 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
    101. 

  101.  	    case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
    102. 

  102.  	    case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
    103. 

  103.  	    case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
    104. 

  104. +	    case EF_SHJ2: strcat (buf, ", j2"); break;
    105. 

  105. +	    case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
    106. 

  106.  	    default: strcat (buf, _(", unknown ISA")); break;
    107. 

  107.  	    }
    108. 

  108.  
    109. 

  109. diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
    110. 

  110. index 125f073..37f6fb0 100644
    111. 

  111. --- a/gas/config/tc-sh.c
    112. 

  112. +++ b/gas/config/tc-sh.c
    113. 

  113. @@ -1648,6 +1648,8 @@ get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand)
    114. 

  114.  		  ptr++;
    115. 

  115.  		}
    116. 

  116.  	      get_operand (&ptr, operand + 2);
    117. 

  117. +	      if (strcmp (info->name,"cas") == 0)
    118. 

  118. +		operand[2].type = A_IND_0;
    119. 

  119.  	    }
    120. 

  120.  	  else
    121. 

  121.  	    {
    122. 

  122. @@ -2187,7 +2189,10 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
    123. 

  123.  		goto fail;
    124. 

  124.  	      reg_m = 4;
    125. 

  125.  	      break;
    126. 

  126. -
    127. 

  127. +	    case A_IND_0:
    128. 

  128. +	      if (user->reg != 0)
    129. 

  129. +		goto fail;
    130. 

  130. +	      break;
    131. 

  131.  	    default:
    132. 

  132.  	      printf (_("unhandled %d\n"), arg);
    133. 

  133.  	      goto fail;
    134. 

  134. diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
    135. 

  135. index cc29889..a3e18b5 100644
    136. 

  136. --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
    137. 

  137. +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
    138. 

  138. @@ -12,7 +12,5 @@
    139. 

  139.  sh2a_nofpu_or_sh3_nommu:
    140. 

  140.  ! Instructions introduced into sh2a-nofpu-or-sh3-nommu
    141. 

  141. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    142. 

  142. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    143. 

  143.  
    144. 

  144.  ! Instructions inherited from ancestors: sh sh2
    145. 

  145.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    146. 

  146. diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    147. 

  147. index c702845..812aa76 100644
    148. 

  148. --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    149. 

  149. +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    150. 

  150. @@ -12,7 +12,7 @@
    151. 

  151.  sh2a_nofpu_or_sh4_nommu_nofpu:
    152. 

  152.  ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
    153. 

  153.  
    154. 

  154. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
    155. 

  155. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
    156. 

  156.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    157. 

  157.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    158. 

  158.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    159. 

  159. @@ -119,8 +119,8 @@ sh2a_nofpu_or_sh4_nommu_nofpu:
    160. 

  160.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    161. 

  161.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    162. 

  162.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    163. 

  163. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    164. 

  164. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    165. 

  165. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    166. 

  166. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    167. 

  167.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    168. 

  168.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    169. 

  169.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    170. 

  170. diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
    171. 

  171. index 6f4a17e..5b38643 100644
    172. 

  172. --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
    173. 

  173. +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
    174. 

  174. @@ -64,7 +64,7 @@ sh2a_nofpu:
    175. 

  175.  	movu.b @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
    176. 

  176.  	movu.w @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
    177. 

  177.  
    178. 

  178. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
    179. 

  179. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
    180. 

  180.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    181. 

  181.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    182. 

  182.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    183. 

  183. @@ -171,8 +171,8 @@ sh2a_nofpu:
    184. 

  184.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    185. 

  185.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    186. 

  186.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    187. 

  187. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    188. 

  188. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    189. 

  189. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    190. 

  190. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    191. 

  191.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    192. 

  192.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    193. 

  193.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    194. 

  194. diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
    195. 

  195. index 25c8ae1..69d3536 100644
    196. 

  196. --- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
    197. 

  197. +++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
    198. 

  198. @@ -13,7 +13,7 @@ sh2a_or_sh3e:
    199. 

  199.  ! Instructions introduced into sh2a-or-sh3e
    200. 

  200.  	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
    201. 

  201.  
    202. 

  202. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
    203. 

  203. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
    204. 

  204.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    205. 

  205.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    206. 

  206.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    207. 

  207. @@ -124,8 +124,8 @@ sh2a_or_sh3e:
    208. 

  208.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    209. 

  209.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    210. 

  210.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    211. 

  211. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    212. 

  212. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    213. 

  213. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    214. 

  214. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    215. 

  215.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    216. 

  216.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    217. 

  217.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    218. 

  218. diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
    219. 

  219. index d3300ca..c697268 100644
    220. 

  220. --- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
    221. 

  221. +++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
    222. 

  222. @@ -39,7 +39,7 @@ sh2a_or_sh4:
    223. 

  223.  	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
    224. 

  224.  	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
    225. 

  225.  
    226. 

  226. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
    227. 

  227. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
    228. 

  228.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    229. 

  229.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    230. 

  230.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    231. 

  231. @@ -150,8 +150,8 @@ sh2a_or_sh4:
    232. 

  232.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    233. 

  233.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    234. 

  234.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    235. 

  235. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    236. 

  236. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    237. 

  237. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    238. 

  238. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    239. 

  239.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    240. 

  240.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    241. 

  241.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    242. 

  242. diff --git a/gas/testsuite/gas/sh/arch/sh2a.s b/gas/testsuite/gas/sh/arch/sh2a.s
    243. 

  243. index 370dbd4..0d9f3b0 100644
    244. 

  244. --- a/gas/testsuite/gas/sh/arch/sh2a.s
    245. 

  245. +++ b/gas/testsuite/gas/sh/arch/sh2a.s
    246. 

  246. @@ -16,7 +16,7 @@ sh2a:
    247. 

  247.  	fmov.s fr2,@(2048,r4)     ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */  {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
    248. 

  248.  	fmov.s @(2048,r5),fr1     ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */  {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
    249. 

  249.  
    250. 

  250. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
    251. 

  251. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
    252. 

  252.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    253. 

  253.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    254. 

  254.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    255. 

  255. @@ -140,8 +140,8 @@ sh2a:
    256. 

  256.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    257. 

  257.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    258. 

  258.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    259. 

  259. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    260. 

  260. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    261. 

  261. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    262. 

  262. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    263. 

  263.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    264. 

  264.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    265. 

  265.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    266. 

  266. diff --git a/gas/testsuite/gas/sh/arch/sh3-dsp.s b/gas/testsuite/gas/sh/arch/sh3-dsp.s
    267. 

  267. index acc26be..cfd4dfe 100644
    268. 

  268. --- a/gas/testsuite/gas/sh/arch/sh3-dsp.s
    269. 

  269. +++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s
    270. 

  270. @@ -12,7 +12,7 @@
    271. 

  271.  sh3_dsp:
    272. 

  272.  ! Instructions introduced into sh3-dsp
    273. 

  273.  
    274. 

  274. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
    275. 

  275. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
    276. 

  276.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    277. 

  277.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    278. 

  278.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    279. 

  279. @@ -152,8 +152,8 @@ sh3_dsp:
    280. 

  280.  	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
    281. 

  281.  	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
    282. 

  282.  	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
    283. 

  283. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    284. 

  284. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    285. 

  285. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    286. 

  286. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    287. 

  287.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    288. 

  288.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    289. 

  289.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    290. 

  290. diff --git a/gas/testsuite/gas/sh/arch/sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh3-nommu.s
    291. 

  291. index 3e8ff02..dacaae1 100644
    292. 

  292. --- a/gas/testsuite/gas/sh/arch/sh3-nommu.s
    293. 

  293. +++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s
    294. 

  294. @@ -26,7 +26,7 @@ sh3_nommu:
    295. 

  295.  	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
    296. 

  296.  	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
    297. 

  297.  
    298. 

  298. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
    299. 

  299. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
    300. 

  300.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    301. 

  301.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    302. 

  302.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    303. 

  303. @@ -133,8 +133,8 @@ sh3_nommu:
    304. 

  304.  	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
    305. 

  305.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    306. 

  306.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    307. 

  307. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    308. 

  308. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    309. 

  309. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    310. 

  310. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    311. 

  311.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    312. 

  312.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    313. 

  313.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    314. 

  314. diff --git a/gas/testsuite/gas/sh/arch/sh3.s b/gas/testsuite/gas/sh/arch/sh3.s
    315. 

  315. index 97ab939..aa70fc3 100644
    316. 

  316. --- a/gas/testsuite/gas/sh/arch/sh3.s
    317. 

  317. +++ b/gas/testsuite/gas/sh/arch/sh3.s
    318. 

  318. @@ -13,7 +13,7 @@ sh3:
    319. 

  319.  ! Instructions introduced into sh3
    320. 

  320.  	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
    321. 

  321.  
    322. 

  322. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
    323. 

  323. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
    324. 

  324.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    325. 

  325.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    326. 

  326.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    327. 

  327. @@ -128,8 +128,8 @@ sh3:
    328. 

  328.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    329. 

  329.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    330. 

  330.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    331. 

  331. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    332. 

  332. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    333. 

  333. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    334. 

  334. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    335. 

  335.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    336. 

  336.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    337. 

  337.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    338. 

  338. diff --git a/gas/testsuite/gas/sh/arch/sh3e.s b/gas/testsuite/gas/sh/arch/sh3e.s
    339. 

  339. index f5c8ab9..215e5ec 100644
    340. 

  340. --- a/gas/testsuite/gas/sh/arch/sh3e.s
    341. 

  341. +++ b/gas/testsuite/gas/sh/arch/sh3e.s
    342. 

  342. @@ -12,7 +12,7 @@
    343. 

  343.  sh3e:
    344. 

  344.  ! Instructions introduced into sh3e
    345. 

  345.  
    346. 

  346. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
    347. 

  347. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
    348. 

  348.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    349. 

  349.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    350. 

  350.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    351. 

  351. @@ -132,8 +132,8 @@ sh3e:
    352. 

  352.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    353. 

  353.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    354. 

  354.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    355. 

  355. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    356. 

  356. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    357. 

  357. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    358. 

  358. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    359. 

  359.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    360. 

  360.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    361. 

  361.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    362. 

  362. diff --git a/gas/testsuite/gas/sh/arch/sh4-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
    363. 

  363. index 32b58f9..1fef035 100644
    364. 

  364. --- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s
    365. 

  365. +++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
    366. 

  366. @@ -12,7 +12,7 @@
    367. 

  367.  sh4_nofpu:
    368. 

  368.  ! Instructions introduced into sh4-nofpu
    369. 

  369.  
    370. 

  370. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
    371. 

  371. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
    372. 

  372.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    373. 

  373.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    374. 

  374.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    375. 

  375. @@ -136,8 +136,8 @@ sh4_nofpu:
    376. 

  376.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    377. 

  377.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    378. 

  378.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    379. 

  379. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    380. 

  380. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    381. 

  381. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    382. 

  382. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    383. 

  383.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    384. 

  384.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    385. 

  385.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    386. 

  386. diff --git a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
    387. 

  387. index 61f0bc6..65d11c5 100644
    388. 

  388. --- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
    389. 

  389. +++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
    390. 

  390. @@ -24,7 +24,7 @@ sh4_nommu_nofpu:
    391. 

  391.  	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
    392. 

  392.  	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
    393. 

  393.  
    394. 

  394. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
    395. 

  395. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
    396. 

  396.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    397. 

  397.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    398. 

  398.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    399. 

  399. @@ -139,8 +139,8 @@ sh4_nommu_nofpu:
    400. 

  400.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    401. 

  401.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    402. 

  402.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    403. 

  403. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    404. 

  404. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    405. 

  405. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    406. 

  406. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    407. 

  407.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    408. 

  408.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    409. 

  409.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    410. 

  410. diff --git a/gas/testsuite/gas/sh/arch/sh4.s b/gas/testsuite/gas/sh/arch/sh4.s
    411. 

  411. index af135ce..dc199cb 100644
    412. 

  412. --- a/gas/testsuite/gas/sh/arch/sh4.s
    413. 

  413. +++ b/gas/testsuite/gas/sh/arch/sh4.s
    414. 

  414. @@ -17,7 +17,7 @@ sh4:
    415. 

  415.  	fsrra fr1                 ;!/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
    416. 

  416.  	ftrv xmtrx,fv0            ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
    417. 

  417.  
    418. 

  418. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
    419. 

  419. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
    420. 

  420.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    421. 

  421.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    422. 

  422.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    423. 

  423. @@ -145,8 +145,8 @@ sh4:
    424. 

  424.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    425. 

  425.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    426. 

  426.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    427. 

  427. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    428. 

  428. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    429. 

  429. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    430. 

  430. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    431. 

  431.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    432. 

  432.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    433. 

  433.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    434. 

  434. diff --git a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
    435. 

  435. index 9522bb6..7581f47 100644
    436. 

  436. --- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
    437. 

  437. +++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
    438. 

  438. @@ -19,7 +19,7 @@ sh4a_nofpu:
    439. 

  439.  	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
    440. 

  440.  	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
    441. 

  441.  
    442. 

  442. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
    443. 

  443. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
    444. 

  444.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    445. 

  445.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    446. 

  446.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    447. 

  447. @@ -143,8 +143,8 @@ sh4a_nofpu:
    448. 

  448.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    449. 

  449.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    450. 

  450.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    451. 

  451. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    452. 

  452. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    453. 

  453. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    454. 

  454. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    455. 

  455.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    456. 

  456.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    457. 

  457.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    458. 

  458. diff --git a/gas/testsuite/gas/sh/arch/sh4a.s b/gas/testsuite/gas/sh/arch/sh4a.s
    459. 

  459. index 950ed2d..55e9611 100644
    460. 

  460. --- a/gas/testsuite/gas/sh/arch/sh4a.s
    461. 

  461. +++ b/gas/testsuite/gas/sh/arch/sh4a.s
    462. 

  462. @@ -13,7 +13,7 @@ sh4a:
    463. 

  463.  ! Instructions introduced into sh4a
    464. 

  464.  	fpchg                     ;!/* 1111011111111101 fpchg               */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
    465. 

  465.  
    466. 

  466. -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    467. 

  467. +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    468. 

  468.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    469. 

  469.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    470. 

  470.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    471. 

  471. @@ -147,8 +147,8 @@ sh4a:
    472. 

  472.  	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
    473. 

  473.  	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
    474. 

  474.  	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
    475. 

  475. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    476. 

  476. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    477. 

  477. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    478. 

  478. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    479. 

  479.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    480. 

  480.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    481. 

  481.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    482. 

  482. diff --git a/gas/testsuite/gas/sh/arch/sh4al-dsp.s b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
    483. 

  483. index 6caaf2c..fde6c1e 100644
    484. 

  484. --- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s
    485. 

  485. +++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
    486. 

  486. @@ -48,7 +48,7 @@ sh4al_dsp:
    487. 

  487.  	dct pswap x1,m0           ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */  {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
    488. 

  488.  	dct pswap y0,m0           ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */  {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
    489. 

  489.  
    490. 

  490. -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    491. 

  491. +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
    492. 

  492.  	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
    493. 

  493.  	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
    494. 

  494.  	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
    495. 

  495. @@ -202,8 +202,8 @@ sh4al_dsp:
    496. 

  496.  	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
    497. 

  497.  	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
    498. 

  498.  	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
    499. 

  499. -	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
    500. 

  500. -	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
    501. 

  501. +	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    502. 

  502. +	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
    503. 

  503.  	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
    504. 

  504.  	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
    505. 

  505.  	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    506. 

  506. diff --git a/include/elf/sh.h b/include/elf/sh.h
    507. 

  507. index a54158f..109d90f 100644
    508. 

  508. --- a/include/elf/sh.h
    509. 

  509. +++ b/include/elf/sh.h
    510. 

  510. @@ -35,6 +35,7 @@
    511. 

  511.  #define EF_SH2E            11
    512. 

  512.  #define EF_SH4A		   12
    513. 

  513.  #define EF_SH2A            13
    514. 

  514. +#define EF_SHJ2            14
    515. 

  515.  
    516. 

  516.  #define EF_SH4_NOFPU	   16
    517. 

  517.  #define EF_SH4A_NOFPU	   17
    518. 

  518. @@ -46,6 +47,7 @@
    519. 

  519.  #define EF_SH2A_SH3_NOFPU  22
    520. 

  520.  #define EF_SH2A_SH4        23
    521. 

  521.  #define EF_SH2A_SH3E       24
    522. 

  522. +#define EF_SH2A_SH3_SHJ2   25
    523. 

  523.  
    524. 

  524.  /* This one can only mix in objects from other EF_SH5 objects.  */
    525. 

  525.  #define EF_SH5		  10
    526. 

  526. @@ -68,7 +70,8 @@
    527. 

  527.  /* EF_SH2E		*/ bfd_mach_sh2e	, \
    528. 

  528.  /* EF_SH4A		*/ bfd_mach_sh4a	, \
    529. 

  529.  /* EF_SH2A		*/ bfd_mach_sh2a        , \
    530. 

  530. -/* 14, 15		*/ 0, 0, \
    531. 

  531. +/* EF_SHJ2		*/ bfd_mach_shj2        , \
    532. 

  532. +/* 15			*/ 0, \
    533. 

  533.  /* EF_SH4_NOFPU		*/ bfd_mach_sh4_nofpu	, \
    534. 

  534.  /* EF_SH4A_NOFPU	*/ bfd_mach_sh4a_nofpu	, \
    535. 

  535.  /* EF_SH4_NOMMU_NOFPU	*/ bfd_mach_sh4_nommu_nofpu, \
    536. 

  536. @@ -77,7 +80,8 @@
    537. 

  537.  /* EF_SH2A_SH4_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
    538. 

  538.  /* EF_SH2A_SH3_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
    539. 

  539.  /* EF_SH2A_SH4          */ bfd_mach_sh2a_or_sh4 , \
    540. 

  540. -/* EF_SH2A_SH3E         */ bfd_mach_sh2a_or_sh3e
    541. 

  541. +/* EF_SH2A_SH3E         */ bfd_mach_sh2a_or_sh3e, \
    542. 

  542. +/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
    543. 

  543.  
    544. 

  544.  /* Convert arch_sh* into EF_SH*.  */
    545. 

  545.  int sh_find_elf_flags (unsigned int arch_set);
    546. 

  546. diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
    547. 

  547. index d4e1a6d..181e21a 100644
    548. 

  548. --- a/opcodes/sh-dis.c
    549. 

  549. +++ b/opcodes/sh-dis.c
    550. 

  550. @@ -868,6 +868,9 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
    551. 

  551.  	    case XMTRX_M4:
    552. 

  552.  	      fprintf_fn (stream, "xmtrx");
    553. 

  553.  	      break;
    554. 

  554. +	    case A_IND_0:
    555. 

  555. +	      fprintf_fn (stream, "@r0");
    556. 

  556. +	      break;
    557. 

  557.  	    default:
    558. 

  558.  	      abort ();
    559. 

  559.  	    }
    560. 

  560. diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
    561. 

  561. index 5863aa9..19c5a61 100644
    562. 

  562. --- a/opcodes/sh-opc.h
    563. 

  563. +++ b/opcodes/sh-opc.h
    564. 

  564. @@ -187,7 +187,8 @@ typedef enum
    565. 

  565.      FPUL_N,
    566. 

  566.      FPUL_M,
    567. 

  567.      FPSCR_N,
    568. 

  568. -    FPSCR_M
    569. 

  569. +    FPSCR_M,
    570. 

  570. +    A_IND_0
    571. 

  571.    }
    572. 

  572.  sh_arg_type;
    573. 

  573.  
    574. 

  574. @@ -214,9 +215,11 @@ sh_dsp_reg_nums;
    575. 

  575.  #define arch_sh4_base	    (1 << 5)
    576. 

  576.  #define arch_sh4a_base	    (1 << 6)
    577. 

  577.  #define arch_sh2a_base      (1 << 7)
    578. 

  578. -#define arch_sh_base_mask   MASK (0, 7)
    579. 

  579. +#define arch_shj2_base      (1 << 8)
    580. 

  580. +#define arch_sh2a_sh3_shj2_base  (1 << 9)
    581. 

  581. +#define arch_sh_base_mask   MASK (0, 9)
    582. 

  582.  
    583. 

  583. -/* Bits 8 ... 24 are currently free.  */
    584. 

  584. +/* Bits 10 ... 24 are currently free.  */
    585. 

  585.  
    586. 

  586.  /* This is an annotation on instruction types, but we
    587. 

  587.     abuse the arch field in instructions to denote it.  */
    588. 

  588. @@ -254,6 +257,8 @@ sh_dsp_reg_nums;
    589. 

  589.  #define arch_sh2a_nofpu_or_sh3_nommu       (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
    590. 

  590.  #define arch_sh2a_or_sh3e                  (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
    591. 

  591.  #define arch_sh2a_or_sh4                   (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
    592. 

  592. +#define arch_shj2                          (arch_shj2_base    |arch_sh_no_mmu |arch_sh_no_co)
    593. 

  593. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu       (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
    594. 

  594.  
    595. 

  595.  #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
    596. 

  596.  #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
    597. 

  597. @@ -319,7 +324,8 @@ SH4AL-dsp                                          SH4A
    598. 

  598.  #define arch_sh2_up                            (arch_sh2 \
    599. 

  599.  		| arch_sh2e_up \
    600. 

  600.  		| arch_sh2a_nofpu_or_sh3_nommu_up \
    601. 

  601. -		| arch_sh_dsp_up)
    602. 

  602. +		| arch_sh_dsp_up \
    603. 

  603. +		| arch_shj2_up)
    604. 

  604.  #define arch_sh2a_nofpu_or_sh3_nommu_up        (arch_sh2a_nofpu_or_sh3_nommu \
    605. 

  605.  		| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
    606. 

  606.  		| arch_sh2a_or_sh3e_up \
    607. 

  607. @@ -345,6 +351,12 @@ SH4AL-dsp                                          SH4A
    608. 

  608.  #define arch_sh4a_nofpu_up                     (arch_sh4a_nofpu \
    609. 

  609.  		| arch_sh4a_up \
    610. 

  610.  		| arch_sh4al_dsp_up)
    611. 

  611. +#define arch_shj2_up		       	       ( arch_shj2)
    612. 

  612. +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
    613. 

  613. +		| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
    614. 

  614. +		| arch_sh2a_or_sh3e_up \
    615. 

  615. +		| arch_sh3_nommu_up \
    616. 

  616. +		| arch_shj2_up)
    617. 

  617.  
    618. 

  618.  /* Right branches.  */
    619. 

  619.  #define arch_sh2e_up                           (arch_sh2e \
    620. 

  620. @@ -713,9 +725,9 @@ const sh_opcode_info sh_table[] =
    621. 

  621.  
    622. 

  622.  /* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
    623. 

  623.  
    624. 

  624. -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
    625. 

  625. +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
    626. 

  626.  
    627. 

  627. -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
    628. 

  628. +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
    629. 

  629.  
    630. 

  630.  /* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
    631. 

  631.  
    632. 

  632. @@ -1193,7 +1205,7 @@ const sh_opcode_info sh_table[] =
    633. 

  633.  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
    634. 

  634.  /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
    635. 

  635.  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
    636. 

  636. -
    637. 

  637. +  /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */       {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
    638. 

  638.  { 0, {0}, {0}, 0 } 
    639. 

  639.  };
    640. 

  640.  
    641.