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0003-or1k-32bithost-2.diff

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
  1. From: Stafford Horne <[email protected]>
    2. 

  2. To: GNU Binutils <[email protected]>
    3. 

  3. Cc: Openrisc <[email protected]>,	[email protected],	Stafford Horne <[email protected]>
    4. 

  4. Subject: [PATCH 2/2] or1k: Regnerate opcode files after removing 64-bit support
    5. 

  5. Date: Wed, 11 Dec 2019 06:49:06 +0900
    6. 

  6. 

  7. opcodes/ChangeLog:
    8. 

  8. 

  9. yyyy-mm-dd  Stafford Horne  <[email protected]>
    10. 

  10. 

  11. 	* or1k-asm.c: Regenerate.
    12. 

  12. 	* or1k-desc.c: Regenerate.
    13. 

  13. 	* or1k-desc.h: Regenerate.
    14. 

  14. 	* or1k-dis.c: Regenerate.
    15. 

  15. 	* or1k-ibld.c: Regenerate.
    16. 

  16. 	* or1k-opc.c: Regenerate.
    17. 

  17. 	* or1k-opc.h: Regenerate.
    18. 

  18. 	* or1k-opinst.c: Regenerate.
    19. 

  19. ---
    20. 

  20.  opcodes/or1k-asm.c    |    9 -
    21. 

  21.  opcodes/or1k-desc.c   | 1811 +++++++++++++++++++----------------------
    22. 

  22.  opcodes/or1k-desc.h   |  332 ++++----
    23. 

  23.  opcodes/or1k-dis.c    |    9 -
    24. 

  24.  opcodes/or1k-ibld.c   |   60 +-
    25. 

  25.  opcodes/or1k-opc.c    |  152 ----
    26. 

  26.  opcodes/or1k-opc.h    |   28 +-
    27. 

  27.  opcodes/or1k-opinst.c |  428 +++++-----
    28. 

  28.  8 files changed, 1182 insertions(+), 1647 deletions(-)
    29. 

  29. 

  30. diff --git a/opcodes/or1k-asm.c b/opcodes/or1k-asm.c
    31. 

  31. index 55668afee5..11f25868bb 100644
    32. 

  32. --- a/opcodes/or1k-asm.c
    33. 

  33. +++ b/opcodes/or1k-asm.c
    34. 

  34. @@ -519,9 +519,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
    35. 

  35.      case OR1K_OPERAND_RAD32F :
    36. 

  36.        errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RAD32F, (unsigned long *) (& fields->f_rad32));
    37. 

  37.        break;
    38. 

  38. -    case OR1K_OPERAND_RADF :
    39. 

  39. -      errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r2);
    40. 

  40. -      break;
    41. 

  41.      case OR1K_OPERAND_RADI :
    42. 

  42.        errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RADI, (unsigned long *) (& fields->f_rad32));
    43. 

  43.        break;
    44. 

  44. @@ -534,9 +531,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
    45. 

  45.      case OR1K_OPERAND_RBD32F :
    46. 

  46.        errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBD32F, (unsigned long *) (& fields->f_rbd32));
    47. 

  47.        break;
    48. 

  48. -    case OR1K_OPERAND_RBDF :
    49. 

  49. -      errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r3);
    50. 

  50. -      break;
    51. 

  51.      case OR1K_OPERAND_RBDI :
    52. 

  52.        errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBDI, (unsigned long *) (& fields->f_rbd32));
    53. 

  53.        break;
    54. 

  54. @@ -549,9 +543,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
    55. 

  55.      case OR1K_OPERAND_RDD32F :
    56. 

  56.        errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDD32F, (unsigned long *) (& fields->f_rdd32));
    57. 

  57.        break;
    58. 

  58. -    case OR1K_OPERAND_RDDF :
    59. 

  59. -      errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1);
    60. 

  60. -      break;
    61. 

  61.      case OR1K_OPERAND_RDDI :
    62. 

  62.        errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDDI, (unsigned long *) (& fields->f_rdd32));
    63. 

  63.        break;
    64. 

  64. diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c
    65. 

  65. index 3357849a27..10158cd076 100644
    66. 

  66. --- a/opcodes/or1k-desc.c
    67. 

  67. +++ b/opcodes/or1k-desc.c
    68. 

  68. @@ -49,8 +49,6 @@ static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
    69. 

  69.    { "base", MACH_BASE },
    70. 

  70.    { "or32", MACH_OR32 },
    71. 

  71.    { "or32nd", MACH_OR32ND },
    72. 

  72. -  { "or64", MACH_OR64 },
    73. 

  73. -  { "or64nd", MACH_OR64ND },
    74. 

  74.    { "max", MACH_MAX },
    75. 

  75.    { 0, 0 }
    76. 

  76.  };
    77. 

  77. @@ -129,8 +127,6 @@ static const CGEN_ISA or1k_cgen_isa_table[] = {
    78. 

  78.  static const CGEN_MACH or1k_cgen_mach_table[] = {
    79. 

  79.    { "or32", "or1k", MACH_OR32, 0 },
    80. 

  80.    { "or32nd", "or1knd", MACH_OR32ND, 0 },
    81. 

  81. -  { "or64", "or1k64", MACH_OR64, 0 },
    82. 

  82. -  { "or64nd", "or1k64nd", MACH_OR64ND, 0 },
    83. 

  83.    { 0, 0, 0, 0 }
    84. 

  84.  };
    85. 

  85.  
    86. 

  86. @@ -226,52 +222,6 @@ CGEN_KEYWORD or1k_cgen_opval_h_fsr =
    87. 

  87.    0, 0, 0, 0, ""
    88. 

  88.  };
    89. 

  89.  
    90. 

  90. -static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
    91. 

  91. -{
    92. 

  92. -  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
    93. 

  93. -  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
    94. 

  94. -  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
    95. 

  95. -  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
    96. 

  96. -  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
    97. 

  97. -  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
    98. 

  98. -  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
    99. 

  99. -  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
    100. 

  100. -  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
    101. 

  101. -  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
    102. 

  102. -  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
    103. 

  103. -  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
    104. 

  104. -  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
    105. 

  105. -  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
    106. 

  106. -  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
    107. 

  107. -  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
    108. 

  108. -  { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
    109. 

  109. -  { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
    110. 

  110. -  { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
    111. 

  111. -  { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
    112. 

  112. -  { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
    113. 

  113. -  { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
    114. 

  114. -  { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
    115. 

  115. -  { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
    116. 

  116. -  { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
    117. 

  117. -  { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
    118. 

  118. -  { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
    119. 

  119. -  { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
    120. 

  120. -  { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
    121. 

  121. -  { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
    122. 

  122. -  { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
    123. 

  123. -  { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
    124. 

  124. -  { "lr", 9, {0, {{{0, 0}}}}, 0, 0 },
    125. 

  125. -  { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
    126. 

  126. -  { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
    127. 

  127. -};
    128. 

  128. -
    129. 

  129. -CGEN_KEYWORD or1k_cgen_opval_h_fdr =
    130. 

  130. -{
    131. 

  131. -  & or1k_cgen_opval_h_fdr_entries[0],
    132. 

  132. -  35,
    133. 

  133. -  0, 0, 0, 0, ""
    134. 

  134. -};
    135. 

  135. -
    136. 

  136.  
    137. 

  137.  /* The hardware table.  */
    138. 

  138.  
    139. 

  139. @@ -284,642 +234,641 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
    140. 

  140.    { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    141. 

  141.    { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    142. 

  142.    { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    143. 

  143. -  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    144. 

  144. -  { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    145. 

  145. -  { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    146. 

  146. -  { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    147. 

  147. -  { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    148. 

  148. +  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    149. 

  149. +  { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    150. 

  150. +  { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    151. 

  151. +  { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    152. 

  152.    { "h-fd32r", HW_H_FD32R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    153. 

  153.    { "h-i64r", HW_H_I64R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    154. 

  154. -  { "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    155. 

  155. -  { "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    156. 

  156. -  { "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    157. 

  157. -  { "h-sys-dmmucfgr", HW_H_SYS_DMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    158. 

  158. -  { "h-sys-immucfgr", HW_H_SYS_IMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    159. 

  159. -  { "h-sys-dccfgr", HW_H_SYS_DCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    160. 

  160. -  { "h-sys-iccfgr", HW_H_SYS_ICCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    161. 

  161. -  { "h-sys-dcfgr", HW_H_SYS_DCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    162. 

  162. -  { "h-sys-pccfgr", HW_H_SYS_PCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    163. 

  163. -  { "h-sys-npc", HW_H_SYS_NPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    164. 

  164. -  { "h-sys-sr", HW_H_SYS_SR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    165. 

  165. -  { "h-sys-ppc", HW_H_SYS_PPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    166. 

  166. -  { "h-sys-fpcsr", HW_H_SYS_FPCSR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    167. 

  167. -  { "h-sys-epcr0", HW_H_SYS_EPCR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    168. 

  168. -  { "h-sys-epcr1", HW_H_SYS_EPCR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    169. 

  169. -  { "h-sys-epcr2", HW_H_SYS_EPCR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    170. 

  170. -  { "h-sys-epcr3", HW_H_SYS_EPCR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    171. 

  171. -  { "h-sys-epcr4", HW_H_SYS_EPCR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    172. 

  172. -  { "h-sys-epcr5", HW_H_SYS_EPCR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    173. 

  173. -  { "h-sys-epcr6", HW_H_SYS_EPCR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    174. 

  174. -  { "h-sys-epcr7", HW_H_SYS_EPCR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    175. 

  175. -  { "h-sys-epcr8", HW_H_SYS_EPCR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    176. 

  176. -  { "h-sys-epcr9", HW_H_SYS_EPCR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    177. 

  177. -  { "h-sys-epcr10", HW_H_SYS_EPCR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    178. 

  178. -  { "h-sys-epcr11", HW_H_SYS_EPCR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    179. 

  179. -  { "h-sys-epcr12", HW_H_SYS_EPCR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    180. 

  180. -  { "h-sys-epcr13", HW_H_SYS_EPCR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    181. 

  181. -  { "h-sys-epcr14", HW_H_SYS_EPCR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    182. 

  182. -  { "h-sys-epcr15", HW_H_SYS_EPCR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    183. 

  183. -  { "h-sys-eear0", HW_H_SYS_EEAR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    184. 

  184. -  { "h-sys-eear1", HW_H_SYS_EEAR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    185. 

  185. -  { "h-sys-eear2", HW_H_SYS_EEAR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    186. 

  186. -  { "h-sys-eear3", HW_H_SYS_EEAR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    187. 

  187. -  { "h-sys-eear4", HW_H_SYS_EEAR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    188. 

  188. -  { "h-sys-eear5", HW_H_SYS_EEAR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    189. 

  189. -  { "h-sys-eear6", HW_H_SYS_EEAR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    190. 

  190. -  { "h-sys-eear7", HW_H_SYS_EEAR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    191. 

  191. -  { "h-sys-eear8", HW_H_SYS_EEAR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    192. 

  192. -  { "h-sys-eear9", HW_H_SYS_EEAR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    193. 

  193. -  { "h-sys-eear10", HW_H_SYS_EEAR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    194. 

  194. -  { "h-sys-eear11", HW_H_SYS_EEAR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    195. 

  195. -  { "h-sys-eear12", HW_H_SYS_EEAR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    196. 

  196. -  { "h-sys-eear13", HW_H_SYS_EEAR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    197. 

  197. -  { "h-sys-eear14", HW_H_SYS_EEAR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    198. 

  198. -  { "h-sys-eear15", HW_H_SYS_EEAR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    199. 

  199. -  { "h-sys-esr0", HW_H_SYS_ESR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    200. 

  200. -  { "h-sys-esr1", HW_H_SYS_ESR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    201. 

  201. -  { "h-sys-esr2", HW_H_SYS_ESR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    202. 

  202. -  { "h-sys-esr3", HW_H_SYS_ESR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    203. 

  203. -  { "h-sys-esr4", HW_H_SYS_ESR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    204. 

  204. -  { "h-sys-esr5", HW_H_SYS_ESR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    205. 

  205. -  { "h-sys-esr6", HW_H_SYS_ESR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    206. 

  206. -  { "h-sys-esr7", HW_H_SYS_ESR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    207. 

  207. -  { "h-sys-esr8", HW_H_SYS_ESR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    208. 

  208. -  { "h-sys-esr9", HW_H_SYS_ESR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    209. 

  209. -  { "h-sys-esr10", HW_H_SYS_ESR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    210. 

  210. -  { "h-sys-esr11", HW_H_SYS_ESR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    211. 

  211. -  { "h-sys-esr12", HW_H_SYS_ESR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    212. 

  212. -  { "h-sys-esr13", HW_H_SYS_ESR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    213. 

  213. -  { "h-sys-esr14", HW_H_SYS_ESR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    214. 

  214. -  { "h-sys-esr15", HW_H_SYS_ESR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    215. 

  215. -  { "h-sys-gpr0", HW_H_SYS_GPR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    216. 

  216. -  { "h-sys-gpr1", HW_H_SYS_GPR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    217. 

  217. -  { "h-sys-gpr2", HW_H_SYS_GPR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    218. 

  218. -  { "h-sys-gpr3", HW_H_SYS_GPR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    219. 

  219. -  { "h-sys-gpr4", HW_H_SYS_GPR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    220. 

  220. -  { "h-sys-gpr5", HW_H_SYS_GPR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    221. 

  221. -  { "h-sys-gpr6", HW_H_SYS_GPR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    222. 

  222. -  { "h-sys-gpr7", HW_H_SYS_GPR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    223. 

  223. -  { "h-sys-gpr8", HW_H_SYS_GPR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    224. 

  224. -  { "h-sys-gpr9", HW_H_SYS_GPR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    225. 

  225. -  { "h-sys-gpr10", HW_H_SYS_GPR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    226. 

  226. -  { "h-sys-gpr11", HW_H_SYS_GPR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    227. 

  227. -  { "h-sys-gpr12", HW_H_SYS_GPR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    228. 

  228. -  { "h-sys-gpr13", HW_H_SYS_GPR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    229. 

  229. -  { "h-sys-gpr14", HW_H_SYS_GPR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    230. 

  230. -  { "h-sys-gpr15", HW_H_SYS_GPR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    231. 

  231. -  { "h-sys-gpr16", HW_H_SYS_GPR16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    232. 

  232. -  { "h-sys-gpr17", HW_H_SYS_GPR17, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    233. 

  233. -  { "h-sys-gpr18", HW_H_SYS_GPR18, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    234. 

  234. -  { "h-sys-gpr19", HW_H_SYS_GPR19, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    235. 

  235. -  { "h-sys-gpr20", HW_H_SYS_GPR20, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    236. 

  236. -  { "h-sys-gpr21", HW_H_SYS_GPR21, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    237. 

  237. -  { "h-sys-gpr22", HW_H_SYS_GPR22, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    238. 

  238. -  { "h-sys-gpr23", HW_H_SYS_GPR23, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    239. 

  239. -  { "h-sys-gpr24", HW_H_SYS_GPR24, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    240. 

  240. -  { "h-sys-gpr25", HW_H_SYS_GPR25, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    241. 

  241. -  { "h-sys-gpr26", HW_H_SYS_GPR26, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    242. 

  242. -  { "h-sys-gpr27", HW_H_SYS_GPR27, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    243. 

  243. -  { "h-sys-gpr28", HW_H_SYS_GPR28, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    244. 

  244. -  { "h-sys-gpr29", HW_H_SYS_GPR29, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    245. 

  245. -  { "h-sys-gpr30", HW_H_SYS_GPR30, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    246. 

  246. -  { "h-sys-gpr31", HW_H_SYS_GPR31, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    247. 

  247. -  { "h-sys-gpr32", HW_H_SYS_GPR32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    248. 

  248. -  { "h-sys-gpr33", HW_H_SYS_GPR33, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    249. 

  249. -  { "h-sys-gpr34", HW_H_SYS_GPR34, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    250. 

  250. -  { "h-sys-gpr35", HW_H_SYS_GPR35, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    251. 

  251. -  { "h-sys-gpr36", HW_H_SYS_GPR36, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    252. 

  252. -  { "h-sys-gpr37", HW_H_SYS_GPR37, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    253. 

  253. -  { "h-sys-gpr38", HW_H_SYS_GPR38, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    254. 

  254. -  { "h-sys-gpr39", HW_H_SYS_GPR39, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    255. 

  255. -  { "h-sys-gpr40", HW_H_SYS_GPR40, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    256. 

  256. -  { "h-sys-gpr41", HW_H_SYS_GPR41, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    257. 

  257. -  { "h-sys-gpr42", HW_H_SYS_GPR42, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    258. 

  258. -  { "h-sys-gpr43", HW_H_SYS_GPR43, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    259. 

  259. -  { "h-sys-gpr44", HW_H_SYS_GPR44, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    260. 

  260. -  { "h-sys-gpr45", HW_H_SYS_GPR45, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    261. 

  261. -  { "h-sys-gpr46", HW_H_SYS_GPR46, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    262. 

  262. -  { "h-sys-gpr47", HW_H_SYS_GPR47, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    263. 

  263. -  { "h-sys-gpr48", HW_H_SYS_GPR48, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    264. 

  264. -  { "h-sys-gpr49", HW_H_SYS_GPR49, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    265. 

  265. -  { "h-sys-gpr50", HW_H_SYS_GPR50, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    266. 

  266. -  { "h-sys-gpr51", HW_H_SYS_GPR51, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    267. 

  267. -  { "h-sys-gpr52", HW_H_SYS_GPR52, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    268. 

  268. -  { "h-sys-gpr53", HW_H_SYS_GPR53, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    269. 

  269. -  { "h-sys-gpr54", HW_H_SYS_GPR54, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    270. 

  270. -  { "h-sys-gpr55", HW_H_SYS_GPR55, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    271. 

  271. -  { "h-sys-gpr56", HW_H_SYS_GPR56, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    272. 

  272. -  { "h-sys-gpr57", HW_H_SYS_GPR57, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    273. 

  273. -  { "h-sys-gpr58", HW_H_SYS_GPR58, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    274. 

  274. -  { "h-sys-gpr59", HW_H_SYS_GPR59, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    275. 

  275. -  { "h-sys-gpr60", HW_H_SYS_GPR60, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    276. 

  276. -  { "h-sys-gpr61", HW_H_SYS_GPR61, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    277. 

  277. -  { "h-sys-gpr62", HW_H_SYS_GPR62, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    278. 

  278. -  { "h-sys-gpr63", HW_H_SYS_GPR63, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    279. 

  279. -  { "h-sys-gpr64", HW_H_SYS_GPR64, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    280. 

  280. -  { "h-sys-gpr65", HW_H_SYS_GPR65, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    281. 

  281. -  { "h-sys-gpr66", HW_H_SYS_GPR66, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    282. 

  282. -  { "h-sys-gpr67", HW_H_SYS_GPR67, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    283. 

  283. -  { "h-sys-gpr68", HW_H_SYS_GPR68, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    284. 

  284. -  { "h-sys-gpr69", HW_H_SYS_GPR69, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    285. 

  285. -  { "h-sys-gpr70", HW_H_SYS_GPR70, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    286. 

  286. -  { "h-sys-gpr71", HW_H_SYS_GPR71, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    287. 

  287. -  { "h-sys-gpr72", HW_H_SYS_GPR72, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    288. 

  288. -  { "h-sys-gpr73", HW_H_SYS_GPR73, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    289. 

  289. -  { "h-sys-gpr74", HW_H_SYS_GPR74, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    290. 

  290. -  { "h-sys-gpr75", HW_H_SYS_GPR75, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    291. 

  291. -  { "h-sys-gpr76", HW_H_SYS_GPR76, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    292. 

  292. -  { "h-sys-gpr77", HW_H_SYS_GPR77, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    293. 

  293. -  { "h-sys-gpr78", HW_H_SYS_GPR78, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    294. 

  294. -  { "h-sys-gpr79", HW_H_SYS_GPR79, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    295. 

  295. -  { "h-sys-gpr80", HW_H_SYS_GPR80, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    296. 

  296. -  { "h-sys-gpr81", HW_H_SYS_GPR81, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    297. 

  297. -  { "h-sys-gpr82", HW_H_SYS_GPR82, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    298. 

  298. -  { "h-sys-gpr83", HW_H_SYS_GPR83, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    299. 

  299. -  { "h-sys-gpr84", HW_H_SYS_GPR84, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    300. 

  300. -  { "h-sys-gpr85", HW_H_SYS_GPR85, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    301. 

  301. -  { "h-sys-gpr86", HW_H_SYS_GPR86, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    302. 

  302. -  { "h-sys-gpr87", HW_H_SYS_GPR87, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    303. 

  303. -  { "h-sys-gpr88", HW_H_SYS_GPR88, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    304. 

  304. -  { "h-sys-gpr89", HW_H_SYS_GPR89, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    305. 

  305. -  { "h-sys-gpr90", HW_H_SYS_GPR90, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    306. 

  306. -  { "h-sys-gpr91", HW_H_SYS_GPR91, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    307. 

  307. -  { "h-sys-gpr92", HW_H_SYS_GPR92, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    308. 

  308. -  { "h-sys-gpr93", HW_H_SYS_GPR93, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    309. 

  309. -  { "h-sys-gpr94", HW_H_SYS_GPR94, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    310. 

  310. -  { "h-sys-gpr95", HW_H_SYS_GPR95, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    311. 

  311. -  { "h-sys-gpr96", HW_H_SYS_GPR96, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    312. 

  312. -  { "h-sys-gpr97", HW_H_SYS_GPR97, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    313. 

  313. -  { "h-sys-gpr98", HW_H_SYS_GPR98, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    314. 

  314. -  { "h-sys-gpr99", HW_H_SYS_GPR99, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    315. 

  315. -  { "h-sys-gpr100", HW_H_SYS_GPR100, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    316. 

  316. -  { "h-sys-gpr101", HW_H_SYS_GPR101, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    317. 

  317. -  { "h-sys-gpr102", HW_H_SYS_GPR102, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    318. 

  318. -  { "h-sys-gpr103", HW_H_SYS_GPR103, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    319. 

  319. -  { "h-sys-gpr104", HW_H_SYS_GPR104, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    320. 

  320. -  { "h-sys-gpr105", HW_H_SYS_GPR105, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    321. 

  321. -  { "h-sys-gpr106", HW_H_SYS_GPR106, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    322. 

  322. -  { "h-sys-gpr107", HW_H_SYS_GPR107, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    323. 

  323. -  { "h-sys-gpr108", HW_H_SYS_GPR108, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    324. 

  324. -  { "h-sys-gpr109", HW_H_SYS_GPR109, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    325. 

  325. -  { "h-sys-gpr110", HW_H_SYS_GPR110, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    326. 

  326. -  { "h-sys-gpr111", HW_H_SYS_GPR111, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    327. 

  327. -  { "h-sys-gpr112", HW_H_SYS_GPR112, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    328. 

  328. -  { "h-sys-gpr113", HW_H_SYS_GPR113, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    329. 

  329. -  { "h-sys-gpr114", HW_H_SYS_GPR114, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    330. 

  330. -  { "h-sys-gpr115", HW_H_SYS_GPR115, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    331. 

  331. -  { "h-sys-gpr116", HW_H_SYS_GPR116, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    332. 

  332. -  { "h-sys-gpr117", HW_H_SYS_GPR117, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    333. 

  333. -  { "h-sys-gpr118", HW_H_SYS_GPR118, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    334. 

  334. -  { "h-sys-gpr119", HW_H_SYS_GPR119, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    335. 

  335. -  { "h-sys-gpr120", HW_H_SYS_GPR120, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    336. 

  336. -  { "h-sys-gpr121", HW_H_SYS_GPR121, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    337. 

  337. -  { "h-sys-gpr122", HW_H_SYS_GPR122, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    338. 

  338. -  { "h-sys-gpr123", HW_H_SYS_GPR123, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    339. 

  339. -  { "h-sys-gpr124", HW_H_SYS_GPR124, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    340. 

  340. -  { "h-sys-gpr125", HW_H_SYS_GPR125, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    341. 

  341. -  { "h-sys-gpr126", HW_H_SYS_GPR126, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    342. 

  342. -  { "h-sys-gpr127", HW_H_SYS_GPR127, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    343. 

  343. -  { "h-sys-gpr128", HW_H_SYS_GPR128, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    344. 

  344. -  { "h-sys-gpr129", HW_H_SYS_GPR129, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    345. 

  345. -  { "h-sys-gpr130", HW_H_SYS_GPR130, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    346. 

  346. -  { "h-sys-gpr131", HW_H_SYS_GPR131, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    347. 

  347. -  { "h-sys-gpr132", HW_H_SYS_GPR132, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    348. 

  348. -  { "h-sys-gpr133", HW_H_SYS_GPR133, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    349. 

  349. -  { "h-sys-gpr134", HW_H_SYS_GPR134, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    350. 

  350. -  { "h-sys-gpr135", HW_H_SYS_GPR135, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    351. 

  351. -  { "h-sys-gpr136", HW_H_SYS_GPR136, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    352. 

  352. -  { "h-sys-gpr137", HW_H_SYS_GPR137, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    353. 

  353. -  { "h-sys-gpr138", HW_H_SYS_GPR138, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    354. 

  354. -  { "h-sys-gpr139", HW_H_SYS_GPR139, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    355. 

  355. -  { "h-sys-gpr140", HW_H_SYS_GPR140, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    356. 

  356. -  { "h-sys-gpr141", HW_H_SYS_GPR141, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    357. 

  357. -  { "h-sys-gpr142", HW_H_SYS_GPR142, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    358. 

  358. -  { "h-sys-gpr143", HW_H_SYS_GPR143, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    359. 

  359. -  { "h-sys-gpr144", HW_H_SYS_GPR144, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    360. 

  360. -  { "h-sys-gpr145", HW_H_SYS_GPR145, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    361. 

  361. -  { "h-sys-gpr146", HW_H_SYS_GPR146, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    362. 

  362. -  { "h-sys-gpr147", HW_H_SYS_GPR147, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    363. 

  363. -  { "h-sys-gpr148", HW_H_SYS_GPR148, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    364. 

  364. -  { "h-sys-gpr149", HW_H_SYS_GPR149, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    365. 

  365. -  { "h-sys-gpr150", HW_H_SYS_GPR150, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    366. 

  366. -  { "h-sys-gpr151", HW_H_SYS_GPR151, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    367. 

  367. -  { "h-sys-gpr152", HW_H_SYS_GPR152, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    368. 

  368. -  { "h-sys-gpr153", HW_H_SYS_GPR153, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    369. 

  369. -  { "h-sys-gpr154", HW_H_SYS_GPR154, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    370. 

  370. -  { "h-sys-gpr155", HW_H_SYS_GPR155, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    371. 

  371. -  { "h-sys-gpr156", HW_H_SYS_GPR156, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    372. 

  372. -  { "h-sys-gpr157", HW_H_SYS_GPR157, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    373. 

  373. -  { "h-sys-gpr158", HW_H_SYS_GPR158, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    374. 

  374. -  { "h-sys-gpr159", HW_H_SYS_GPR159, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    375. 

  375. -  { "h-sys-gpr160", HW_H_SYS_GPR160, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    376. 

  376. -  { "h-sys-gpr161", HW_H_SYS_GPR161, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    377. 

  377. -  { "h-sys-gpr162", HW_H_SYS_GPR162, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    378. 

  378. -  { "h-sys-gpr163", HW_H_SYS_GPR163, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    379. 

  379. -  { "h-sys-gpr164", HW_H_SYS_GPR164, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    380. 

  380. -  { "h-sys-gpr165", HW_H_SYS_GPR165, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    381. 

  381. -  { "h-sys-gpr166", HW_H_SYS_GPR166, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    382. 

  382. -  { "h-sys-gpr167", HW_H_SYS_GPR167, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    383. 

  383. -  { "h-sys-gpr168", HW_H_SYS_GPR168, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    384. 

  384. -  { "h-sys-gpr169", HW_H_SYS_GPR169, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    385. 

  385. -  { "h-sys-gpr170", HW_H_SYS_GPR170, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    386. 

  386. -  { "h-sys-gpr171", HW_H_SYS_GPR171, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    387. 

  387. -  { "h-sys-gpr172", HW_H_SYS_GPR172, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    388. 

  388. -  { "h-sys-gpr173", HW_H_SYS_GPR173, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    389. 

  389. -  { "h-sys-gpr174", HW_H_SYS_GPR174, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    390. 

  390. -  { "h-sys-gpr175", HW_H_SYS_GPR175, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    391. 

  391. -  { "h-sys-gpr176", HW_H_SYS_GPR176, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    392. 

  392. -  { "h-sys-gpr177", HW_H_SYS_GPR177, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    393. 

  393. -  { "h-sys-gpr178", HW_H_SYS_GPR178, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    394. 

  394. -  { "h-sys-gpr179", HW_H_SYS_GPR179, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    395. 

  395. -  { "h-sys-gpr180", HW_H_SYS_GPR180, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    396. 

  396. -  { "h-sys-gpr181", HW_H_SYS_GPR181, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    397. 

  397. -  { "h-sys-gpr182", HW_H_SYS_GPR182, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    398. 

  398. -  { "h-sys-gpr183", HW_H_SYS_GPR183, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    399. 

  399. -  { "h-sys-gpr184", HW_H_SYS_GPR184, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    400. 

  400. -  { "h-sys-gpr185", HW_H_SYS_GPR185, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    401. 

  401. -  { "h-sys-gpr186", HW_H_SYS_GPR186, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    402. 

  402. -  { "h-sys-gpr187", HW_H_SYS_GPR187, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    403. 

  403. -  { "h-sys-gpr188", HW_H_SYS_GPR188, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    404. 

  404. -  { "h-sys-gpr189", HW_H_SYS_GPR189, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    405. 

  405. -  { "h-sys-gpr190", HW_H_SYS_GPR190, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    406. 

  406. -  { "h-sys-gpr191", HW_H_SYS_GPR191, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    407. 

  407. -  { "h-sys-gpr192", HW_H_SYS_GPR192, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    408. 

  408. -  { "h-sys-gpr193", HW_H_SYS_GPR193, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    409. 

  409. -  { "h-sys-gpr194", HW_H_SYS_GPR194, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    410. 

  410. -  { "h-sys-gpr195", HW_H_SYS_GPR195, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    411. 

  411. -  { "h-sys-gpr196", HW_H_SYS_GPR196, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    412. 

  412. -  { "h-sys-gpr197", HW_H_SYS_GPR197, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    413. 

  413. -  { "h-sys-gpr198", HW_H_SYS_GPR198, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    414. 

  414. -  { "h-sys-gpr199", HW_H_SYS_GPR199, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    415. 

  415. -  { "h-sys-gpr200", HW_H_SYS_GPR200, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    416. 

  416. -  { "h-sys-gpr201", HW_H_SYS_GPR201, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    417. 

  417. -  { "h-sys-gpr202", HW_H_SYS_GPR202, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    418. 

  418. -  { "h-sys-gpr203", HW_H_SYS_GPR203, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    419. 

  419. -  { "h-sys-gpr204", HW_H_SYS_GPR204, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    420. 

  420. -  { "h-sys-gpr205", HW_H_SYS_GPR205, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    421. 

  421. -  { "h-sys-gpr206", HW_H_SYS_GPR206, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    422. 

  422. -  { "h-sys-gpr207", HW_H_SYS_GPR207, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    423. 

  423. -  { "h-sys-gpr208", HW_H_SYS_GPR208, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    424. 

  424. -  { "h-sys-gpr209", HW_H_SYS_GPR209, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    425. 

  425. -  { "h-sys-gpr210", HW_H_SYS_GPR210, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    426. 

  426. -  { "h-sys-gpr211", HW_H_SYS_GPR211, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    427. 

  427. -  { "h-sys-gpr212", HW_H_SYS_GPR212, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    428. 

  428. -  { "h-sys-gpr213", HW_H_SYS_GPR213, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    429. 

  429. -  { "h-sys-gpr214", HW_H_SYS_GPR214, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    430. 

  430. -  { "h-sys-gpr215", HW_H_SYS_GPR215, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    431. 

  431. -  { "h-sys-gpr216", HW_H_SYS_GPR216, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    432. 

  432. -  { "h-sys-gpr217", HW_H_SYS_GPR217, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    433. 

  433. -  { "h-sys-gpr218", HW_H_SYS_GPR218, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    434. 

  434. -  { "h-sys-gpr219", HW_H_SYS_GPR219, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    435. 

  435. -  { "h-sys-gpr220", HW_H_SYS_GPR220, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    436. 

  436. -  { "h-sys-gpr221", HW_H_SYS_GPR221, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    437. 

  437. -  { "h-sys-gpr222", HW_H_SYS_GPR222, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    438. 

  438. -  { "h-sys-gpr223", HW_H_SYS_GPR223, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    439. 

  439. -  { "h-sys-gpr224", HW_H_SYS_GPR224, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    440. 

  440. -  { "h-sys-gpr225", HW_H_SYS_GPR225, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    441. 

  441. -  { "h-sys-gpr226", HW_H_SYS_GPR226, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    442. 

  442. -  { "h-sys-gpr227", HW_H_SYS_GPR227, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    443. 

  443. -  { "h-sys-gpr228", HW_H_SYS_GPR228, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    444. 

  444. -  { "h-sys-gpr229", HW_H_SYS_GPR229, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    445. 

  445. -  { "h-sys-gpr230", HW_H_SYS_GPR230, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    446. 

  446. -  { "h-sys-gpr231", HW_H_SYS_GPR231, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    447. 

  447. -  { "h-sys-gpr232", HW_H_SYS_GPR232, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    448. 

  448. -  { "h-sys-gpr233", HW_H_SYS_GPR233, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    449. 

  449. -  { "h-sys-gpr234", HW_H_SYS_GPR234, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    450. 

  450. -  { "h-sys-gpr235", HW_H_SYS_GPR235, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    451. 

  451. -  { "h-sys-gpr236", HW_H_SYS_GPR236, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    452. 

  452. -  { "h-sys-gpr237", HW_H_SYS_GPR237, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    453. 

  453. -  { "h-sys-gpr238", HW_H_SYS_GPR238, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    454. 

  454. -  { "h-sys-gpr239", HW_H_SYS_GPR239, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    455. 

  455. -  { "h-sys-gpr240", HW_H_SYS_GPR240, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    456. 

  456. -  { "h-sys-gpr241", HW_H_SYS_GPR241, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    457. 

  457. -  { "h-sys-gpr242", HW_H_SYS_GPR242, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    458. 

  458. -  { "h-sys-gpr243", HW_H_SYS_GPR243, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    459. 

  459. -  { "h-sys-gpr244", HW_H_SYS_GPR244, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    460. 

  460. -  { "h-sys-gpr245", HW_H_SYS_GPR245, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    461. 

  461. -  { "h-sys-gpr246", HW_H_SYS_GPR246, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    462. 

  462. -  { "h-sys-gpr247", HW_H_SYS_GPR247, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    463. 

  463. -  { "h-sys-gpr248", HW_H_SYS_GPR248, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    464. 

  464. -  { "h-sys-gpr249", HW_H_SYS_GPR249, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    465. 

  465. -  { "h-sys-gpr250", HW_H_SYS_GPR250, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    466. 

  466. -  { "h-sys-gpr251", HW_H_SYS_GPR251, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    467. 

  467. -  { "h-sys-gpr252", HW_H_SYS_GPR252, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    468. 

  468. -  { "h-sys-gpr253", HW_H_SYS_GPR253, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    469. 

  469. -  { "h-sys-gpr254", HW_H_SYS_GPR254, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    470. 

  470. -  { "h-sys-gpr255", HW_H_SYS_GPR255, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    471. 

  471. -  { "h-sys-gpr256", HW_H_SYS_GPR256, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    472. 

  472. -  { "h-sys-gpr257", HW_H_SYS_GPR257, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    473. 

  473. -  { "h-sys-gpr258", HW_H_SYS_GPR258, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    474. 

  474. -  { "h-sys-gpr259", HW_H_SYS_GPR259, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    475. 

  475. -  { "h-sys-gpr260", HW_H_SYS_GPR260, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    476. 

  476. -  { "h-sys-gpr261", HW_H_SYS_GPR261, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    477. 

  477. -  { "h-sys-gpr262", HW_H_SYS_GPR262, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    478. 

  478. -  { "h-sys-gpr263", HW_H_SYS_GPR263, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    479. 

  479. -  { "h-sys-gpr264", HW_H_SYS_GPR264, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    480. 

  480. -  { "h-sys-gpr265", HW_H_SYS_GPR265, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    481. 

  481. -  { "h-sys-gpr266", HW_H_SYS_GPR266, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    482. 

  482. -  { "h-sys-gpr267", HW_H_SYS_GPR267, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    483. 

  483. -  { "h-sys-gpr268", HW_H_SYS_GPR268, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    484. 

  484. -  { "h-sys-gpr269", HW_H_SYS_GPR269, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    485. 

  485. -  { "h-sys-gpr270", HW_H_SYS_GPR270, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    486. 

  486. -  { "h-sys-gpr271", HW_H_SYS_GPR271, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    487. 

  487. -  { "h-sys-gpr272", HW_H_SYS_GPR272, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    488. 

  488. -  { "h-sys-gpr273", HW_H_SYS_GPR273, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    489. 

  489. -  { "h-sys-gpr274", HW_H_SYS_GPR274, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    490. 

  490. -  { "h-sys-gpr275", HW_H_SYS_GPR275, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    491. 

  491. -  { "h-sys-gpr276", HW_H_SYS_GPR276, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    492. 

  492. -  { "h-sys-gpr277", HW_H_SYS_GPR277, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    493. 

  493. -  { "h-sys-gpr278", HW_H_SYS_GPR278, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    494. 

  494. -  { "h-sys-gpr279", HW_H_SYS_GPR279, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    495. 

  495. -  { "h-sys-gpr280", HW_H_SYS_GPR280, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    496. 

  496. -  { "h-sys-gpr281", HW_H_SYS_GPR281, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    497. 

  497. -  { "h-sys-gpr282", HW_H_SYS_GPR282, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    498. 

  498. -  { "h-sys-gpr283", HW_H_SYS_GPR283, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    499. 

  499. -  { "h-sys-gpr284", HW_H_SYS_GPR284, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    500. 

  500. -  { "h-sys-gpr285", HW_H_SYS_GPR285, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    501. 

  501. -  { "h-sys-gpr286", HW_H_SYS_GPR286, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    502. 

  502. -  { "h-sys-gpr287", HW_H_SYS_GPR287, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    503. 

  503. -  { "h-sys-gpr288", HW_H_SYS_GPR288, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    504. 

  504. -  { "h-sys-gpr289", HW_H_SYS_GPR289, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    505. 

  505. -  { "h-sys-gpr290", HW_H_SYS_GPR290, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    506. 

  506. -  { "h-sys-gpr291", HW_H_SYS_GPR291, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    507. 

  507. -  { "h-sys-gpr292", HW_H_SYS_GPR292, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    508. 

  508. -  { "h-sys-gpr293", HW_H_SYS_GPR293, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    509. 

  509. -  { "h-sys-gpr294", HW_H_SYS_GPR294, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    510. 

  510. -  { "h-sys-gpr295", HW_H_SYS_GPR295, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    511. 

  511. -  { "h-sys-gpr296", HW_H_SYS_GPR296, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    512. 

  512. -  { "h-sys-gpr297", HW_H_SYS_GPR297, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    513. 

  513. -  { "h-sys-gpr298", HW_H_SYS_GPR298, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    514. 

  514. -  { "h-sys-gpr299", HW_H_SYS_GPR299, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    515. 

  515. -  { "h-sys-gpr300", HW_H_SYS_GPR300, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    516. 

  516. -  { "h-sys-gpr301", HW_H_SYS_GPR301, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    517. 

  517. -  { "h-sys-gpr302", HW_H_SYS_GPR302, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    518. 

  518. -  { "h-sys-gpr303", HW_H_SYS_GPR303, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    519. 

  519. -  { "h-sys-gpr304", HW_H_SYS_GPR304, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    520. 

  520. -  { "h-sys-gpr305", HW_H_SYS_GPR305, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    521. 

  521. -  { "h-sys-gpr306", HW_H_SYS_GPR306, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    522. 

  522. -  { "h-sys-gpr307", HW_H_SYS_GPR307, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    523. 

  523. -  { "h-sys-gpr308", HW_H_SYS_GPR308, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    524. 

  524. -  { "h-sys-gpr309", HW_H_SYS_GPR309, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    525. 

  525. -  { "h-sys-gpr310", HW_H_SYS_GPR310, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    526. 

  526. -  { "h-sys-gpr311", HW_H_SYS_GPR311, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    527. 

  527. -  { "h-sys-gpr312", HW_H_SYS_GPR312, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    528. 

  528. -  { "h-sys-gpr313", HW_H_SYS_GPR313, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    529. 

  529. -  { "h-sys-gpr314", HW_H_SYS_GPR314, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    530. 

  530. -  { "h-sys-gpr315", HW_H_SYS_GPR315, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    531. 

  531. -  { "h-sys-gpr316", HW_H_SYS_GPR316, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    532. 

  532. -  { "h-sys-gpr317", HW_H_SYS_GPR317, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    533. 

  533. -  { "h-sys-gpr318", HW_H_SYS_GPR318, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    534. 

  534. -  { "h-sys-gpr319", HW_H_SYS_GPR319, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    535. 

  535. -  { "h-sys-gpr320", HW_H_SYS_GPR320, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    536. 

  536. -  { "h-sys-gpr321", HW_H_SYS_GPR321, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    537. 

  537. -  { "h-sys-gpr322", HW_H_SYS_GPR322, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    538. 

  538. -  { "h-sys-gpr323", HW_H_SYS_GPR323, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    539. 

  539. -  { "h-sys-gpr324", HW_H_SYS_GPR324, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    540. 

  540. -  { "h-sys-gpr325", HW_H_SYS_GPR325, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    541. 

  541. -  { "h-sys-gpr326", HW_H_SYS_GPR326, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    542. 

  542. -  { "h-sys-gpr327", HW_H_SYS_GPR327, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    543. 

  543. -  { "h-sys-gpr328", HW_H_SYS_GPR328, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    544. 

  544. -  { "h-sys-gpr329", HW_H_SYS_GPR329, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    545. 

  545. -  { "h-sys-gpr330", HW_H_SYS_GPR330, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    546. 

  546. -  { "h-sys-gpr331", HW_H_SYS_GPR331, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    547. 

  547. -  { "h-sys-gpr332", HW_H_SYS_GPR332, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    548. 

  548. -  { "h-sys-gpr333", HW_H_SYS_GPR333, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    549. 

  549. -  { "h-sys-gpr334", HW_H_SYS_GPR334, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    550. 

  550. -  { "h-sys-gpr335", HW_H_SYS_GPR335, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    551. 

  551. -  { "h-sys-gpr336", HW_H_SYS_GPR336, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    552. 

  552. -  { "h-sys-gpr337", HW_H_SYS_GPR337, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    553. 

  553. -  { "h-sys-gpr338", HW_H_SYS_GPR338, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    554. 

  554. -  { "h-sys-gpr339", HW_H_SYS_GPR339, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    555. 

  555. -  { "h-sys-gpr340", HW_H_SYS_GPR340, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    556. 

  556. -  { "h-sys-gpr341", HW_H_SYS_GPR341, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    557. 

  557. -  { "h-sys-gpr342", HW_H_SYS_GPR342, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    558. 

  558. -  { "h-sys-gpr343", HW_H_SYS_GPR343, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    559. 

  559. -  { "h-sys-gpr344", HW_H_SYS_GPR344, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    560. 

  560. -  { "h-sys-gpr345", HW_H_SYS_GPR345, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    561. 

  561. -  { "h-sys-gpr346", HW_H_SYS_GPR346, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    562. 

  562. -  { "h-sys-gpr347", HW_H_SYS_GPR347, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    563. 

  563. -  { "h-sys-gpr348", HW_H_SYS_GPR348, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    564. 

  564. -  { "h-sys-gpr349", HW_H_SYS_GPR349, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    565. 

  565. -  { "h-sys-gpr350", HW_H_SYS_GPR350, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    566. 

  566. -  { "h-sys-gpr351", HW_H_SYS_GPR351, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    567. 

  567. -  { "h-sys-gpr352", HW_H_SYS_GPR352, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    568. 

  568. -  { "h-sys-gpr353", HW_H_SYS_GPR353, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    569. 

  569. -  { "h-sys-gpr354", HW_H_SYS_GPR354, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    570. 

  570. -  { "h-sys-gpr355", HW_H_SYS_GPR355, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    571. 

  571. -  { "h-sys-gpr356", HW_H_SYS_GPR356, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    572. 

  572. -  { "h-sys-gpr357", HW_H_SYS_GPR357, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    573. 

  573. -  { "h-sys-gpr358", HW_H_SYS_GPR358, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    574. 

  574. -  { "h-sys-gpr359", HW_H_SYS_GPR359, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    575. 

  575. -  { "h-sys-gpr360", HW_H_SYS_GPR360, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    576. 

  576. -  { "h-sys-gpr361", HW_H_SYS_GPR361, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    577. 

  577. -  { "h-sys-gpr362", HW_H_SYS_GPR362, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    578. 

  578. -  { "h-sys-gpr363", HW_H_SYS_GPR363, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    579. 

  579. -  { "h-sys-gpr364", HW_H_SYS_GPR364, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    580. 

  580. -  { "h-sys-gpr365", HW_H_SYS_GPR365, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    581. 

  581. -  { "h-sys-gpr366", HW_H_SYS_GPR366, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    582. 

  582. -  { "h-sys-gpr367", HW_H_SYS_GPR367, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    583. 

  583. -  { "h-sys-gpr368", HW_H_SYS_GPR368, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    584. 

  584. -  { "h-sys-gpr369", HW_H_SYS_GPR369, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    585. 

  585. -  { "h-sys-gpr370", HW_H_SYS_GPR370, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    586. 

  586. -  { "h-sys-gpr371", HW_H_SYS_GPR371, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    587. 

  587. -  { "h-sys-gpr372", HW_H_SYS_GPR372, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    588. 

  588. -  { "h-sys-gpr373", HW_H_SYS_GPR373, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    589. 

  589. -  { "h-sys-gpr374", HW_H_SYS_GPR374, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    590. 

  590. -  { "h-sys-gpr375", HW_H_SYS_GPR375, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    591. 

  591. -  { "h-sys-gpr376", HW_H_SYS_GPR376, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    592. 

  592. -  { "h-sys-gpr377", HW_H_SYS_GPR377, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    593. 

  593. -  { "h-sys-gpr378", HW_H_SYS_GPR378, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    594. 

  594. -  { "h-sys-gpr379", HW_H_SYS_GPR379, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    595. 

  595. -  { "h-sys-gpr380", HW_H_SYS_GPR380, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    596. 

  596. -  { "h-sys-gpr381", HW_H_SYS_GPR381, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    597. 

  597. -  { "h-sys-gpr382", HW_H_SYS_GPR382, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    598. 

  598. -  { "h-sys-gpr383", HW_H_SYS_GPR383, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    599. 

  599. -  { "h-sys-gpr384", HW_H_SYS_GPR384, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    600. 

  600. -  { "h-sys-gpr385", HW_H_SYS_GPR385, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    601. 

  601. -  { "h-sys-gpr386", HW_H_SYS_GPR386, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    602. 

  602. -  { "h-sys-gpr387", HW_H_SYS_GPR387, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    603. 

  603. -  { "h-sys-gpr388", HW_H_SYS_GPR388, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    604. 

  604. -  { "h-sys-gpr389", HW_H_SYS_GPR389, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    605. 

  605. -  { "h-sys-gpr390", HW_H_SYS_GPR390, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    606. 

  606. -  { "h-sys-gpr391", HW_H_SYS_GPR391, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    607. 

  607. -  { "h-sys-gpr392", HW_H_SYS_GPR392, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    608. 

  608. -  { "h-sys-gpr393", HW_H_SYS_GPR393, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    609. 

  609. -  { "h-sys-gpr394", HW_H_SYS_GPR394, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    610. 

  610. -  { "h-sys-gpr395", HW_H_SYS_GPR395, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    611. 

  611. -  { "h-sys-gpr396", HW_H_SYS_GPR396, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    612. 

  612. -  { "h-sys-gpr397", HW_H_SYS_GPR397, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    613. 

  613. -  { "h-sys-gpr398", HW_H_SYS_GPR398, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    614. 

  614. -  { "h-sys-gpr399", HW_H_SYS_GPR399, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    615. 

  615. -  { "h-sys-gpr400", HW_H_SYS_GPR400, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    616. 

  616. -  { "h-sys-gpr401", HW_H_SYS_GPR401, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    617. 

  617. -  { "h-sys-gpr402", HW_H_SYS_GPR402, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    618. 

  618. -  { "h-sys-gpr403", HW_H_SYS_GPR403, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    619. 

  619. -  { "h-sys-gpr404", HW_H_SYS_GPR404, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    620. 

  620. -  { "h-sys-gpr405", HW_H_SYS_GPR405, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    621. 

  621. -  { "h-sys-gpr406", HW_H_SYS_GPR406, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    622. 

  622. -  { "h-sys-gpr407", HW_H_SYS_GPR407, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    623. 

  623. -  { "h-sys-gpr408", HW_H_SYS_GPR408, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    624. 

  624. -  { "h-sys-gpr409", HW_H_SYS_GPR409, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    625. 

  625. -  { "h-sys-gpr410", HW_H_SYS_GPR410, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    626. 

  626. -  { "h-sys-gpr411", HW_H_SYS_GPR411, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    627. 

  627. -  { "h-sys-gpr412", HW_H_SYS_GPR412, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    628. 

  628. -  { "h-sys-gpr413", HW_H_SYS_GPR413, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    629. 

  629. -  { "h-sys-gpr414", HW_H_SYS_GPR414, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    630. 

  630. -  { "h-sys-gpr415", HW_H_SYS_GPR415, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    631. 

  631. -  { "h-sys-gpr416", HW_H_SYS_GPR416, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    632. 

  632. -  { "h-sys-gpr417", HW_H_SYS_GPR417, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    633. 

  633. -  { "h-sys-gpr418", HW_H_SYS_GPR418, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    634. 

  634. -  { "h-sys-gpr419", HW_H_SYS_GPR419, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    635. 

  635. -  { "h-sys-gpr420", HW_H_SYS_GPR420, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    636. 

  636. -  { "h-sys-gpr421", HW_H_SYS_GPR421, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    637. 

  637. -  { "h-sys-gpr422", HW_H_SYS_GPR422, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    638. 

  638. -  { "h-sys-gpr423", HW_H_SYS_GPR423, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    639. 

  639. -  { "h-sys-gpr424", HW_H_SYS_GPR424, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    640. 

  640. -  { "h-sys-gpr425", HW_H_SYS_GPR425, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    641. 

  641. -  { "h-sys-gpr426", HW_H_SYS_GPR426, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    642. 

  642. -  { "h-sys-gpr427", HW_H_SYS_GPR427, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    643. 

  643. -  { "h-sys-gpr428", HW_H_SYS_GPR428, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    644. 

  644. -  { "h-sys-gpr429", HW_H_SYS_GPR429, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    645. 

  645. -  { "h-sys-gpr430", HW_H_SYS_GPR430, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    646. 

  646. -  { "h-sys-gpr431", HW_H_SYS_GPR431, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    647. 

  647. -  { "h-sys-gpr432", HW_H_SYS_GPR432, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    648. 

  648. -  { "h-sys-gpr433", HW_H_SYS_GPR433, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    649. 

  649. -  { "h-sys-gpr434", HW_H_SYS_GPR434, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    650. 

  650. -  { "h-sys-gpr435", HW_H_SYS_GPR435, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    651. 

  651. -  { "h-sys-gpr436", HW_H_SYS_GPR436, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    652. 

  652. -  { "h-sys-gpr437", HW_H_SYS_GPR437, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    653. 

  653. -  { "h-sys-gpr438", HW_H_SYS_GPR438, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    654. 

  654. -  { "h-sys-gpr439", HW_H_SYS_GPR439, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    655. 

  655. -  { "h-sys-gpr440", HW_H_SYS_GPR440, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    656. 

  656. -  { "h-sys-gpr441", HW_H_SYS_GPR441, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    657. 

  657. -  { "h-sys-gpr442", HW_H_SYS_GPR442, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    658. 

  658. -  { "h-sys-gpr443", HW_H_SYS_GPR443, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    659. 

  659. -  { "h-sys-gpr444", HW_H_SYS_GPR444, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    660. 

  660. -  { "h-sys-gpr445", HW_H_SYS_GPR445, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    661. 

  661. -  { "h-sys-gpr446", HW_H_SYS_GPR446, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    662. 

  662. -  { "h-sys-gpr447", HW_H_SYS_GPR447, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    663. 

  663. -  { "h-sys-gpr448", HW_H_SYS_GPR448, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    664. 

  664. -  { "h-sys-gpr449", HW_H_SYS_GPR449, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    665. 

  665. -  { "h-sys-gpr450", HW_H_SYS_GPR450, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    666. 

  666. -  { "h-sys-gpr451", HW_H_SYS_GPR451, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    667. 

  667. -  { "h-sys-gpr452", HW_H_SYS_GPR452, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    668. 

  668. -  { "h-sys-gpr453", HW_H_SYS_GPR453, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    669. 

  669. -  { "h-sys-gpr454", HW_H_SYS_GPR454, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    670. 

  670. -  { "h-sys-gpr455", HW_H_SYS_GPR455, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    671. 

  671. -  { "h-sys-gpr456", HW_H_SYS_GPR456, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    672. 

  672. -  { "h-sys-gpr457", HW_H_SYS_GPR457, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    673. 

  673. -  { "h-sys-gpr458", HW_H_SYS_GPR458, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    674. 

  674. -  { "h-sys-gpr459", HW_H_SYS_GPR459, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    675. 

  675. -  { "h-sys-gpr460", HW_H_SYS_GPR460, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    676. 

  676. -  { "h-sys-gpr461", HW_H_SYS_GPR461, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    677. 

  677. -  { "h-sys-gpr462", HW_H_SYS_GPR462, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    678. 

  678. -  { "h-sys-gpr463", HW_H_SYS_GPR463, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    679. 

  679. -  { "h-sys-gpr464", HW_H_SYS_GPR464, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    680. 

  680. -  { "h-sys-gpr465", HW_H_SYS_GPR465, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    681. 

  681. -  { "h-sys-gpr466", HW_H_SYS_GPR466, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    682. 

  682. -  { "h-sys-gpr467", HW_H_SYS_GPR467, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    683. 

  683. -  { "h-sys-gpr468", HW_H_SYS_GPR468, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    684. 

  684. -  { "h-sys-gpr469", HW_H_SYS_GPR469, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    685. 

  685. -  { "h-sys-gpr470", HW_H_SYS_GPR470, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    686. 

  686. -  { "h-sys-gpr471", HW_H_SYS_GPR471, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    687. 

  687. -  { "h-sys-gpr472", HW_H_SYS_GPR472, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    688. 

  688. -  { "h-sys-gpr473", HW_H_SYS_GPR473, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    689. 

  689. -  { "h-sys-gpr474", HW_H_SYS_GPR474, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    690. 

  690. -  { "h-sys-gpr475", HW_H_SYS_GPR475, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    691. 

  691. -  { "h-sys-gpr476", HW_H_SYS_GPR476, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    692. 

  692. -  { "h-sys-gpr477", HW_H_SYS_GPR477, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    693. 

  693. -  { "h-sys-gpr478", HW_H_SYS_GPR478, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    694. 

  694. -  { "h-sys-gpr479", HW_H_SYS_GPR479, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    695. 

  695. -  { "h-sys-gpr480", HW_H_SYS_GPR480, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    696. 

  696. -  { "h-sys-gpr481", HW_H_SYS_GPR481, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    697. 

  697. -  { "h-sys-gpr482", HW_H_SYS_GPR482, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    698. 

  698. -  { "h-sys-gpr483", HW_H_SYS_GPR483, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    699. 

  699. -  { "h-sys-gpr484", HW_H_SYS_GPR484, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    700. 

  700. -  { "h-sys-gpr485", HW_H_SYS_GPR485, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    701. 

  701. -  { "h-sys-gpr486", HW_H_SYS_GPR486, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    702. 

  702. -  { "h-sys-gpr487", HW_H_SYS_GPR487, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    703. 

  703. -  { "h-sys-gpr488", HW_H_SYS_GPR488, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    704. 

  704. -  { "h-sys-gpr489", HW_H_SYS_GPR489, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    705. 

  705. -  { "h-sys-gpr490", HW_H_SYS_GPR490, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    706. 

  706. -  { "h-sys-gpr491", HW_H_SYS_GPR491, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    707. 

  707. -  { "h-sys-gpr492", HW_H_SYS_GPR492, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    708. 

  708. -  { "h-sys-gpr493", HW_H_SYS_GPR493, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    709. 

  709. -  { "h-sys-gpr494", HW_H_SYS_GPR494, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    710. 

  710. -  { "h-sys-gpr495", HW_H_SYS_GPR495, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    711. 

  711. -  { "h-sys-gpr496", HW_H_SYS_GPR496, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    712. 

  712. -  { "h-sys-gpr497", HW_H_SYS_GPR497, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    713. 

  713. -  { "h-sys-gpr498", HW_H_SYS_GPR498, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    714. 

  714. -  { "h-sys-gpr499", HW_H_SYS_GPR499, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    715. 

  715. -  { "h-sys-gpr500", HW_H_SYS_GPR500, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    716. 

  716. -  { "h-sys-gpr501", HW_H_SYS_GPR501, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    717. 

  717. -  { "h-sys-gpr502", HW_H_SYS_GPR502, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    718. 

  718. -  { "h-sys-gpr503", HW_H_SYS_GPR503, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    719. 

  719. -  { "h-sys-gpr504", HW_H_SYS_GPR504, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    720. 

  720. -  { "h-sys-gpr505", HW_H_SYS_GPR505, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    721. 

  721. -  { "h-sys-gpr506", HW_H_SYS_GPR506, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    722. 

  722. -  { "h-sys-gpr507", HW_H_SYS_GPR507, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    723. 

  723. -  { "h-sys-gpr508", HW_H_SYS_GPR508, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    724. 

  724. -  { "h-sys-gpr509", HW_H_SYS_GPR509, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    725. 

  725. -  { "h-sys-gpr510", HW_H_SYS_GPR510, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    726. 

  726. -  { "h-sys-gpr511", HW_H_SYS_GPR511, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    727. 

  727. -  { "h-mac-maclo", HW_H_MAC_MACLO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    728. 

  728. -  { "h-mac-machi", HW_H_MAC_MACHI, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    729. 

  729. -  { "h-tick-ttmr", HW_H_TICK_TTMR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    730. 

  730. -  { "h-sys-vr-rev", HW_H_SYS_VR_REV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    731. 

  731. -  { "h-sys-vr-cfg", HW_H_SYS_VR_CFG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    732. 

  732. -  { "h-sys-vr-ver", HW_H_SYS_VR_VER, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    733. 

  733. -  { "h-sys-upr-up", HW_H_SYS_UPR_UP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    734. 

  734. -  { "h-sys-upr-dcp", HW_H_SYS_UPR_DCP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    735. 

  735. -  { "h-sys-upr-icp", HW_H_SYS_UPR_ICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    736. 

  736. -  { "h-sys-upr-dmp", HW_H_SYS_UPR_DMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    737. 

  737. -  { "h-sys-upr-mp", HW_H_SYS_UPR_MP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    738. 

  738. -  { "h-sys-upr-imp", HW_H_SYS_UPR_IMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    739. 

  739. -  { "h-sys-upr-dup", HW_H_SYS_UPR_DUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    740. 

  740. -  { "h-sys-upr-pcup", HW_H_SYS_UPR_PCUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    741. 

  741. -  { "h-sys-upr-picp", HW_H_SYS_UPR_PICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    742. 

  742. -  { "h-sys-upr-pmp", HW_H_SYS_UPR_PMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    743. 

  743. -  { "h-sys-upr-ttp", HW_H_SYS_UPR_TTP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    744. 

  744. -  { "h-sys-upr-cup", HW_H_SYS_UPR_CUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    745. 

  745. -  { "h-sys-cpucfgr-nsgr", HW_H_SYS_CPUCFGR_NSGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    746. 

  746. -  { "h-sys-cpucfgr-cgf", HW_H_SYS_CPUCFGR_CGF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    747. 

  747. -  { "h-sys-cpucfgr-ob32s", HW_H_SYS_CPUCFGR_OB32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    748. 

  748. -  { "h-sys-cpucfgr-ob64s", HW_H_SYS_CPUCFGR_OB64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    749. 

  749. -  { "h-sys-cpucfgr-of32s", HW_H_SYS_CPUCFGR_OF32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    750. 

  750. -  { "h-sys-cpucfgr-of64s", HW_H_SYS_CPUCFGR_OF64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    751. 

  751. -  { "h-sys-cpucfgr-ov64s", HW_H_SYS_CPUCFGR_OV64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    752. 

  752. -  { "h-sys-cpucfgr-nd", HW_H_SYS_CPUCFGR_ND, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    753. 

  753. -  { "h-sys-sr-sm", HW_H_SYS_SR_SM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    754. 

  754. -  { "h-sys-sr-tee", HW_H_SYS_SR_TEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    755. 

  755. -  { "h-sys-sr-iee", HW_H_SYS_SR_IEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    756. 

  756. -  { "h-sys-sr-dce", HW_H_SYS_SR_DCE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    757. 

  757. -  { "h-sys-sr-ice", HW_H_SYS_SR_ICE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    758. 

  758. -  { "h-sys-sr-dme", HW_H_SYS_SR_DME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    759. 

  759. -  { "h-sys-sr-ime", HW_H_SYS_SR_IME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    760. 

  760. -  { "h-sys-sr-lee", HW_H_SYS_SR_LEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    761. 

  761. -  { "h-sys-sr-ce", HW_H_SYS_SR_CE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    762. 

  762. -  { "h-sys-sr-f", HW_H_SYS_SR_F, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    763. 

  763. -  { "h-sys-sr-cy", HW_H_SYS_SR_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    764. 

  764. -  { "h-sys-sr-ov", HW_H_SYS_SR_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    765. 

  765. -  { "h-sys-sr-ove", HW_H_SYS_SR_OVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    766. 

  766. -  { "h-sys-sr-dsx", HW_H_SYS_SR_DSX, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    767. 

  767. -  { "h-sys-sr-eph", HW_H_SYS_SR_EPH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    768. 

  768. -  { "h-sys-sr-fo", HW_H_SYS_SR_FO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    769. 

  769. -  { "h-sys-sr-sumra", HW_H_SYS_SR_SUMRA, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    770. 

  770. -  { "h-sys-sr-cid", HW_H_SYS_SR_CID, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    771. 

  771. -  { "h-sys-fpcsr-fpee", HW_H_SYS_FPCSR_FPEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    772. 

  772. -  { "h-sys-fpcsr-rm", HW_H_SYS_FPCSR_RM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    773. 

  773. -  { "h-sys-fpcsr-ovf", HW_H_SYS_FPCSR_OVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    774. 

  774. -  { "h-sys-fpcsr-unf", HW_H_SYS_FPCSR_UNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    775. 

  775. -  { "h-sys-fpcsr-snf", HW_H_SYS_FPCSR_SNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    776. 

  776. -  { "h-sys-fpcsr-qnf", HW_H_SYS_FPCSR_QNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    777. 

  777. -  { "h-sys-fpcsr-zf", HW_H_SYS_FPCSR_ZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    778. 

  778. -  { "h-sys-fpcsr-ixf", HW_H_SYS_FPCSR_IXF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    779. 

  779. -  { "h-sys-fpcsr-ivf", HW_H_SYS_FPCSR_IVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    780. 

  780. -  { "h-sys-fpcsr-inf", HW_H_SYS_FPCSR_INF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    781. 

  781. -  { "h-sys-fpcsr-dzf", HW_H_SYS_FPCSR_DZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    782. 

  782. -  { "h-simm16", HW_H_SIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    783. 

  783. +  { "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    784. 

  784. +  { "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    785. 

  785. +  { "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    786. 

  786. +  { "h-sys-dmmucfgr", HW_H_SYS_DMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    787. 

  787. +  { "h-sys-immucfgr", HW_H_SYS_IMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    788. 

  788. +  { "h-sys-dccfgr", HW_H_SYS_DCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    789. 

  789. +  { "h-sys-iccfgr", HW_H_SYS_ICCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    790. 

  790. +  { "h-sys-dcfgr", HW_H_SYS_DCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    791. 

  791. +  { "h-sys-pccfgr", HW_H_SYS_PCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    792. 

  792. +  { "h-sys-npc", HW_H_SYS_NPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    793. 

  793. +  { "h-sys-sr", HW_H_SYS_SR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    794. 

  794. +  { "h-sys-ppc", HW_H_SYS_PPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    795. 

  795. +  { "h-sys-fpcsr", HW_H_SYS_FPCSR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    796. 

  796. +  { "h-sys-epcr0", HW_H_SYS_EPCR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    797. 

  797. +  { "h-sys-epcr1", HW_H_SYS_EPCR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    798. 

  798. +  { "h-sys-epcr2", HW_H_SYS_EPCR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    799. 

  799. +  { "h-sys-epcr3", HW_H_SYS_EPCR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    800. 

  800. +  { "h-sys-epcr4", HW_H_SYS_EPCR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    801. 

  801. +  { "h-sys-epcr5", HW_H_SYS_EPCR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    802. 

  802. +  { "h-sys-epcr6", HW_H_SYS_EPCR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    803. 

  803. +  { "h-sys-epcr7", HW_H_SYS_EPCR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    804. 

  804. +  { "h-sys-epcr8", HW_H_SYS_EPCR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    805. 

  805. +  { "h-sys-epcr9", HW_H_SYS_EPCR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    806. 

  806. +  { "h-sys-epcr10", HW_H_SYS_EPCR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    807. 

  807. +  { "h-sys-epcr11", HW_H_SYS_EPCR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    808. 

  808. +  { "h-sys-epcr12", HW_H_SYS_EPCR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    809. 

  809. +  { "h-sys-epcr13", HW_H_SYS_EPCR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    810. 

  810. +  { "h-sys-epcr14", HW_H_SYS_EPCR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    811. 

  811. +  { "h-sys-epcr15", HW_H_SYS_EPCR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    812. 

  812. +  { "h-sys-eear0", HW_H_SYS_EEAR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    813. 

  813. +  { "h-sys-eear1", HW_H_SYS_EEAR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    814. 

  814. +  { "h-sys-eear2", HW_H_SYS_EEAR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    815. 

  815. +  { "h-sys-eear3", HW_H_SYS_EEAR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    816. 

  816. +  { "h-sys-eear4", HW_H_SYS_EEAR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    817. 

  817. +  { "h-sys-eear5", HW_H_SYS_EEAR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    818. 

  818. +  { "h-sys-eear6", HW_H_SYS_EEAR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    819. 

  819. +  { "h-sys-eear7", HW_H_SYS_EEAR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    820. 

  820. +  { "h-sys-eear8", HW_H_SYS_EEAR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    821. 

  821. +  { "h-sys-eear9", HW_H_SYS_EEAR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    822. 

  822. +  { "h-sys-eear10", HW_H_SYS_EEAR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    823. 

  823. +  { "h-sys-eear11", HW_H_SYS_EEAR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    824. 

  824. +  { "h-sys-eear12", HW_H_SYS_EEAR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    825. 

  825. +  { "h-sys-eear13", HW_H_SYS_EEAR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    826. 

  826. +  { "h-sys-eear14", HW_H_SYS_EEAR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    827. 

  827. +  { "h-sys-eear15", HW_H_SYS_EEAR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    828. 

  828. +  { "h-sys-esr0", HW_H_SYS_ESR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    829. 

  829. +  { "h-sys-esr1", HW_H_SYS_ESR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    830. 

  830. +  { "h-sys-esr2", HW_H_SYS_ESR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    831. 

  831. +  { "h-sys-esr3", HW_H_SYS_ESR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    832. 

  832. +  { "h-sys-esr4", HW_H_SYS_ESR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    833. 

  833. +  { "h-sys-esr5", HW_H_SYS_ESR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    834. 

  834. +  { "h-sys-esr6", HW_H_SYS_ESR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    835. 

  835. +  { "h-sys-esr7", HW_H_SYS_ESR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    836. 

  836. +  { "h-sys-esr8", HW_H_SYS_ESR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    837. 

  837. +  { "h-sys-esr9", HW_H_SYS_ESR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    838. 

  838. +  { "h-sys-esr10", HW_H_SYS_ESR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    839. 

  839. +  { "h-sys-esr11", HW_H_SYS_ESR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    840. 

  840. +  { "h-sys-esr12", HW_H_SYS_ESR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    841. 

  841. +  { "h-sys-esr13", HW_H_SYS_ESR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    842. 

  842. +  { "h-sys-esr14", HW_H_SYS_ESR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    843. 

  843. +  { "h-sys-esr15", HW_H_SYS_ESR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    844. 

  844. +  { "h-sys-gpr0", HW_H_SYS_GPR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    845. 

  845. +  { "h-sys-gpr1", HW_H_SYS_GPR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    846. 

  846. +  { "h-sys-gpr2", HW_H_SYS_GPR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    847. 

  847. +  { "h-sys-gpr3", HW_H_SYS_GPR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    848. 

  848. +  { "h-sys-gpr4", HW_H_SYS_GPR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    849. 

  849. +  { "h-sys-gpr5", HW_H_SYS_GPR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    850. 

  850. +  { "h-sys-gpr6", HW_H_SYS_GPR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    851. 

  851. +  { "h-sys-gpr7", HW_H_SYS_GPR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    852. 

  852. +  { "h-sys-gpr8", HW_H_SYS_GPR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    853. 

  853. +  { "h-sys-gpr9", HW_H_SYS_GPR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    854. 

  854. +  { "h-sys-gpr10", HW_H_SYS_GPR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    855. 

  855. +  { "h-sys-gpr11", HW_H_SYS_GPR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    856. 

  856. +  { "h-sys-gpr12", HW_H_SYS_GPR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    857. 

  857. +  { "h-sys-gpr13", HW_H_SYS_GPR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    858. 

  858. +  { "h-sys-gpr14", HW_H_SYS_GPR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    859. 

  859. +  { "h-sys-gpr15", HW_H_SYS_GPR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    860. 

  860. +  { "h-sys-gpr16", HW_H_SYS_GPR16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    861. 

  861. +  { "h-sys-gpr17", HW_H_SYS_GPR17, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    862. 

  862. +  { "h-sys-gpr18", HW_H_SYS_GPR18, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    863. 

  863. +  { "h-sys-gpr19", HW_H_SYS_GPR19, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    864. 

  864. +  { "h-sys-gpr20", HW_H_SYS_GPR20, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    865. 

  865. +  { "h-sys-gpr21", HW_H_SYS_GPR21, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    866. 

  866. +  { "h-sys-gpr22", HW_H_SYS_GPR22, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    867. 

  867. +  { "h-sys-gpr23", HW_H_SYS_GPR23, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    868. 

  868. +  { "h-sys-gpr24", HW_H_SYS_GPR24, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    869. 

  869. +  { "h-sys-gpr25", HW_H_SYS_GPR25, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    870. 

  870. +  { "h-sys-gpr26", HW_H_SYS_GPR26, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    871. 

  871. +  { "h-sys-gpr27", HW_H_SYS_GPR27, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    872. 

  872. +  { "h-sys-gpr28", HW_H_SYS_GPR28, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    873. 

  873. +  { "h-sys-gpr29", HW_H_SYS_GPR29, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    874. 

  874. +  { "h-sys-gpr30", HW_H_SYS_GPR30, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    875. 

  875. +  { "h-sys-gpr31", HW_H_SYS_GPR31, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    876. 

  876. +  { "h-sys-gpr32", HW_H_SYS_GPR32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    877. 

  877. +  { "h-sys-gpr33", HW_H_SYS_GPR33, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    878. 

  878. +  { "h-sys-gpr34", HW_H_SYS_GPR34, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    879. 

  879. +  { "h-sys-gpr35", HW_H_SYS_GPR35, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    880. 

  880. +  { "h-sys-gpr36", HW_H_SYS_GPR36, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    881. 

  881. +  { "h-sys-gpr37", HW_H_SYS_GPR37, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    882. 

  882. +  { "h-sys-gpr38", HW_H_SYS_GPR38, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    883. 

  883. +  { "h-sys-gpr39", HW_H_SYS_GPR39, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    884. 

  884. +  { "h-sys-gpr40", HW_H_SYS_GPR40, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    885. 

  885. +  { "h-sys-gpr41", HW_H_SYS_GPR41, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    886. 

  886. +  { "h-sys-gpr42", HW_H_SYS_GPR42, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    887. 

  887. +  { "h-sys-gpr43", HW_H_SYS_GPR43, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    888. 

  888. +  { "h-sys-gpr44", HW_H_SYS_GPR44, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    889. 

  889. +  { "h-sys-gpr45", HW_H_SYS_GPR45, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    890. 

  890. +  { "h-sys-gpr46", HW_H_SYS_GPR46, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    891. 

  891. +  { "h-sys-gpr47", HW_H_SYS_GPR47, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    892. 

  892. +  { "h-sys-gpr48", HW_H_SYS_GPR48, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    893. 

  893. +  { "h-sys-gpr49", HW_H_SYS_GPR49, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    894. 

  894. +  { "h-sys-gpr50", HW_H_SYS_GPR50, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    895. 

  895. +  { "h-sys-gpr51", HW_H_SYS_GPR51, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    896. 

  896. +  { "h-sys-gpr52", HW_H_SYS_GPR52, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    897. 

  897. +  { "h-sys-gpr53", HW_H_SYS_GPR53, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    898. 

  898. +  { "h-sys-gpr54", HW_H_SYS_GPR54, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    899. 

  899. +  { "h-sys-gpr55", HW_H_SYS_GPR55, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    900. 

  900. +  { "h-sys-gpr56", HW_H_SYS_GPR56, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    901. 

  901. +  { "h-sys-gpr57", HW_H_SYS_GPR57, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    902. 

  902. +  { "h-sys-gpr58", HW_H_SYS_GPR58, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    903. 

  903. +  { "h-sys-gpr59", HW_H_SYS_GPR59, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    904. 

  904. +  { "h-sys-gpr60", HW_H_SYS_GPR60, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    905. 

  905. +  { "h-sys-gpr61", HW_H_SYS_GPR61, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    906. 

  906. +  { "h-sys-gpr62", HW_H_SYS_GPR62, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    907. 

  907. +  { "h-sys-gpr63", HW_H_SYS_GPR63, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    908. 

  908. +  { "h-sys-gpr64", HW_H_SYS_GPR64, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    909. 

  909. +  { "h-sys-gpr65", HW_H_SYS_GPR65, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    910. 

  910. +  { "h-sys-gpr66", HW_H_SYS_GPR66, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    911. 

  911. +  { "h-sys-gpr67", HW_H_SYS_GPR67, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    912. 

  912. +  { "h-sys-gpr68", HW_H_SYS_GPR68, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    913. 

  913. +  { "h-sys-gpr69", HW_H_SYS_GPR69, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    914. 

  914. +  { "h-sys-gpr70", HW_H_SYS_GPR70, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    915. 

  915. +  { "h-sys-gpr71", HW_H_SYS_GPR71, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    916. 

  916. +  { "h-sys-gpr72", HW_H_SYS_GPR72, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    917. 

  917. +  { "h-sys-gpr73", HW_H_SYS_GPR73, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    918. 

  918. +  { "h-sys-gpr74", HW_H_SYS_GPR74, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    919. 

  919. +  { "h-sys-gpr75", HW_H_SYS_GPR75, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    920. 

  920. +  { "h-sys-gpr76", HW_H_SYS_GPR76, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    921. 

  921. +  { "h-sys-gpr77", HW_H_SYS_GPR77, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    922. 

  922. +  { "h-sys-gpr78", HW_H_SYS_GPR78, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    923. 

  923. +  { "h-sys-gpr79", HW_H_SYS_GPR79, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    924. 

  924. +  { "h-sys-gpr80", HW_H_SYS_GPR80, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    925. 

  925. +  { "h-sys-gpr81", HW_H_SYS_GPR81, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    926. 

  926. +  { "h-sys-gpr82", HW_H_SYS_GPR82, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    927. 

  927. +  { "h-sys-gpr83", HW_H_SYS_GPR83, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    928. 

  928. +  { "h-sys-gpr84", HW_H_SYS_GPR84, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    929. 

  929. +  { "h-sys-gpr85", HW_H_SYS_GPR85, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    930. 

  930. +  { "h-sys-gpr86", HW_H_SYS_GPR86, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    931. 

  931. +  { "h-sys-gpr87", HW_H_SYS_GPR87, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    932. 

  932. +  { "h-sys-gpr88", HW_H_SYS_GPR88, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    933. 

  933. +  { "h-sys-gpr89", HW_H_SYS_GPR89, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    934. 

  934. +  { "h-sys-gpr90", HW_H_SYS_GPR90, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    935. 

  935. +  { "h-sys-gpr91", HW_H_SYS_GPR91, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    936. 

  936. +  { "h-sys-gpr92", HW_H_SYS_GPR92, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    937. 

  937. +  { "h-sys-gpr93", HW_H_SYS_GPR93, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    938. 

  938. +  { "h-sys-gpr94", HW_H_SYS_GPR94, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    939. 

  939. +  { "h-sys-gpr95", HW_H_SYS_GPR95, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    940. 

  940. +  { "h-sys-gpr96", HW_H_SYS_GPR96, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    941. 

  941. +  { "h-sys-gpr97", HW_H_SYS_GPR97, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    942. 

  942. +  { "h-sys-gpr98", HW_H_SYS_GPR98, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    943. 

  943. +  { "h-sys-gpr99", HW_H_SYS_GPR99, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    944. 

  944. +  { "h-sys-gpr100", HW_H_SYS_GPR100, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    945. 

  945. +  { "h-sys-gpr101", HW_H_SYS_GPR101, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    946. 

  946. +  { "h-sys-gpr102", HW_H_SYS_GPR102, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    947. 

  947. +  { "h-sys-gpr103", HW_H_SYS_GPR103, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    948. 

  948. +  { "h-sys-gpr104", HW_H_SYS_GPR104, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    949. 

  949. +  { "h-sys-gpr105", HW_H_SYS_GPR105, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    950. 

  950. +  { "h-sys-gpr106", HW_H_SYS_GPR106, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    951. 

  951. +  { "h-sys-gpr107", HW_H_SYS_GPR107, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    952. 

  952. +  { "h-sys-gpr108", HW_H_SYS_GPR108, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    953. 

  953. +  { "h-sys-gpr109", HW_H_SYS_GPR109, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    954. 

  954. +  { "h-sys-gpr110", HW_H_SYS_GPR110, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    955. 

  955. +  { "h-sys-gpr111", HW_H_SYS_GPR111, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    956. 

  956. +  { "h-sys-gpr112", HW_H_SYS_GPR112, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    957. 

  957. +  { "h-sys-gpr113", HW_H_SYS_GPR113, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    958. 

  958. +  { "h-sys-gpr114", HW_H_SYS_GPR114, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    959. 

  959. +  { "h-sys-gpr115", HW_H_SYS_GPR115, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    960. 

  960. +  { "h-sys-gpr116", HW_H_SYS_GPR116, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    961. 

  961. +  { "h-sys-gpr117", HW_H_SYS_GPR117, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    962. 

  962. +  { "h-sys-gpr118", HW_H_SYS_GPR118, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    963. 

  963. +  { "h-sys-gpr119", HW_H_SYS_GPR119, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    964. 

  964. +  { "h-sys-gpr120", HW_H_SYS_GPR120, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    965. 

  965. +  { "h-sys-gpr121", HW_H_SYS_GPR121, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    966. 

  966. +  { "h-sys-gpr122", HW_H_SYS_GPR122, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    967. 

  967. +  { "h-sys-gpr123", HW_H_SYS_GPR123, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    968. 

  968. +  { "h-sys-gpr124", HW_H_SYS_GPR124, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    969. 

  969. +  { "h-sys-gpr125", HW_H_SYS_GPR125, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    970. 

  970. +  { "h-sys-gpr126", HW_H_SYS_GPR126, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    971. 

  971. +  { "h-sys-gpr127", HW_H_SYS_GPR127, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    972. 

  972. +  { "h-sys-gpr128", HW_H_SYS_GPR128, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    973. 

  973. +  { "h-sys-gpr129", HW_H_SYS_GPR129, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    974. 

  974. +  { "h-sys-gpr130", HW_H_SYS_GPR130, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    975. 

  975. +  { "h-sys-gpr131", HW_H_SYS_GPR131, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    976. 

  976. +  { "h-sys-gpr132", HW_H_SYS_GPR132, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    977. 

  977. +  { "h-sys-gpr133", HW_H_SYS_GPR133, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    978. 

  978. +  { "h-sys-gpr134", HW_H_SYS_GPR134, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    979. 

  979. +  { "h-sys-gpr135", HW_H_SYS_GPR135, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    980. 

  980. +  { "h-sys-gpr136", HW_H_SYS_GPR136, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    981. 

  981. +  { "h-sys-gpr137", HW_H_SYS_GPR137, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    982. 

  982. +  { "h-sys-gpr138", HW_H_SYS_GPR138, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    983. 

  983. +  { "h-sys-gpr139", HW_H_SYS_GPR139, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    984. 

  984. +  { "h-sys-gpr140", HW_H_SYS_GPR140, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    985. 

  985. +  { "h-sys-gpr141", HW_H_SYS_GPR141, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    986. 

  986. +  { "h-sys-gpr142", HW_H_SYS_GPR142, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    987. 

  987. +  { "h-sys-gpr143", HW_H_SYS_GPR143, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    988. 

  988. +  { "h-sys-gpr144", HW_H_SYS_GPR144, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    989. 

  989. +  { "h-sys-gpr145", HW_H_SYS_GPR145, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    990. 

  990. +  { "h-sys-gpr146", HW_H_SYS_GPR146, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    991. 

  991. +  { "h-sys-gpr147", HW_H_SYS_GPR147, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    992. 

  992. +  { "h-sys-gpr148", HW_H_SYS_GPR148, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    993. 

  993. +  { "h-sys-gpr149", HW_H_SYS_GPR149, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    994. 

  994. +  { "h-sys-gpr150", HW_H_SYS_GPR150, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    995. 

  995. +  { "h-sys-gpr151", HW_H_SYS_GPR151, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    996. 

  996. +  { "h-sys-gpr152", HW_H_SYS_GPR152, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    997. 

  997. +  { "h-sys-gpr153", HW_H_SYS_GPR153, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    998. 

  998. +  { "h-sys-gpr154", HW_H_SYS_GPR154, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    999. 

  999. +  { "h-sys-gpr155", HW_H_SYS_GPR155, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1000. 

  1000. +  { "h-sys-gpr156", HW_H_SYS_GPR156, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1001. 

  1001. +  { "h-sys-gpr157", HW_H_SYS_GPR157, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1002. 

  1002. +  { "h-sys-gpr158", HW_H_SYS_GPR158, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1003. 

  1003. +  { "h-sys-gpr159", HW_H_SYS_GPR159, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1004. 

  1004. +  { "h-sys-gpr160", HW_H_SYS_GPR160, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1005. 

  1005. +  { "h-sys-gpr161", HW_H_SYS_GPR161, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1006. 

  1006. +  { "h-sys-gpr162", HW_H_SYS_GPR162, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1007. 

  1007. +  { "h-sys-gpr163", HW_H_SYS_GPR163, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1008. 

  1008. +  { "h-sys-gpr164", HW_H_SYS_GPR164, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1009. 

  1009. +  { "h-sys-gpr165", HW_H_SYS_GPR165, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1010. 

  1010. +  { "h-sys-gpr166", HW_H_SYS_GPR166, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1011. 

  1011. +  { "h-sys-gpr167", HW_H_SYS_GPR167, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1012. 

  1012. +  { "h-sys-gpr168", HW_H_SYS_GPR168, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1013. 

  1013. +  { "h-sys-gpr169", HW_H_SYS_GPR169, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1014. 

  1014. +  { "h-sys-gpr170", HW_H_SYS_GPR170, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1015. 

  1015. +  { "h-sys-gpr171", HW_H_SYS_GPR171, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1016. 

  1016. +  { "h-sys-gpr172", HW_H_SYS_GPR172, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1017. 

  1017. +  { "h-sys-gpr173", HW_H_SYS_GPR173, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1018. 

  1018. +  { "h-sys-gpr174", HW_H_SYS_GPR174, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1019. 

  1019. +  { "h-sys-gpr175", HW_H_SYS_GPR175, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1020. 

  1020. +  { "h-sys-gpr176", HW_H_SYS_GPR176, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1021. 

  1021. +  { "h-sys-gpr177", HW_H_SYS_GPR177, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1022. 

  1022. +  { "h-sys-gpr178", HW_H_SYS_GPR178, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1023. 

  1023. +  { "h-sys-gpr179", HW_H_SYS_GPR179, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1024. 

  1024. +  { "h-sys-gpr180", HW_H_SYS_GPR180, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1025. 

  1025. +  { "h-sys-gpr181", HW_H_SYS_GPR181, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1026. 

  1026. +  { "h-sys-gpr182", HW_H_SYS_GPR182, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1027. 

  1027. +  { "h-sys-gpr183", HW_H_SYS_GPR183, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1028. 

  1028. +  { "h-sys-gpr184", HW_H_SYS_GPR184, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1029. 

  1029. +  { "h-sys-gpr185", HW_H_SYS_GPR185, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1030. 

  1030. +  { "h-sys-gpr186", HW_H_SYS_GPR186, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1031. 

  1031. +  { "h-sys-gpr187", HW_H_SYS_GPR187, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1032. 

  1032. +  { "h-sys-gpr188", HW_H_SYS_GPR188, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1033. 

  1033. +  { "h-sys-gpr189", HW_H_SYS_GPR189, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1034. 

  1034. +  { "h-sys-gpr190", HW_H_SYS_GPR190, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1035. 

  1035. +  { "h-sys-gpr191", HW_H_SYS_GPR191, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1036. 

  1036. +  { "h-sys-gpr192", HW_H_SYS_GPR192, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1037. 

  1037. +  { "h-sys-gpr193", HW_H_SYS_GPR193, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1038. 

  1038. +  { "h-sys-gpr194", HW_H_SYS_GPR194, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1039. 

  1039. +  { "h-sys-gpr195", HW_H_SYS_GPR195, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1040. 

  1040. +  { "h-sys-gpr196", HW_H_SYS_GPR196, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1041. 

  1041. +  { "h-sys-gpr197", HW_H_SYS_GPR197, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1042. 

  1042. +  { "h-sys-gpr198", HW_H_SYS_GPR198, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1043. 

  1043. +  { "h-sys-gpr199", HW_H_SYS_GPR199, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1044. 

  1044. +  { "h-sys-gpr200", HW_H_SYS_GPR200, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1045. 

  1045. +  { "h-sys-gpr201", HW_H_SYS_GPR201, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1046. 

  1046. +  { "h-sys-gpr202", HW_H_SYS_GPR202, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1047. 

  1047. +  { "h-sys-gpr203", HW_H_SYS_GPR203, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1048. 

  1048. +  { "h-sys-gpr204", HW_H_SYS_GPR204, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1049. 

  1049. +  { "h-sys-gpr205", HW_H_SYS_GPR205, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1050. 

  1050. +  { "h-sys-gpr206", HW_H_SYS_GPR206, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1051. 

  1051. +  { "h-sys-gpr207", HW_H_SYS_GPR207, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1052. 

  1052. +  { "h-sys-gpr208", HW_H_SYS_GPR208, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1053. 

  1053. +  { "h-sys-gpr209", HW_H_SYS_GPR209, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1054. 

  1054. +  { "h-sys-gpr210", HW_H_SYS_GPR210, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1055. 

  1055. +  { "h-sys-gpr211", HW_H_SYS_GPR211, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1056. 

  1056. +  { "h-sys-gpr212", HW_H_SYS_GPR212, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1057. 

  1057. +  { "h-sys-gpr213", HW_H_SYS_GPR213, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1058. 

  1058. +  { "h-sys-gpr214", HW_H_SYS_GPR214, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1059. 

  1059. +  { "h-sys-gpr215", HW_H_SYS_GPR215, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1060. 

  1060. +  { "h-sys-gpr216", HW_H_SYS_GPR216, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1061. 

  1061. +  { "h-sys-gpr217", HW_H_SYS_GPR217, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1062. 

  1062. +  { "h-sys-gpr218", HW_H_SYS_GPR218, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1063. 

  1063. +  { "h-sys-gpr219", HW_H_SYS_GPR219, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1064. 

  1064. +  { "h-sys-gpr220", HW_H_SYS_GPR220, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1065. 

  1065. +  { "h-sys-gpr221", HW_H_SYS_GPR221, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1066. 

  1066. +  { "h-sys-gpr222", HW_H_SYS_GPR222, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1067. 

  1067. +  { "h-sys-gpr223", HW_H_SYS_GPR223, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1068. 

  1068. +  { "h-sys-gpr224", HW_H_SYS_GPR224, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1069. 

  1069. +  { "h-sys-gpr225", HW_H_SYS_GPR225, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1070. 

  1070. +  { "h-sys-gpr226", HW_H_SYS_GPR226, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1071. 

  1071. +  { "h-sys-gpr227", HW_H_SYS_GPR227, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1072. 

  1072. +  { "h-sys-gpr228", HW_H_SYS_GPR228, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1073. 

  1073. +  { "h-sys-gpr229", HW_H_SYS_GPR229, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1074. 

  1074. +  { "h-sys-gpr230", HW_H_SYS_GPR230, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1075. 

  1075. +  { "h-sys-gpr231", HW_H_SYS_GPR231, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1076. 

  1076. +  { "h-sys-gpr232", HW_H_SYS_GPR232, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1077. 

  1077. +  { "h-sys-gpr233", HW_H_SYS_GPR233, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1078. 

  1078. +  { "h-sys-gpr234", HW_H_SYS_GPR234, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1079. 

  1079. +  { "h-sys-gpr235", HW_H_SYS_GPR235, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1080. 

  1080. +  { "h-sys-gpr236", HW_H_SYS_GPR236, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1081. 

  1081. +  { "h-sys-gpr237", HW_H_SYS_GPR237, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1082. 

  1082. +  { "h-sys-gpr238", HW_H_SYS_GPR238, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1083. 

  1083. +  { "h-sys-gpr239", HW_H_SYS_GPR239, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1084. 

  1084. +  { "h-sys-gpr240", HW_H_SYS_GPR240, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1085. 

  1085. +  { "h-sys-gpr241", HW_H_SYS_GPR241, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1086. 

  1086. +  { "h-sys-gpr242", HW_H_SYS_GPR242, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1087. 

  1087. +  { "h-sys-gpr243", HW_H_SYS_GPR243, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1088. 

  1088. +  { "h-sys-gpr244", HW_H_SYS_GPR244, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1089. 

  1089. +  { "h-sys-gpr245", HW_H_SYS_GPR245, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1090. 

  1090. +  { "h-sys-gpr246", HW_H_SYS_GPR246, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1091. 

  1091. +  { "h-sys-gpr247", HW_H_SYS_GPR247, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1092. 

  1092. +  { "h-sys-gpr248", HW_H_SYS_GPR248, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1093. 

  1093. +  { "h-sys-gpr249", HW_H_SYS_GPR249, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1094. 

  1094. +  { "h-sys-gpr250", HW_H_SYS_GPR250, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1095. 

  1095. +  { "h-sys-gpr251", HW_H_SYS_GPR251, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1096. 

  1096. +  { "h-sys-gpr252", HW_H_SYS_GPR252, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1097. 

  1097. +  { "h-sys-gpr253", HW_H_SYS_GPR253, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1098. 

  1098. +  { "h-sys-gpr254", HW_H_SYS_GPR254, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1099. 

  1099. +  { "h-sys-gpr255", HW_H_SYS_GPR255, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1100. 

  1100. +  { "h-sys-gpr256", HW_H_SYS_GPR256, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1101. 

  1101. +  { "h-sys-gpr257", HW_H_SYS_GPR257, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1102. 

  1102. +  { "h-sys-gpr258", HW_H_SYS_GPR258, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1103. 

  1103. +  { "h-sys-gpr259", HW_H_SYS_GPR259, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1104. 

  1104. +  { "h-sys-gpr260", HW_H_SYS_GPR260, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1105. 

  1105. +  { "h-sys-gpr261", HW_H_SYS_GPR261, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1106. 

  1106. +  { "h-sys-gpr262", HW_H_SYS_GPR262, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1107. 

  1107. +  { "h-sys-gpr263", HW_H_SYS_GPR263, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1108. 

  1108. +  { "h-sys-gpr264", HW_H_SYS_GPR264, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1109. 

  1109. +  { "h-sys-gpr265", HW_H_SYS_GPR265, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1110. 

  1110. +  { "h-sys-gpr266", HW_H_SYS_GPR266, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1111. 

  1111. +  { "h-sys-gpr267", HW_H_SYS_GPR267, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1112. 

  1112. +  { "h-sys-gpr268", HW_H_SYS_GPR268, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1113. 

  1113. +  { "h-sys-gpr269", HW_H_SYS_GPR269, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1114. 

  1114. +  { "h-sys-gpr270", HW_H_SYS_GPR270, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1115. 

  1115. +  { "h-sys-gpr271", HW_H_SYS_GPR271, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1116. 

  1116. +  { "h-sys-gpr272", HW_H_SYS_GPR272, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1117. 

  1117. +  { "h-sys-gpr273", HW_H_SYS_GPR273, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1118. 

  1118. +  { "h-sys-gpr274", HW_H_SYS_GPR274, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1119. 

  1119. +  { "h-sys-gpr275", HW_H_SYS_GPR275, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1120. 

  1120. +  { "h-sys-gpr276", HW_H_SYS_GPR276, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1121. 

  1121. +  { "h-sys-gpr277", HW_H_SYS_GPR277, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1122. 

  1122. +  { "h-sys-gpr278", HW_H_SYS_GPR278, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1123. 

  1123. +  { "h-sys-gpr279", HW_H_SYS_GPR279, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1124. 

  1124. +  { "h-sys-gpr280", HW_H_SYS_GPR280, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1125. 

  1125. +  { "h-sys-gpr281", HW_H_SYS_GPR281, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1126. 

  1126. +  { "h-sys-gpr282", HW_H_SYS_GPR282, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1127. 

  1127. +  { "h-sys-gpr283", HW_H_SYS_GPR283, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1128. 

  1128. +  { "h-sys-gpr284", HW_H_SYS_GPR284, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1129. 

  1129. +  { "h-sys-gpr285", HW_H_SYS_GPR285, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1130. 

  1130. +  { "h-sys-gpr286", HW_H_SYS_GPR286, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1131. 

  1131. +  { "h-sys-gpr287", HW_H_SYS_GPR287, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1132. 

  1132. +  { "h-sys-gpr288", HW_H_SYS_GPR288, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1133. 

  1133. +  { "h-sys-gpr289", HW_H_SYS_GPR289, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1134. 

  1134. +  { "h-sys-gpr290", HW_H_SYS_GPR290, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1135. 

  1135. +  { "h-sys-gpr291", HW_H_SYS_GPR291, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1136. 

  1136. +  { "h-sys-gpr292", HW_H_SYS_GPR292, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1137. 

  1137. +  { "h-sys-gpr293", HW_H_SYS_GPR293, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1138. 

  1138. +  { "h-sys-gpr294", HW_H_SYS_GPR294, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1139. 

  1139. +  { "h-sys-gpr295", HW_H_SYS_GPR295, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1140. 

  1140. +  { "h-sys-gpr296", HW_H_SYS_GPR296, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1141. 

  1141. +  { "h-sys-gpr297", HW_H_SYS_GPR297, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1142. 

  1142. +  { "h-sys-gpr298", HW_H_SYS_GPR298, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1143. 

  1143. +  { "h-sys-gpr299", HW_H_SYS_GPR299, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1144. 

  1144. +  { "h-sys-gpr300", HW_H_SYS_GPR300, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1145. 

  1145. +  { "h-sys-gpr301", HW_H_SYS_GPR301, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1146. 

  1146. +  { "h-sys-gpr302", HW_H_SYS_GPR302, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1147. 

  1147. +  { "h-sys-gpr303", HW_H_SYS_GPR303, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1148. 

  1148. +  { "h-sys-gpr304", HW_H_SYS_GPR304, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1149. 

  1149. +  { "h-sys-gpr305", HW_H_SYS_GPR305, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1150. 

  1150. +  { "h-sys-gpr306", HW_H_SYS_GPR306, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1151. 

  1151. +  { "h-sys-gpr307", HW_H_SYS_GPR307, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1152. 

  1152. +  { "h-sys-gpr308", HW_H_SYS_GPR308, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1153. 

  1153. +  { "h-sys-gpr309", HW_H_SYS_GPR309, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1154. 

  1154. +  { "h-sys-gpr310", HW_H_SYS_GPR310, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1155. 

  1155. +  { "h-sys-gpr311", HW_H_SYS_GPR311, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1156. 

  1156. +  { "h-sys-gpr312", HW_H_SYS_GPR312, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1157. 

  1157. +  { "h-sys-gpr313", HW_H_SYS_GPR313, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1158. 

  1158. +  { "h-sys-gpr314", HW_H_SYS_GPR314, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1159. 

  1159. +  { "h-sys-gpr315", HW_H_SYS_GPR315, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1160. 

  1160. +  { "h-sys-gpr316", HW_H_SYS_GPR316, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1161. 

  1161. +  { "h-sys-gpr317", HW_H_SYS_GPR317, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1162. 

  1162. +  { "h-sys-gpr318", HW_H_SYS_GPR318, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1163. 

  1163. +  { "h-sys-gpr319", HW_H_SYS_GPR319, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1164. 

  1164. +  { "h-sys-gpr320", HW_H_SYS_GPR320, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1165. 

  1165. +  { "h-sys-gpr321", HW_H_SYS_GPR321, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1166. 

  1166. +  { "h-sys-gpr322", HW_H_SYS_GPR322, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1167. 

  1167. +  { "h-sys-gpr323", HW_H_SYS_GPR323, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1168. 

  1168. +  { "h-sys-gpr324", HW_H_SYS_GPR324, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1169. 

  1169. +  { "h-sys-gpr325", HW_H_SYS_GPR325, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1170. 

  1170. +  { "h-sys-gpr326", HW_H_SYS_GPR326, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1171. 

  1171. +  { "h-sys-gpr327", HW_H_SYS_GPR327, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1172. 

  1172. +  { "h-sys-gpr328", HW_H_SYS_GPR328, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1173. 

  1173. +  { "h-sys-gpr329", HW_H_SYS_GPR329, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1174. 

  1174. +  { "h-sys-gpr330", HW_H_SYS_GPR330, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1175. 

  1175. +  { "h-sys-gpr331", HW_H_SYS_GPR331, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1176. 

  1176. +  { "h-sys-gpr332", HW_H_SYS_GPR332, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1177. 

  1177. +  { "h-sys-gpr333", HW_H_SYS_GPR333, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1178. 

  1178. +  { "h-sys-gpr334", HW_H_SYS_GPR334, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1179. 

  1179. +  { "h-sys-gpr335", HW_H_SYS_GPR335, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1180. 

  1180. +  { "h-sys-gpr336", HW_H_SYS_GPR336, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1181. 

  1181. +  { "h-sys-gpr337", HW_H_SYS_GPR337, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1182. 

  1182. +  { "h-sys-gpr338", HW_H_SYS_GPR338, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1183. 

  1183. +  { "h-sys-gpr339", HW_H_SYS_GPR339, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1184. 

  1184. +  { "h-sys-gpr340", HW_H_SYS_GPR340, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1185. 

  1185. +  { "h-sys-gpr341", HW_H_SYS_GPR341, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1186. 

  1186. +  { "h-sys-gpr342", HW_H_SYS_GPR342, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1187. 

  1187. +  { "h-sys-gpr343", HW_H_SYS_GPR343, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1188. 

  1188. +  { "h-sys-gpr344", HW_H_SYS_GPR344, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1189. 

  1189. +  { "h-sys-gpr345", HW_H_SYS_GPR345, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1190. 

  1190. +  { "h-sys-gpr346", HW_H_SYS_GPR346, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1191. 

  1191. +  { "h-sys-gpr347", HW_H_SYS_GPR347, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1192. 

  1192. +  { "h-sys-gpr348", HW_H_SYS_GPR348, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1193. 

  1193. +  { "h-sys-gpr349", HW_H_SYS_GPR349, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1194. 

  1194. +  { "h-sys-gpr350", HW_H_SYS_GPR350, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1195. 

  1195. +  { "h-sys-gpr351", HW_H_SYS_GPR351, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1196. 

  1196. +  { "h-sys-gpr352", HW_H_SYS_GPR352, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1197. 

  1197. +  { "h-sys-gpr353", HW_H_SYS_GPR353, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1198. 

  1198. +  { "h-sys-gpr354", HW_H_SYS_GPR354, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1199. 

  1199. +  { "h-sys-gpr355", HW_H_SYS_GPR355, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1200. 

  1200. +  { "h-sys-gpr356", HW_H_SYS_GPR356, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1201. 

  1201. +  { "h-sys-gpr357", HW_H_SYS_GPR357, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1202. 

  1202. +  { "h-sys-gpr358", HW_H_SYS_GPR358, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1203. 

  1203. +  { "h-sys-gpr359", HW_H_SYS_GPR359, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1204. 

  1204. +  { "h-sys-gpr360", HW_H_SYS_GPR360, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1205. 

  1205. +  { "h-sys-gpr361", HW_H_SYS_GPR361, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1206. 

  1206. +  { "h-sys-gpr362", HW_H_SYS_GPR362, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1207. 

  1207. +  { "h-sys-gpr363", HW_H_SYS_GPR363, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1208. 

  1208. +  { "h-sys-gpr364", HW_H_SYS_GPR364, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1209. 

  1209. +  { "h-sys-gpr365", HW_H_SYS_GPR365, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1210. 

  1210. +  { "h-sys-gpr366", HW_H_SYS_GPR366, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1211. 

  1211. +  { "h-sys-gpr367", HW_H_SYS_GPR367, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1212. 

  1212. +  { "h-sys-gpr368", HW_H_SYS_GPR368, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1213. 

  1213. +  { "h-sys-gpr369", HW_H_SYS_GPR369, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1214. 

  1214. +  { "h-sys-gpr370", HW_H_SYS_GPR370, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1215. 

  1215. +  { "h-sys-gpr371", HW_H_SYS_GPR371, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1216. 

  1216. +  { "h-sys-gpr372", HW_H_SYS_GPR372, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1217. 

  1217. +  { "h-sys-gpr373", HW_H_SYS_GPR373, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1218. 

  1218. +  { "h-sys-gpr374", HW_H_SYS_GPR374, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1219. 

  1219. +  { "h-sys-gpr375", HW_H_SYS_GPR375, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1220. 

  1220. +  { "h-sys-gpr376", HW_H_SYS_GPR376, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1221. 

  1221. +  { "h-sys-gpr377", HW_H_SYS_GPR377, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1222. 

  1222. +  { "h-sys-gpr378", HW_H_SYS_GPR378, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1223. 

  1223. +  { "h-sys-gpr379", HW_H_SYS_GPR379, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1224. 

  1224. +  { "h-sys-gpr380", HW_H_SYS_GPR380, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1225. 

  1225. +  { "h-sys-gpr381", HW_H_SYS_GPR381, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1226. 

  1226. +  { "h-sys-gpr382", HW_H_SYS_GPR382, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1227. 

  1227. +  { "h-sys-gpr383", HW_H_SYS_GPR383, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1228. 

  1228. +  { "h-sys-gpr384", HW_H_SYS_GPR384, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1229. 

  1229. +  { "h-sys-gpr385", HW_H_SYS_GPR385, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1230. 

  1230. +  { "h-sys-gpr386", HW_H_SYS_GPR386, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1231. 

  1231. +  { "h-sys-gpr387", HW_H_SYS_GPR387, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1232. 

  1232. +  { "h-sys-gpr388", HW_H_SYS_GPR388, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1233. 

  1233. +  { "h-sys-gpr389", HW_H_SYS_GPR389, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1234. 

  1234. +  { "h-sys-gpr390", HW_H_SYS_GPR390, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1235. 

  1235. +  { "h-sys-gpr391", HW_H_SYS_GPR391, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1236. 

  1236. +  { "h-sys-gpr392", HW_H_SYS_GPR392, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1237. 

  1237. +  { "h-sys-gpr393", HW_H_SYS_GPR393, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1238. 

  1238. +  { "h-sys-gpr394", HW_H_SYS_GPR394, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1239. 

  1239. +  { "h-sys-gpr395", HW_H_SYS_GPR395, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1240. 

  1240. +  { "h-sys-gpr396", HW_H_SYS_GPR396, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1241. 

  1241. +  { "h-sys-gpr397", HW_H_SYS_GPR397, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1242. 

  1242. +  { "h-sys-gpr398", HW_H_SYS_GPR398, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1243. 

  1243. +  { "h-sys-gpr399", HW_H_SYS_GPR399, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1244. 

  1244. +  { "h-sys-gpr400", HW_H_SYS_GPR400, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1245. 

  1245. +  { "h-sys-gpr401", HW_H_SYS_GPR401, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1246. 

  1246. +  { "h-sys-gpr402", HW_H_SYS_GPR402, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1247. 

  1247. +  { "h-sys-gpr403", HW_H_SYS_GPR403, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1248. 

  1248. +  { "h-sys-gpr404", HW_H_SYS_GPR404, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1249. 

  1249. +  { "h-sys-gpr405", HW_H_SYS_GPR405, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1250. 

  1250. +  { "h-sys-gpr406", HW_H_SYS_GPR406, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1251. 

  1251. +  { "h-sys-gpr407", HW_H_SYS_GPR407, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1252. 

  1252. +  { "h-sys-gpr408", HW_H_SYS_GPR408, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1253. 

  1253. +  { "h-sys-gpr409", HW_H_SYS_GPR409, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1254. 

  1254. +  { "h-sys-gpr410", HW_H_SYS_GPR410, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1255. 

  1255. +  { "h-sys-gpr411", HW_H_SYS_GPR411, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1256. 

  1256. +  { "h-sys-gpr412", HW_H_SYS_GPR412, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1257. 

  1257. +  { "h-sys-gpr413", HW_H_SYS_GPR413, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1258. 

  1258. +  { "h-sys-gpr414", HW_H_SYS_GPR414, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1259. 

  1259. +  { "h-sys-gpr415", HW_H_SYS_GPR415, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1260. 

  1260. +  { "h-sys-gpr416", HW_H_SYS_GPR416, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1261. 

  1261. +  { "h-sys-gpr417", HW_H_SYS_GPR417, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1262. 

  1262. +  { "h-sys-gpr418", HW_H_SYS_GPR418, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1263. 

  1263. +  { "h-sys-gpr419", HW_H_SYS_GPR419, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1264. 

  1264. +  { "h-sys-gpr420", HW_H_SYS_GPR420, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1265. 

  1265. +  { "h-sys-gpr421", HW_H_SYS_GPR421, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1266. 

  1266. +  { "h-sys-gpr422", HW_H_SYS_GPR422, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1267. 

  1267. +  { "h-sys-gpr423", HW_H_SYS_GPR423, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1268. 

  1268. +  { "h-sys-gpr424", HW_H_SYS_GPR424, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1269. 

  1269. +  { "h-sys-gpr425", HW_H_SYS_GPR425, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1270. 

  1270. +  { "h-sys-gpr426", HW_H_SYS_GPR426, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1271. 

  1271. +  { "h-sys-gpr427", HW_H_SYS_GPR427, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1272. 

  1272. +  { "h-sys-gpr428", HW_H_SYS_GPR428, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1273. 

  1273. +  { "h-sys-gpr429", HW_H_SYS_GPR429, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1274. 

  1274. +  { "h-sys-gpr430", HW_H_SYS_GPR430, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1275. 

  1275. +  { "h-sys-gpr431", HW_H_SYS_GPR431, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1276. 

  1276. +  { "h-sys-gpr432", HW_H_SYS_GPR432, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1277. 

  1277. +  { "h-sys-gpr433", HW_H_SYS_GPR433, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1278. 

  1278. +  { "h-sys-gpr434", HW_H_SYS_GPR434, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1279. 

  1279. +  { "h-sys-gpr435", HW_H_SYS_GPR435, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1280. 

  1280. +  { "h-sys-gpr436", HW_H_SYS_GPR436, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1281. 

  1281. +  { "h-sys-gpr437", HW_H_SYS_GPR437, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1282. 

  1282. +  { "h-sys-gpr438", HW_H_SYS_GPR438, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1283. 

  1283. +  { "h-sys-gpr439", HW_H_SYS_GPR439, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1284. 

  1284. +  { "h-sys-gpr440", HW_H_SYS_GPR440, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1285. 

  1285. +  { "h-sys-gpr441", HW_H_SYS_GPR441, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1286. 

  1286. +  { "h-sys-gpr442", HW_H_SYS_GPR442, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1287. 

  1287. +  { "h-sys-gpr443", HW_H_SYS_GPR443, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1288. 

  1288. +  { "h-sys-gpr444", HW_H_SYS_GPR444, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1289. 

  1289. +  { "h-sys-gpr445", HW_H_SYS_GPR445, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1290. 

  1290. +  { "h-sys-gpr446", HW_H_SYS_GPR446, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1291. 

  1291. +  { "h-sys-gpr447", HW_H_SYS_GPR447, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1292. 

  1292. +  { "h-sys-gpr448", HW_H_SYS_GPR448, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1293. 

  1293. +  { "h-sys-gpr449", HW_H_SYS_GPR449, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1294. 

  1294. +  { "h-sys-gpr450", HW_H_SYS_GPR450, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1295. 

  1295. +  { "h-sys-gpr451", HW_H_SYS_GPR451, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1296. 

  1296. +  { "h-sys-gpr452", HW_H_SYS_GPR452, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1297. 

  1297. +  { "h-sys-gpr453", HW_H_SYS_GPR453, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1298. 

  1298. +  { "h-sys-gpr454", HW_H_SYS_GPR454, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1299. 

  1299. +  { "h-sys-gpr455", HW_H_SYS_GPR455, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1300. 

  1300. +  { "h-sys-gpr456", HW_H_SYS_GPR456, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1301. 

  1301. +  { "h-sys-gpr457", HW_H_SYS_GPR457, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1302. 

  1302. +  { "h-sys-gpr458", HW_H_SYS_GPR458, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1303. 

  1303. +  { "h-sys-gpr459", HW_H_SYS_GPR459, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1304. 

  1304. +  { "h-sys-gpr460", HW_H_SYS_GPR460, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1305. 

  1305. +  { "h-sys-gpr461", HW_H_SYS_GPR461, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1306. 

  1306. +  { "h-sys-gpr462", HW_H_SYS_GPR462, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1307. 

  1307. +  { "h-sys-gpr463", HW_H_SYS_GPR463, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1308. 

  1308. +  { "h-sys-gpr464", HW_H_SYS_GPR464, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1309. 

  1309. +  { "h-sys-gpr465", HW_H_SYS_GPR465, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1310. 

  1310. +  { "h-sys-gpr466", HW_H_SYS_GPR466, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1311. 

  1311. +  { "h-sys-gpr467", HW_H_SYS_GPR467, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1312. 

  1312. +  { "h-sys-gpr468", HW_H_SYS_GPR468, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1313. 

  1313. +  { "h-sys-gpr469", HW_H_SYS_GPR469, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1314. 

  1314. +  { "h-sys-gpr470", HW_H_SYS_GPR470, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1315. 

  1315. +  { "h-sys-gpr471", HW_H_SYS_GPR471, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1316. 

  1316. +  { "h-sys-gpr472", HW_H_SYS_GPR472, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1317. 

  1317. +  { "h-sys-gpr473", HW_H_SYS_GPR473, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1318. 

  1318. +  { "h-sys-gpr474", HW_H_SYS_GPR474, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1319. 

  1319. +  { "h-sys-gpr475", HW_H_SYS_GPR475, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1320. 

  1320. +  { "h-sys-gpr476", HW_H_SYS_GPR476, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1321. 

  1321. +  { "h-sys-gpr477", HW_H_SYS_GPR477, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1322. 

  1322. +  { "h-sys-gpr478", HW_H_SYS_GPR478, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1323. 

  1323. +  { "h-sys-gpr479", HW_H_SYS_GPR479, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1324. 

  1324. +  { "h-sys-gpr480", HW_H_SYS_GPR480, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1325. 

  1325. +  { "h-sys-gpr481", HW_H_SYS_GPR481, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1326. 

  1326. +  { "h-sys-gpr482", HW_H_SYS_GPR482, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1327. 

  1327. +  { "h-sys-gpr483", HW_H_SYS_GPR483, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1328. 

  1328. +  { "h-sys-gpr484", HW_H_SYS_GPR484, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1329. 

  1329. +  { "h-sys-gpr485", HW_H_SYS_GPR485, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1330. 

  1330. +  { "h-sys-gpr486", HW_H_SYS_GPR486, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1331. 

  1331. +  { "h-sys-gpr487", HW_H_SYS_GPR487, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1332. 

  1332. +  { "h-sys-gpr488", HW_H_SYS_GPR488, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1333. 

  1333. +  { "h-sys-gpr489", HW_H_SYS_GPR489, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1334. 

  1334. +  { "h-sys-gpr490", HW_H_SYS_GPR490, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1335. 

  1335. +  { "h-sys-gpr491", HW_H_SYS_GPR491, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1336. 

  1336. +  { "h-sys-gpr492", HW_H_SYS_GPR492, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1337. 

  1337. +  { "h-sys-gpr493", HW_H_SYS_GPR493, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1338. 

  1338. +  { "h-sys-gpr494", HW_H_SYS_GPR494, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1339. 

  1339. +  { "h-sys-gpr495", HW_H_SYS_GPR495, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1340. 

  1340. +  { "h-sys-gpr496", HW_H_SYS_GPR496, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1341. 

  1341. +  { "h-sys-gpr497", HW_H_SYS_GPR497, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1342. 

  1342. +  { "h-sys-gpr498", HW_H_SYS_GPR498, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1343. 

  1343. +  { "h-sys-gpr499", HW_H_SYS_GPR499, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1344. 

  1344. +  { "h-sys-gpr500", HW_H_SYS_GPR500, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1345. 

  1345. +  { "h-sys-gpr501", HW_H_SYS_GPR501, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1346. 

  1346. +  { "h-sys-gpr502", HW_H_SYS_GPR502, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1347. 

  1347. +  { "h-sys-gpr503", HW_H_SYS_GPR503, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1348. 

  1348. +  { "h-sys-gpr504", HW_H_SYS_GPR504, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1349. 

  1349. +  { "h-sys-gpr505", HW_H_SYS_GPR505, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1350. 

  1350. +  { "h-sys-gpr506", HW_H_SYS_GPR506, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1351. 

  1351. +  { "h-sys-gpr507", HW_H_SYS_GPR507, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1352. 

  1352. +  { "h-sys-gpr508", HW_H_SYS_GPR508, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1353. 

  1353. +  { "h-sys-gpr509", HW_H_SYS_GPR509, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1354. 

  1354. +  { "h-sys-gpr510", HW_H_SYS_GPR510, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1355. 

  1355. +  { "h-sys-gpr511", HW_H_SYS_GPR511, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1356. 

  1356. +  { "h-mac-maclo", HW_H_MAC_MACLO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1357. 

  1357. +  { "h-mac-machi", HW_H_MAC_MACHI, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1358. 

  1358. +  { "h-tick-ttmr", HW_H_TICK_TTMR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1359. 

  1359. +  { "h-sys-vr-rev", HW_H_SYS_VR_REV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1360. 

  1360. +  { "h-sys-vr-cfg", HW_H_SYS_VR_CFG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1361. 

  1361. +  { "h-sys-vr-ver", HW_H_SYS_VR_VER, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1362. 

  1362. +  { "h-sys-upr-up", HW_H_SYS_UPR_UP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1363. 

  1363. +  { "h-sys-upr-dcp", HW_H_SYS_UPR_DCP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1364. 

  1364. +  { "h-sys-upr-icp", HW_H_SYS_UPR_ICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1365. 

  1365. +  { "h-sys-upr-dmp", HW_H_SYS_UPR_DMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1366. 

  1366. +  { "h-sys-upr-mp", HW_H_SYS_UPR_MP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1367. 

  1367. +  { "h-sys-upr-imp", HW_H_SYS_UPR_IMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1368. 

  1368. +  { "h-sys-upr-dup", HW_H_SYS_UPR_DUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1369. 

  1369. +  { "h-sys-upr-pcup", HW_H_SYS_UPR_PCUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1370. 

  1370. +  { "h-sys-upr-picp", HW_H_SYS_UPR_PICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1371. 

  1371. +  { "h-sys-upr-pmp", HW_H_SYS_UPR_PMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1372. 

  1372. +  { "h-sys-upr-ttp", HW_H_SYS_UPR_TTP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1373. 

  1373. +  { "h-sys-upr-cup", HW_H_SYS_UPR_CUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1374. 

  1374. +  { "h-sys-cpucfgr-nsgr", HW_H_SYS_CPUCFGR_NSGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1375. 

  1375. +  { "h-sys-cpucfgr-cgf", HW_H_SYS_CPUCFGR_CGF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1376. 

  1376. +  { "h-sys-cpucfgr-ob32s", HW_H_SYS_CPUCFGR_OB32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1377. 

  1377. +  { "h-sys-cpucfgr-ob64s", HW_H_SYS_CPUCFGR_OB64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1378. 

  1378. +  { "h-sys-cpucfgr-of32s", HW_H_SYS_CPUCFGR_OF32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1379. 

  1379. +  { "h-sys-cpucfgr-of64s", HW_H_SYS_CPUCFGR_OF64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1380. 

  1380. +  { "h-sys-cpucfgr-ov64s", HW_H_SYS_CPUCFGR_OV64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1381. 

  1381. +  { "h-sys-cpucfgr-nd", HW_H_SYS_CPUCFGR_ND, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1382. 

  1382. +  { "h-sys-sr-sm", HW_H_SYS_SR_SM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1383. 

  1383. +  { "h-sys-sr-tee", HW_H_SYS_SR_TEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1384. 

  1384. +  { "h-sys-sr-iee", HW_H_SYS_SR_IEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1385. 

  1385. +  { "h-sys-sr-dce", HW_H_SYS_SR_DCE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1386. 

  1386. +  { "h-sys-sr-ice", HW_H_SYS_SR_ICE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1387. 

  1387. +  { "h-sys-sr-dme", HW_H_SYS_SR_DME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1388. 

  1388. +  { "h-sys-sr-ime", HW_H_SYS_SR_IME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1389. 

  1389. +  { "h-sys-sr-lee", HW_H_SYS_SR_LEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1390. 

  1390. +  { "h-sys-sr-ce", HW_H_SYS_SR_CE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1391. 

  1391. +  { "h-sys-sr-f", HW_H_SYS_SR_F, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1392. 

  1392. +  { "h-sys-sr-cy", HW_H_SYS_SR_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1393. 

  1393. +  { "h-sys-sr-ov", HW_H_SYS_SR_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1394. 

  1394. +  { "h-sys-sr-ove", HW_H_SYS_SR_OVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1395. 

  1395. +  { "h-sys-sr-dsx", HW_H_SYS_SR_DSX, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1396. 

  1396. +  { "h-sys-sr-eph", HW_H_SYS_SR_EPH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1397. 

  1397. +  { "h-sys-sr-fo", HW_H_SYS_SR_FO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1398. 

  1398. +  { "h-sys-sr-sumra", HW_H_SYS_SR_SUMRA, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1399. 

  1399. +  { "h-sys-sr-cid", HW_H_SYS_SR_CID, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1400. 

  1400. +  { "h-sys-fpcsr-fpee", HW_H_SYS_FPCSR_FPEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1401. 

  1401. +  { "h-sys-fpcsr-rm", HW_H_SYS_FPCSR_RM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1402. 

  1402. +  { "h-sys-fpcsr-ovf", HW_H_SYS_FPCSR_OVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1403. 

  1403. +  { "h-sys-fpcsr-unf", HW_H_SYS_FPCSR_UNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1404. 

  1404. +  { "h-sys-fpcsr-snf", HW_H_SYS_FPCSR_SNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1405. 

  1405. +  { "h-sys-fpcsr-qnf", HW_H_SYS_FPCSR_QNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1406. 

  1406. +  { "h-sys-fpcsr-zf", HW_H_SYS_FPCSR_ZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1407. 

  1407. +  { "h-sys-fpcsr-ixf", HW_H_SYS_FPCSR_IXF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1408. 

  1408. +  { "h-sys-fpcsr-ivf", HW_H_SYS_FPCSR_IVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1409. 

  1409. +  { "h-sys-fpcsr-inf", HW_H_SYS_FPCSR_INF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1410. 

  1410. +  { "h-sys-fpcsr-dzf", HW_H_SYS_FPCSR_DZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1411. 

  1411. +  { "h-simm16", HW_H_SIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
    1412. 

  1412.    { "h-uimm16", HW_H_UIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    1413. 

  1413.    { "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    1414. 

  1414.    { "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    1415. 

  1415. @@ -939,44 +888,44 @@ const CGEN_IFLD or1k_cgen_ifld_table[] =
    1416. 

  1416.  {
    1417. 

  1417.    { OR1K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    1418. 

  1418.    { OR1K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    1419. 

  1419. -  { OR1K_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1420. 

  1420. -  { OR1K_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1421. 

  1421. -  { OR1K_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1422. 

  1422. -  { OR1K_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1423. 

  1423. -  { OR1K_F_OP_25_2, "f-op-25-2", 0, 32, 25, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1424. 

  1424. -  { OR1K_F_OP_25_5, "f-op-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1425. 

  1425. -  { OR1K_F_OP_16_1, "f-op-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1426. 

  1426. -  { OR1K_F_OP_7_4, "f-op-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1427. 

  1427. -  { OR1K_F_OP_3_4, "f-op-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1428. 

  1428. -  { OR1K_F_OP_9_2, "f-op-9-2", 0, 32, 9, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1429. 

  1429. -  { OR1K_F_OP_9_4, "f-op-9-4", 0, 32, 9, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1430. 

  1430. -  { OR1K_F_OP_7_8, "f-op-7-8", 0, 32, 7, 8, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1431. 

  1431. -  { OR1K_F_OP_7_2, "f-op-7-2", 0, 32, 7, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1432. 

  1432. -  { OR1K_F_RESV_25_26, "f-resv-25-26", 0, 32, 25, 26, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1433. 

  1433. -  { OR1K_F_RESV_25_10, "f-resv-25-10", 0, 32, 25, 10, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1434. 

  1434. -  { OR1K_F_RESV_25_5, "f-resv-25-5", 0, 32, 25, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1435. 

  1435. -  { OR1K_F_RESV_23_8, "f-resv-23-8", 0, 32, 23, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1436. 

  1436. -  { OR1K_F_RESV_20_21, "f-resv-20-21", 0, 32, 20, 21, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1437. 

  1437. -  { OR1K_F_RESV_20_5, "f-resv-20-5", 0, 32, 20, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1438. 

  1438. -  { OR1K_F_RESV_20_4, "f-resv-20-4", 0, 32, 20, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1439. 

  1439. -  { OR1K_F_RESV_15_8, "f-resv-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1440. 

  1440. -  { OR1K_F_RESV_15_6, "f-resv-15-6", 0, 32, 15, 6, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1441. 

  1441. -  { OR1K_F_RESV_10_11, "f-resv-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1442. 

  1442. -  { OR1K_F_RESV_10_7, "f-resv-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1443. 

  1443. -  { OR1K_F_RESV_10_3, "f-resv-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1444. 

  1444. -  { OR1K_F_RESV_10_1, "f-resv-10-1", 0, 32, 10, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1445. 

  1445. -  { OR1K_F_RESV_8_1, "f-resv-8-1", 0, 32, 8, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1446. 

  1446. -  { OR1K_F_RESV_7_4, "f-resv-7-4", 0, 32, 7, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1447. 

  1447. -  { OR1K_F_RESV_5_2, "f-resv-5-2", 0, 32, 5, 2, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1448. 

  1448. -  { OR1K_F_IMM16_25_5, "f-imm16-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1449. 

  1449. -  { OR1K_F_IMM16_10_11, "f-imm16-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1450. 

  1450. -  { OR1K_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1451. 

  1451. -  { OR1K_F_DISP21, "f-disp21", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1452. 

  1452. -  { OR1K_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1453. 

  1453. -  { OR1K_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1454. 

  1454. -  { OR1K_F_UIMM6, "f-uimm6", 0, 32, 5, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1455. 

  1455. -  { OR1K_F_UIMM16_SPLIT, "f-uimm16-split", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1456. 

  1456. -  { OR1K_F_SIMM16_SPLIT, "f-simm16-split", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1457. 

  1457. +  { OR1K_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1458. 

  1458. +  { OR1K_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1459. 

  1459. +  { OR1K_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1460. 

  1460. +  { OR1K_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1461. 

  1461. +  { OR1K_F_OP_25_2, "f-op-25-2", 0, 32, 25, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1462. 

  1462. +  { OR1K_F_OP_25_5, "f-op-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1463. 

  1463. +  { OR1K_F_OP_16_1, "f-op-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1464. 

  1464. +  { OR1K_F_OP_7_4, "f-op-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1465. 

  1465. +  { OR1K_F_OP_3_4, "f-op-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1466. 

  1466. +  { OR1K_F_OP_9_2, "f-op-9-2", 0, 32, 9, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1467. 

  1467. +  { OR1K_F_OP_9_4, "f-op-9-4", 0, 32, 9, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1468. 

  1468. +  { OR1K_F_OP_7_8, "f-op-7-8", 0, 32, 7, 8, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1469. 

  1469. +  { OR1K_F_OP_7_2, "f-op-7-2", 0, 32, 7, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1470. 

  1470. +  { OR1K_F_RESV_25_26, "f-resv-25-26", 0, 32, 25, 26, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1471. 

  1471. +  { OR1K_F_RESV_25_10, "f-resv-25-10", 0, 32, 25, 10, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1472. 

  1472. +  { OR1K_F_RESV_25_5, "f-resv-25-5", 0, 32, 25, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1473. 

  1473. +  { OR1K_F_RESV_23_8, "f-resv-23-8", 0, 32, 23, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1474. 

  1474. +  { OR1K_F_RESV_20_21, "f-resv-20-21", 0, 32, 20, 21, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1475. 

  1475. +  { OR1K_F_RESV_20_5, "f-resv-20-5", 0, 32, 20, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1476. 

  1476. +  { OR1K_F_RESV_20_4, "f-resv-20-4", 0, 32, 20, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1477. 

  1477. +  { OR1K_F_RESV_15_8, "f-resv-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1478. 

  1478. +  { OR1K_F_RESV_15_6, "f-resv-15-6", 0, 32, 15, 6, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1479. 

  1479. +  { OR1K_F_RESV_10_11, "f-resv-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1480. 

  1480. +  { OR1K_F_RESV_10_7, "f-resv-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1481. 

  1481. +  { OR1K_F_RESV_10_3, "f-resv-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1482. 

  1482. +  { OR1K_F_RESV_10_1, "f-resv-10-1", 0, 32, 10, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1483. 

  1483. +  { OR1K_F_RESV_8_1, "f-resv-8-1", 0, 32, 8, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1484. 

  1484. +  { OR1K_F_RESV_7_4, "f-resv-7-4", 0, 32, 7, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1485. 

  1485. +  { OR1K_F_RESV_5_2, "f-resv-5-2", 0, 32, 5, 2, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1486. 

  1486. +  { OR1K_F_IMM16_25_5, "f-imm16-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1487. 

  1487. +  { OR1K_F_IMM16_10_11, "f-imm16-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1488. 

  1488. +  { OR1K_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1489. 

  1489. +  { OR1K_F_DISP21, "f-disp21", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1490. 

  1490. +  { OR1K_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1491. 

  1491. +  { OR1K_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1492. 

  1492. +  { OR1K_F_UIMM6, "f-uimm6", 0, 32, 5, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1493. 

  1493. +  { OR1K_F_UIMM16_SPLIT, "f-uimm16-split", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1494. 

  1494. +  { OR1K_F_SIMM16_SPLIT, "f-simm16-split", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1495. 

  1495.    { OR1K_F_RDOFF_10_1, "f-rdoff-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1496. 

  1496.    { OR1K_F_RAOFF_9_1, "f-raoff-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1497. 

  1497.    { OR1K_F_RBOFF_8_1, "f-rboff-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1498. 

  1498. @@ -1046,127 +995,115 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
    1499. 

  1499.  /* sys-sr: supervision register */
    1500. 

  1500.    { "sys-sr", OR1K_OPERAND_SYS_SR, HW_H_SYS_SR, 0, 0,
    1501. 

  1501.      { 0, { (const PTR) 0 } },
    1502. 

  1502. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1503. 

  1503. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1504. 

  1504.  /* sys-esr0: exception supervision register 0 */
    1505. 

  1505.    { "sys-esr0", OR1K_OPERAND_SYS_ESR0, HW_H_SYS_ESR0, 0, 0,
    1506. 

  1506.      { 0, { (const PTR) 0 } },
    1507. 

  1507. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1508. 

  1508. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1509. 

  1509.  /* sys-epcr0: exception PC register 0 */
    1510. 

  1510.    { "sys-epcr0", OR1K_OPERAND_SYS_EPCR0, HW_H_SYS_EPCR0, 0, 0,
    1511. 

  1511.      { 0, { (const PTR) 0 } },
    1512. 

  1512. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1513. 

  1513. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1514. 

  1514.  /* sys-sr-lee: SR little endian enable bit */
    1515. 

  1515.    { "sys-sr-lee", OR1K_OPERAND_SYS_SR_LEE, HW_H_SYS_SR_LEE, 0, 0,
    1516. 

  1516.      { 0, { (const PTR) 0 } },
    1517. 

  1517. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1518. 

  1518. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1519. 

  1519.  /* sys-sr-f: SR flag bit */
    1520. 

  1520.    { "sys-sr-f", OR1K_OPERAND_SYS_SR_F, HW_H_SYS_SR_F, 0, 0,
    1521. 

  1521.      { 0, { (const PTR) 0 } },
    1522. 

  1522. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1523. 

  1523. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1524. 

  1524.  /* sys-sr-cy: SR carry bit */
    1525. 

  1525.    { "sys-sr-cy", OR1K_OPERAND_SYS_SR_CY, HW_H_SYS_SR_CY, 0, 0,
    1526. 

  1526.      { 0, { (const PTR) 0 } },
    1527. 

  1527. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1528. 

  1528. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1529. 

  1529.  /* sys-sr-ov: SR overflow bit */
    1530. 

  1530.    { "sys-sr-ov", OR1K_OPERAND_SYS_SR_OV, HW_H_SYS_SR_OV, 0, 0,
    1531. 

  1531.      { 0, { (const PTR) 0 } },
    1532. 

  1532. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1533. 

  1533. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1534. 

  1534.  /* sys-sr-ove: SR overflow exception enable bit */
    1535. 

  1535.    { "sys-sr-ove", OR1K_OPERAND_SYS_SR_OVE, HW_H_SYS_SR_OVE, 0, 0,
    1536. 

  1536.      { 0, { (const PTR) 0 } },
    1537. 

  1537. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1538. 

  1538. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1539. 

  1539.  /* sys-cpucfgr-ob64s: CPUCFGR ORBIS64 supported bit */
    1540. 

  1540.    { "sys-cpucfgr-ob64s", OR1K_OPERAND_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OB64S, 0, 0,
    1541. 

  1541.      { 0, { (const PTR) 0 } },
    1542. 

  1542. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1543. 

  1543. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1544. 

  1544.  /* sys-cpucfgr-nd: CPUCFGR no delay bit */
    1545. 

  1545.    { "sys-cpucfgr-nd", OR1K_OPERAND_SYS_CPUCFGR_ND, HW_H_SYS_CPUCFGR_ND, 0, 0,
    1546. 

  1546.      { 0, { (const PTR) 0 } },
    1547. 

  1547. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1548. 

  1548. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1549. 

  1549.  /* sys-fpcsr-rm: floating point round mode */
    1550. 

  1550.    { "sys-fpcsr-rm", OR1K_OPERAND_SYS_FPCSR_RM, HW_H_SYS_FPCSR_RM, 0, 0,
    1551. 

  1551.      { 0, { (const PTR) 0 } },
    1552. 

  1552. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1553. 

  1553. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1554. 

  1554.  /* mac-machi: MAC HI result register */
    1555. 

  1555.    { "mac-machi", OR1K_OPERAND_MAC_MACHI, HW_H_MAC_MACHI, 0, 0,
    1556. 

  1556.      { 0, { (const PTR) 0 } },
    1557. 

  1557. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1558. 

  1558. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1559. 

  1559.  /* mac-maclo: MAC LO result register */
    1560. 

  1560.    { "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
    1561. 

  1561.      { 0, { (const PTR) 0 } },
    1562. 

  1562. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1563. 

  1563. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1564. 

  1564.  /* atomic-reserve: atomic reserve flag */
    1565. 

  1565.    { "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
    1566. 

  1566.      { 0, { (const PTR) 0 } },
    1567. 

  1567. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1568. 

  1568. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1569. 

  1569.  /* atomic-address: atomic address */
    1570. 

  1570.    { "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
    1571. 

  1571.      { 0, { (const PTR) 0 } },
    1572. 

  1572. -    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1573. 

  1573. +    { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1574. 

  1574.  /* uimm6: uimm6 */
    1575. 

  1575.    { "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
    1576. 

  1576.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
    1577. 

  1577. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1578. 

  1578. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1579. 

  1579.  /* rD: destination register */
    1580. 

  1580.    { "rD", OR1K_OPERAND_RD, HW_H_GPR, 25, 5,
    1581. 

  1581.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1582. 

  1582. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1583. 

  1583. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1584. 

  1584.  /* rA: source register A */
    1585. 

  1585.    { "rA", OR1K_OPERAND_RA, HW_H_GPR, 20, 5,
    1586. 

  1586.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
    1587. 

  1587. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1588. 

  1588. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1589. 

  1589.  /* rB: source register B */
    1590. 

  1590.    { "rB", OR1K_OPERAND_RB, HW_H_GPR, 15, 5,
    1591. 

  1591.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
    1592. 

  1592. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1593. 

  1593. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1594. 

  1594.  /* disp26: pc-rel 26 bit */
    1595. 

  1595.    { "disp26", OR1K_OPERAND_DISP26, HW_H_IADDR, 25, 26,
    1596. 

  1596.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
    1597. 

  1597. -    { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1598. 

  1598. +    { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1599. 

  1599.  /* disp21: pc-rel 21 bit */
    1600. 

  1600.    { "disp21", OR1K_OPERAND_DISP21, HW_H_IADDR, 20, 21,
    1601. 

  1601.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP21] } },
    1602. 

  1602. -    { 0|A(ABS_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1603. 

  1603. +    { 0|A(ABS_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1604. 

  1604.  /* simm16: 16-bit signed immediate */
    1605. 

  1605.    { "simm16", OR1K_OPERAND_SIMM16, HW_H_SIMM16, 15, 16,
    1606. 

  1606.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
    1607. 

  1607. -    { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1608. 

  1608. +    { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1609. 

  1609.  /* uimm16: 16-bit unsigned immediate */
    1610. 

  1610.    { "uimm16", OR1K_OPERAND_UIMM16, HW_H_UIMM16, 15, 16,
    1611. 

  1611.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
    1612. 

  1612. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1613. 

  1613. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1614. 

  1614.  /* simm16-split: split 16-bit signed immediate */
    1615. 

  1615.    { "simm16-split", OR1K_OPERAND_SIMM16_SPLIT, HW_H_SIMM16, 10, 16,
    1616. 

  1616.      { 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
    1617. 

  1617. -    { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1618. 

  1618. +    { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1619. 

  1619.  /* uimm16-split: split 16-bit unsigned immediate */
    1620. 

  1620.    { "uimm16-split", OR1K_OPERAND_UIMM16_SPLIT, HW_H_UIMM16, 10, 16,
    1621. 

  1621.      { 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
    1622. 

  1622. -    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1623. 

  1623. +    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1624. 

  1624.  /* rDSF: destination register (single floating point mode) */
    1625. 

  1625.    { "rDSF", OR1K_OPERAND_RDSF, HW_H_FSR, 25, 5,
    1626. 

  1626.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1627. 

  1627. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1628. 

  1628. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1629. 

  1629.  /* rASF: source register A (single floating point mode) */
    1630. 

  1630.    { "rASF", OR1K_OPERAND_RASF, HW_H_FSR, 20, 5,
    1631. 

  1631.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
    1632. 

  1632. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1633. 

  1633. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1634. 

  1634.  /* rBSF: source register B (single floating point mode) */
    1635. 

  1635.    { "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
    1636. 

  1636.      { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
    1637. 

  1637. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1638. 

  1638. -/* rDDF: or64 destination register (double floating point mode) */
    1639. 

  1639. -  { "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5,
    1640. 

  1640. -    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1641. 

  1641. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1642. 

  1642. -/* rADF: or64 source register A (double floating point mode) */
    1643. 

  1643. -  { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 20, 5,
    1644. 

  1644. -    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
    1645. 

  1645. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1646. 

  1646. -/* rBDF: or64 source register B (double floating point mode) */
    1647. 

  1647. -  { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 15, 5,
    1648. 

  1648. -    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
    1649. 

  1649. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1650. 

  1650. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
    1651. 

  1651.  /* rDD32F: destination register (double floating point pair) */
    1652. 

  1652.    { "rDD32F", OR1K_OPERAND_RDD32F, HW_H_FD32R, 10, 6,
    1653. 

  1653.      { 2, { (const PTR) &OR1K_F_RDD32_MULTI_IFIELD[0] } },
    1654. 

  1654. @@ -1214,502 +1151,497 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    1655. 

  1655.  /* l.j ${disp26} */
    1656. 

  1656.    {
    1657. 

  1657.      OR1K_INSN_L_J, "l-j", "l.j", 32,
    1658. 

  1658. -    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1659. 

  1659. +    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1660. 

  1660.    },
    1661. 

  1661.  /* l.adrp $rD,${disp21} */
    1662. 

  1662.    {
    1663. 

  1663.      OR1K_INSN_L_ADRP, "l-adrp", "l.adrp", 32,
    1664. 

  1664. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1665. 

  1665. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1666. 

  1666.    },
    1667. 

  1667.  /* l.jal ${disp26} */
    1668. 

  1668.    {
    1669. 

  1669.      OR1K_INSN_L_JAL, "l-jal", "l.jal", 32,
    1670. 

  1670. -    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1671. 

  1671. +    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1672. 

  1672.    },
    1673. 

  1673.  /* l.jr $rB */
    1674. 

  1674.    {
    1675. 

  1675.      OR1K_INSN_L_JR, "l-jr", "l.jr", 32,
    1676. 

  1676. -    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1677. 

  1677. +    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1678. 

  1678.    },
    1679. 

  1679.  /* l.jalr $rB */
    1680. 

  1680.    {
    1681. 

  1681.      OR1K_INSN_L_JALR, "l-jalr", "l.jalr", 32,
    1682. 

  1682. -    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1683. 

  1683. +    { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1684. 

  1684.    },
    1685. 

  1685.  /* l.bnf ${disp26} */
    1686. 

  1686.    {
    1687. 

  1687.      OR1K_INSN_L_BNF, "l-bnf", "l.bnf", 32,
    1688. 

  1688. -    { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1689. 

  1689. +    { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1690. 

  1690.    },
    1691. 

  1691.  /* l.bf ${disp26} */
    1692. 

  1692.    {
    1693. 

  1693.      OR1K_INSN_L_BF, "l-bf", "l.bf", 32,
    1694. 

  1694. -    { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1695. 

  1695. +    { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1696. 

  1696.    },
    1697. 

  1697.  /* l.trap ${uimm16} */
    1698. 

  1698.    {
    1699. 

  1699.      OR1K_INSN_L_TRAP, "l-trap", "l.trap", 32,
    1700. 

  1700. -    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1701. 

  1701. +    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1702. 

  1702.    },
    1703. 

  1703.  /* l.sys ${uimm16} */
    1704. 

  1704.    {
    1705. 

  1705.      OR1K_INSN_L_SYS, "l-sys", "l.sys", 32,
    1706. 

  1706. -    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1707. 

  1707. +    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1708. 

  1708.    },
    1709. 

  1709.  /* l.msync */
    1710. 

  1710.    {
    1711. 

  1711.      OR1K_INSN_L_MSYNC, "l-msync", "l.msync", 32,
    1712. 

  1712. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1713. 

  1713. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1714. 

  1714.    },
    1715. 

  1715.  /* l.psync */
    1716. 

  1716.    {
    1717. 

  1717.      OR1K_INSN_L_PSYNC, "l-psync", "l.psync", 32,
    1718. 

  1718. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1719. 

  1719. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1720. 

  1720.    },
    1721. 

  1721.  /* l.csync */
    1722. 

  1722.    {
    1723. 

  1723.      OR1K_INSN_L_CSYNC, "l-csync", "l.csync", 32,
    1724. 

  1724. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1725. 

  1725. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1726. 

  1726.    },
    1727. 

  1727.  /* l.rfe */
    1728. 

  1728.    {
    1729. 

  1729.      OR1K_INSN_L_RFE, "l-rfe", "l.rfe", 32,
    1730. 

  1730. -    { 0|A(FORCED_CTI)|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1731. 

  1731. +    { 0|A(FORCED_CTI)|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1732. 

  1732.    },
    1733. 

  1733.  /* l.nop ${uimm16} */
    1734. 

  1734.    {
    1735. 

  1735.      OR1K_INSN_L_NOP_IMM, "l-nop-imm", "l.nop", 32,
    1736. 

  1736. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1737. 

  1737. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1738. 

  1738.    },
    1739. 

  1739.  /* l.nop */
    1740. 

  1740.    {
    1741. 

  1741.      OR1K_INSN_L_NOP, "l-nop", "l.nop", 32,
    1742. 

  1742. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1743. 

  1743. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1744. 

  1744.    },
    1745. 

  1745.  /* l.movhi $rD,$uimm16 */
    1746. 

  1746.    {
    1747. 

  1747.      OR1K_INSN_L_MOVHI, "l-movhi", "l.movhi", 32,
    1748. 

  1748. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1749. 

  1749. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1750. 

  1750.    },
    1751. 

  1751.  /* l.macrc $rD */
    1752. 

  1752.    {
    1753. 

  1753.      OR1K_INSN_L_MACRC, "l-macrc", "l.macrc", 32,
    1754. 

  1754. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1755. 

  1755. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1756. 

  1756.    },
    1757. 

  1757.  /* l.mfspr $rD,$rA,${uimm16} */
    1758. 

  1758.    {
    1759. 

  1759.      OR1K_INSN_L_MFSPR, "l-mfspr", "l.mfspr", 32,
    1760. 

  1760. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1761. 

  1761. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1762. 

  1762.    },
    1763. 

  1763.  /* l.mtspr $rA,$rB,${uimm16-split} */
    1764. 

  1764.    {
    1765. 

  1765.      OR1K_INSN_L_MTSPR, "l-mtspr", "l.mtspr", 32,
    1766. 

  1766. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1767. 

  1767. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1768. 

  1768.    },
    1769. 

  1769.  /* l.lwz $rD,${simm16}($rA) */
    1770. 

  1770.    {
    1771. 

  1771.      OR1K_INSN_L_LWZ, "l-lwz", "l.lwz", 32,
    1772. 

  1772. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1773. 

  1773. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1774. 

  1774.    },
    1775. 

  1775.  /* l.lws $rD,${simm16}($rA) */
    1776. 

  1776.    {
    1777. 

  1777.      OR1K_INSN_L_LWS, "l-lws", "l.lws", 32,
    1778. 

  1778. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1779. 

  1779. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1780. 

  1780.    },
    1781. 

  1781.  /* l.lwa $rD,${simm16}($rA) */
    1782. 

  1782.    {
    1783. 

  1783.      OR1K_INSN_L_LWA, "l-lwa", "l.lwa", 32,
    1784. 

  1784. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1785. 

  1785. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1786. 

  1786.    },
    1787. 

  1787.  /* l.lbz $rD,${simm16}($rA) */
    1788. 

  1788.    {
    1789. 

  1789.      OR1K_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
    1790. 

  1790. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1791. 

  1791. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1792. 

  1792.    },
    1793. 

  1793.  /* l.lbs $rD,${simm16}($rA) */
    1794. 

  1794.    {
    1795. 

  1795.      OR1K_INSN_L_LBS, "l-lbs", "l.lbs", 32,
    1796. 

  1796. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1797. 

  1797. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1798. 

  1798.    },
    1799. 

  1799.  /* l.lhz $rD,${simm16}($rA) */
    1800. 

  1800.    {
    1801. 

  1801.      OR1K_INSN_L_LHZ, "l-lhz", "l.lhz", 32,
    1802. 

  1802. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1803. 

  1803. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1804. 

  1804.    },
    1805. 

  1805.  /* l.lhs $rD,${simm16}($rA) */
    1806. 

  1806.    {
    1807. 

  1807.      OR1K_INSN_L_LHS, "l-lhs", "l.lhs", 32,
    1808. 

  1808. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1809. 

  1809. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1810. 

  1810.    },
    1811. 

  1811.  /* l.sw ${simm16-split}($rA),$rB */
    1812. 

  1812.    {
    1813. 

  1813.      OR1K_INSN_L_SW, "l-sw", "l.sw", 32,
    1814. 

  1814. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1815. 

  1815. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1816. 

  1816.    },
    1817. 

  1817.  /* l.sb ${simm16-split}($rA),$rB */
    1818. 

  1818.    {
    1819. 

  1819.      OR1K_INSN_L_SB, "l-sb", "l.sb", 32,
    1820. 

  1820. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1821. 

  1821. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1822. 

  1822.    },
    1823. 

  1823.  /* l.sh ${simm16-split}($rA),$rB */
    1824. 

  1824.    {
    1825. 

  1825.      OR1K_INSN_L_SH, "l-sh", "l.sh", 32,
    1826. 

  1826. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1827. 

  1827. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1828. 

  1828.    },
    1829. 

  1829.  /* l.swa ${simm16-split}($rA),$rB */
    1830. 

  1830.    {
    1831. 

  1831.      OR1K_INSN_L_SWA, "l-swa", "l.swa", 32,
    1832. 

  1832. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1833. 

  1833. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1834. 

  1834.    },
    1835. 

  1835.  /* l.sll $rD,$rA,$rB */
    1836. 

  1836.    {
    1837. 

  1837.      OR1K_INSN_L_SLL, "l-sll", "l.sll", 32,
    1838. 

  1838. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1839. 

  1839. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1840. 

  1840.    },
    1841. 

  1841.  /* l.slli $rD,$rA,${uimm6} */
    1842. 

  1842.    {
    1843. 

  1843.      OR1K_INSN_L_SLLI, "l-slli", "l.slli", 32,
    1844. 

  1844. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1845. 

  1845. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1846. 

  1846.    },
    1847. 

  1847.  /* l.srl $rD,$rA,$rB */
    1848. 

  1848.    {
    1849. 

  1849.      OR1K_INSN_L_SRL, "l-srl", "l.srl", 32,
    1850. 

  1850. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1851. 

  1851. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1852. 

  1852.    },
    1853. 

  1853.  /* l.srli $rD,$rA,${uimm6} */
    1854. 

  1854.    {
    1855. 

  1855.      OR1K_INSN_L_SRLI, "l-srli", "l.srli", 32,
    1856. 

  1856. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1857. 

  1857. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1858. 

  1858.    },
    1859. 

  1859.  /* l.sra $rD,$rA,$rB */
    1860. 

  1860.    {
    1861. 

  1861.      OR1K_INSN_L_SRA, "l-sra", "l.sra", 32,
    1862. 

  1862. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1863. 

  1863. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1864. 

  1864.    },
    1865. 

  1865.  /* l.srai $rD,$rA,${uimm6} */
    1866. 

  1866.    {
    1867. 

  1867.      OR1K_INSN_L_SRAI, "l-srai", "l.srai", 32,
    1868. 

  1868. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1869. 

  1869. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1870. 

  1870.    },
    1871. 

  1871.  /* l.ror $rD,$rA,$rB */
    1872. 

  1872.    {
    1873. 

  1873.      OR1K_INSN_L_ROR, "l-ror", "l.ror", 32,
    1874. 

  1874. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1875. 

  1875. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1876. 

  1876.    },
    1877. 

  1877.  /* l.rori $rD,$rA,${uimm6} */
    1878. 

  1878.    {
    1879. 

  1879.      OR1K_INSN_L_RORI, "l-rori", "l.rori", 32,
    1880. 

  1880. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1881. 

  1881. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1882. 

  1882.    },
    1883. 

  1883.  /* l.and $rD,$rA,$rB */
    1884. 

  1884.    {
    1885. 

  1885.      OR1K_INSN_L_AND, "l-and", "l.and", 32,
    1886. 

  1886. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1887. 

  1887. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1888. 

  1888.    },
    1889. 

  1889.  /* l.or $rD,$rA,$rB */
    1890. 

  1890.    {
    1891. 

  1891.      OR1K_INSN_L_OR, "l-or", "l.or", 32,
    1892. 

  1892. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1893. 

  1893. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1894. 

  1894.    },
    1895. 

  1895.  /* l.xor $rD,$rA,$rB */
    1896. 

  1896.    {
    1897. 

  1897.      OR1K_INSN_L_XOR, "l-xor", "l.xor", 32,
    1898. 

  1898. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1899. 

  1899. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1900. 

  1900.    },
    1901. 

  1901.  /* l.add $rD,$rA,$rB */
    1902. 

  1902.    {
    1903. 

  1903.      OR1K_INSN_L_ADD, "l-add", "l.add", 32,
    1904. 

  1904. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1905. 

  1905. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1906. 

  1906.    },
    1907. 

  1907.  /* l.sub $rD,$rA,$rB */
    1908. 

  1908.    {
    1909. 

  1909.      OR1K_INSN_L_SUB, "l-sub", "l.sub", 32,
    1910. 

  1910. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1911. 

  1911. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1912. 

  1912.    },
    1913. 

  1913.  /* l.addc $rD,$rA,$rB */
    1914. 

  1914.    {
    1915. 

  1915.      OR1K_INSN_L_ADDC, "l-addc", "l.addc", 32,
    1916. 

  1916. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1917. 

  1917. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1918. 

  1918.    },
    1919. 

  1919.  /* l.mul $rD,$rA,$rB */
    1920. 

  1920.    {
    1921. 

  1921.      OR1K_INSN_L_MUL, "l-mul", "l.mul", 32,
    1922. 

  1922. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1923. 

  1923. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1924. 

  1924.    },
    1925. 

  1925.  /* l.muld $rA,$rB */
    1926. 

  1926.    {
    1927. 

  1927.      OR1K_INSN_L_MULD, "l-muld", "l.muld", 32,
    1928. 

  1928. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1929. 

  1929. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1930. 

  1930.    },
    1931. 

  1931.  /* l.mulu $rD,$rA,$rB */
    1932. 

  1932.    {
    1933. 

  1933.      OR1K_INSN_L_MULU, "l-mulu", "l.mulu", 32,
    1934. 

  1934. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1935. 

  1935. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1936. 

  1936.    },
    1937. 

  1937.  /* l.muldu $rA,$rB */
    1938. 

  1938.    {
    1939. 

  1939.      OR1K_INSN_L_MULDU, "l-muldu", "l.muldu", 32,
    1940. 

  1940. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1941. 

  1941. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1942. 

  1942.    },
    1943. 

  1943.  /* l.div $rD,$rA,$rB */
    1944. 

  1944.    {
    1945. 

  1945.      OR1K_INSN_L_DIV, "l-div", "l.div", 32,
    1946. 

  1946. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1947. 

  1947. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1948. 

  1948.    },
    1949. 

  1949.  /* l.divu $rD,$rA,$rB */
    1950. 

  1950.    {
    1951. 

  1951.      OR1K_INSN_L_DIVU, "l-divu", "l.divu", 32,
    1952. 

  1952. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1953. 

  1953. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1954. 

  1954.    },
    1955. 

  1955.  /* l.ff1 $rD,$rA */
    1956. 

  1956.    {
    1957. 

  1957.      OR1K_INSN_L_FF1, "l-ff1", "l.ff1", 32,
    1958. 

  1958. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1959. 

  1959. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1960. 

  1960.    },
    1961. 

  1961.  /* l.fl1 $rD,$rA */
    1962. 

  1962.    {
    1963. 

  1963.      OR1K_INSN_L_FL1, "l-fl1", "l.fl1", 32,
    1964. 

  1964. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1965. 

  1965. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1966. 

  1966.    },
    1967. 

  1967.  /* l.andi $rD,$rA,$uimm16 */
    1968. 

  1968.    {
    1969. 

  1969.      OR1K_INSN_L_ANDI, "l-andi", "l.andi", 32,
    1970. 

  1970. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1971. 

  1971. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1972. 

  1972.    },
    1973. 

  1973.  /* l.ori $rD,$rA,$uimm16 */
    1974. 

  1974.    {
    1975. 

  1975.      OR1K_INSN_L_ORI, "l-ori", "l.ori", 32,
    1976. 

  1976. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1977. 

  1977. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1978. 

  1978.    },
    1979. 

  1979.  /* l.xori $rD,$rA,$simm16 */
    1980. 

  1980.    {
    1981. 

  1981.      OR1K_INSN_L_XORI, "l-xori", "l.xori", 32,
    1982. 

  1982. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1983. 

  1983. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1984. 

  1984.    },
    1985. 

  1985.  /* l.addi $rD,$rA,$simm16 */
    1986. 

  1986.    {
    1987. 

  1987.      OR1K_INSN_L_ADDI, "l-addi", "l.addi", 32,
    1988. 

  1988. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1989. 

  1989. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1990. 

  1990.    },
    1991. 

  1991.  /* l.addic $rD,$rA,$simm16 */
    1992. 

  1992.    {
    1993. 

  1993.      OR1K_INSN_L_ADDIC, "l-addic", "l.addic", 32,
    1994. 

  1994. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1995. 

  1995. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    1996. 

  1996.    },
    1997. 

  1997.  /* l.muli $rD,$rA,$simm16 */
    1998. 

  1998.    {
    1999. 

  1999.      OR1K_INSN_L_MULI, "l-muli", "l.muli", 32,
    2000. 

  2000. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2001. 

  2001. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2002. 

  2002.    },
    2003. 

  2003.  /* l.exths $rD,$rA */
    2004. 

  2004.    {
    2005. 

  2005.      OR1K_INSN_L_EXTHS, "l-exths", "l.exths", 32,
    2006. 

  2006. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2007. 

  2007. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2008. 

  2008.    },
    2009. 

  2009.  /* l.extbs $rD,$rA */
    2010. 

  2010.    {
    2011. 

  2011.      OR1K_INSN_L_EXTBS, "l-extbs", "l.extbs", 32,
    2012. 

  2012. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2013. 

  2013. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2014. 

  2014.    },
    2015. 

  2015.  /* l.exthz $rD,$rA */
    2016. 

  2016.    {
    2017. 

  2017.      OR1K_INSN_L_EXTHZ, "l-exthz", "l.exthz", 32,
    2018. 

  2018. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2019. 

  2019. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2020. 

  2020.    },
    2021. 

  2021.  /* l.extbz $rD,$rA */
    2022. 

  2022.    {
    2023. 

  2023.      OR1K_INSN_L_EXTBZ, "l-extbz", "l.extbz", 32,
    2024. 

  2024. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2025. 

  2025. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2026. 

  2026.    },
    2027. 

  2027.  /* l.extws $rD,$rA */
    2028. 

  2028.    {
    2029. 

  2029.      OR1K_INSN_L_EXTWS, "l-extws", "l.extws", 32,
    2030. 

  2030. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2031. 

  2031. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2032. 

  2032.    },
    2033. 

  2033.  /* l.extwz $rD,$rA */
    2034. 

  2034.    {
    2035. 

  2035.      OR1K_INSN_L_EXTWZ, "l-extwz", "l.extwz", 32,
    2036. 

  2036. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2037. 

  2037. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2038. 

  2038.    },
    2039. 

  2039.  /* l.cmov $rD,$rA,$rB */
    2040. 

  2040.    {
    2041. 

  2041.      OR1K_INSN_L_CMOV, "l-cmov", "l.cmov", 32,
    2042. 

  2042. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2043. 

  2043. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2044. 

  2044.    },
    2045. 

  2045.  /* l.sfgts $rA,$rB */
    2046. 

  2046.    {
    2047. 

  2047.      OR1K_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32,
    2048. 

  2048. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2049. 

  2049. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2050. 

  2050.    },
    2051. 

  2051.  /* l.sfgtsi $rA,$simm16 */
    2052. 

  2052.    {
    2053. 

  2053.      OR1K_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32,
    2054. 

  2054. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2055. 

  2055. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2056. 

  2056.    },
    2057. 

  2057.  /* l.sfgtu $rA,$rB */
    2058. 

  2058.    {
    2059. 

  2059.      OR1K_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32,
    2060. 

  2060. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2061. 

  2061. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2062. 

  2062.    },
    2063. 

  2063.  /* l.sfgtui $rA,$simm16 */
    2064. 

  2064.    {
    2065. 

  2065.      OR1K_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32,
    2066. 

  2066. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2067. 

  2067. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2068. 

  2068.    },
    2069. 

  2069.  /* l.sfges $rA,$rB */
    2070. 

  2070.    {
    2071. 

  2071.      OR1K_INSN_L_SFGES, "l-sfges", "l.sfges", 32,
    2072. 

  2072. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2073. 

  2073. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2074. 

  2074.    },
    2075. 

  2075.  /* l.sfgesi $rA,$simm16 */
    2076. 

  2076.    {
    2077. 

  2077.      OR1K_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32,
    2078. 

  2078. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2079. 

  2079. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2080. 

  2080.    },
    2081. 

  2081.  /* l.sfgeu $rA,$rB */
    2082. 

  2082.    {
    2083. 

  2083.      OR1K_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32,
    2084. 

  2084. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2085. 

  2085. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2086. 

  2086.    },
    2087. 

  2087.  /* l.sfgeui $rA,$simm16 */
    2088. 

  2088.    {
    2089. 

  2089.      OR1K_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32,
    2090. 

  2090. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2091. 

  2091. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2092. 

  2092.    },
    2093. 

  2093.  /* l.sflts $rA,$rB */
    2094. 

  2094.    {
    2095. 

  2095.      OR1K_INSN_L_SFLTS, "l-sflts", "l.sflts", 32,
    2096. 

  2096. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2097. 

  2097. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2098. 

  2098.    },
    2099. 

  2099.  /* l.sfltsi $rA,$simm16 */
    2100. 

  2100.    {
    2101. 

  2101.      OR1K_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32,
    2102. 

  2102. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2103. 

  2103. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2104. 

  2104.    },
    2105. 

  2105.  /* l.sfltu $rA,$rB */
    2106. 

  2106.    {
    2107. 

  2107.      OR1K_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32,
    2108. 

  2108. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2109. 

  2109. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2110. 

  2110.    },
    2111. 

  2111.  /* l.sfltui $rA,$simm16 */
    2112. 

  2112.    {
    2113. 

  2113.      OR1K_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32,
    2114. 

  2114. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2115. 

  2115. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2116. 

  2116.    },
    2117. 

  2117.  /* l.sfles $rA,$rB */
    2118. 

  2118.    {
    2119. 

  2119.      OR1K_INSN_L_SFLES, "l-sfles", "l.sfles", 32,
    2120. 

  2120. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2121. 

  2121. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2122. 

  2122.    },
    2123. 

  2123.  /* l.sflesi $rA,$simm16 */
    2124. 

  2124.    {
    2125. 

  2125.      OR1K_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32,
    2126. 

  2126. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2127. 

  2127. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2128. 

  2128.    },
    2129. 

  2129.  /* l.sfleu $rA,$rB */
    2130. 

  2130.    {
    2131. 

  2131.      OR1K_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32,
    2132. 

  2132. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2133. 

  2133. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2134. 

  2134.    },
    2135. 

  2135.  /* l.sfleui $rA,$simm16 */
    2136. 

  2136.    {
    2137. 

  2137.      OR1K_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32,
    2138. 

  2138. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2139. 

  2139. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2140. 

  2140.    },
    2141. 

  2141.  /* l.sfeq $rA,$rB */
    2142. 

  2142.    {
    2143. 

  2143.      OR1K_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32,
    2144. 

  2144. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2145. 

  2145. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2146. 

  2146.    },
    2147. 

  2147.  /* l.sfeqi $rA,$simm16 */
    2148. 

  2148.    {
    2149. 

  2149.      OR1K_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32,
    2150. 

  2150. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2151. 

  2151. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2152. 

  2152.    },
    2153. 

  2153.  /* l.sfne $rA,$rB */
    2154. 

  2154.    {
    2155. 

  2155.      OR1K_INSN_L_SFNE, "l-sfne", "l.sfne", 32,
    2156. 

  2156. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2157. 

  2157. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2158. 

  2158.    },
    2159. 

  2159.  /* l.sfnei $rA,$simm16 */
    2160. 

  2160.    {
    2161. 

  2161.      OR1K_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32,
    2162. 

  2162. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2163. 

  2163. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2164. 

  2164.    },
    2165. 

  2165.  /* l.mac $rA,$rB */
    2166. 

  2166.    {
    2167. 

  2167.      OR1K_INSN_L_MAC, "l-mac", "l.mac", 32,
    2168. 

  2168. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2169. 

  2169. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2170. 

  2170.    },
    2171. 

  2171.  /* l.maci $rA,${simm16} */
    2172. 

  2172.    {
    2173. 

  2173.      OR1K_INSN_L_MACI, "l-maci", "l.maci", 32,
    2174. 

  2174. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2175. 

  2175. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2176. 

  2176.    },
    2177. 

  2177.  /* l.macu $rA,$rB */
    2178. 

  2178.    {
    2179. 

  2179.      OR1K_INSN_L_MACU, "l-macu", "l.macu", 32,
    2180. 

  2180. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2181. 

  2181. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2182. 

  2182.    },
    2183. 

  2183.  /* l.msb $rA,$rB */
    2184. 

  2184.    {
    2185. 

  2185.      OR1K_INSN_L_MSB, "l-msb", "l.msb", 32,
    2186. 

  2186. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2187. 

  2187. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2188. 

  2188.    },
    2189. 

  2189.  /* l.msbu $rA,$rB */
    2190. 

  2190.    {
    2191. 

  2191.      OR1K_INSN_L_MSBU, "l-msbu", "l.msbu", 32,
    2192. 

  2192. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2193. 

  2193. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2194. 

  2194.    },
    2195. 

  2195.  /* l.cust1 */
    2196. 

  2196.    {
    2197. 

  2197.      OR1K_INSN_L_CUST1, "l-cust1", "l.cust1", 32,
    2198. 

  2198. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2199. 

  2199. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2200. 

  2200.    },
    2201. 

  2201.  /* l.cust2 */
    2202. 

  2202.    {
    2203. 

  2203.      OR1K_INSN_L_CUST2, "l-cust2", "l.cust2", 32,
    2204. 

  2204. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2205. 

  2205. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2206. 

  2206.    },
    2207. 

  2207.  /* l.cust3 */
    2208. 

  2208.    {
    2209. 

  2209.      OR1K_INSN_L_CUST3, "l-cust3", "l.cust3", 32,
    2210. 

  2210. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2211. 

  2211. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2212. 

  2212.    },
    2213. 

  2213.  /* l.cust4 */
    2214. 

  2214.    {
    2215. 

  2215.      OR1K_INSN_L_CUST4, "l-cust4", "l.cust4", 32,
    2216. 

  2216. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2217. 

  2217. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2218. 

  2218.    },
    2219. 

  2219.  /* l.cust5 */
    2220. 

  2220.    {
    2221. 

  2221.      OR1K_INSN_L_CUST5, "l-cust5", "l.cust5", 32,
    2222. 

  2222. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2223. 

  2223. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2224. 

  2224.    },
    2225. 

  2225.  /* l.cust6 */
    2226. 

  2226.    {
    2227. 

  2227.      OR1K_INSN_L_CUST6, "l-cust6", "l.cust6", 32,
    2228. 

  2228. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2229. 

  2229. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2230. 

  2230.    },
    2231. 

  2231.  /* l.cust7 */
    2232. 

  2232.    {
    2233. 

  2233.      OR1K_INSN_L_CUST7, "l-cust7", "l.cust7", 32,
    2234. 

  2234. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2235. 

  2235. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2236. 

  2236.    },
    2237. 

  2237.  /* l.cust8 */
    2238. 

  2238.    {
    2239. 

  2239.      OR1K_INSN_L_CUST8, "l-cust8", "l.cust8", 32,
    2240. 

  2240. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2241. 

  2241. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2242. 

  2242.    },
    2243. 

  2243.  /* lf.add.s $rDSF,$rASF,$rBSF */
    2244. 

  2244.    {
    2245. 

  2245.      OR1K_INSN_LF_ADD_S, "lf-add-s", "lf.add.s", 32,
    2246. 

  2246. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2247. 

  2247. -  },
    2248. 

  2248. -/* lf.add.d $rDDF,$rADF,$rBDF */
    2249. 

  2249. -  {
    2250. 

  2250. -    OR1K_INSN_LF_ADD_D, "lf-add-d", "lf.add.d", 32,
    2251. 

  2251. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2252. 

  2252. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2253. 

  2253.    },
    2254. 

  2254.  /* lf.add.d $rDD32F,$rAD32F,$rBD32F */
    2255. 

  2255.    {
    2256. 

  2256. @@ -1719,12 +1651,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2257. 

  2257.  /* lf.sub.s $rDSF,$rASF,$rBSF */
    2258. 

  2258.    {
    2259. 

  2259.      OR1K_INSN_LF_SUB_S, "lf-sub-s", "lf.sub.s", 32,
    2260. 

  2260. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2261. 

  2261. -  },
    2262. 

  2262. -/* lf.sub.d $rDDF,$rADF,$rBDF */
    2263. 

  2263. -  {
    2264. 

  2264. -    OR1K_INSN_LF_SUB_D, "lf-sub-d", "lf.sub.d", 32,
    2265. 

  2265. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2266. 

  2266. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2267. 

  2267.    },
    2268. 

  2268.  /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
    2269. 

  2269.    {
    2270. 

  2270. @@ -1734,12 +1661,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2271. 

  2271.  /* lf.mul.s $rDSF,$rASF,$rBSF */
    2272. 

  2272.    {
    2273. 

  2273.      OR1K_INSN_LF_MUL_S, "lf-mul-s", "lf.mul.s", 32,
    2274. 

  2274. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2275. 

  2275. -  },
    2276. 

  2276. -/* lf.mul.d $rDDF,$rADF,$rBDF */
    2277. 

  2277. -  {
    2278. 

  2278. -    OR1K_INSN_LF_MUL_D, "lf-mul-d", "lf.mul.d", 32,
    2279. 

  2279. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2280. 

  2280. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2281. 

  2281.    },
    2282. 

  2282.  /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
    2283. 

  2283.    {
    2284. 

  2284. @@ -1749,12 +1671,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2285. 

  2285.  /* lf.div.s $rDSF,$rASF,$rBSF */
    2286. 

  2286.    {
    2287. 

  2287.      OR1K_INSN_LF_DIV_S, "lf-div-s", "lf.div.s", 32,
    2288. 

  2288. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2289. 

  2289. -  },
    2290. 

  2290. -/* lf.div.d $rDDF,$rADF,$rBDF */
    2291. 

  2291. -  {
    2292. 

  2292. -    OR1K_INSN_LF_DIV_D, "lf-div-d", "lf.div.d", 32,
    2293. 

  2293. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2294. 

  2294. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2295. 

  2295.    },
    2296. 

  2296.  /* lf.div.d $rDD32F,$rAD32F,$rBD32F */
    2297. 

  2297.    {
    2298. 

  2298. @@ -1764,12 +1681,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2299. 

  2299.  /* lf.rem.s $rDSF,$rASF,$rBSF */
    2300. 

  2300.    {
    2301. 

  2301.      OR1K_INSN_LF_REM_S, "lf-rem-s", "lf.rem.s", 32,
    2302. 

  2302. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2303. 

  2303. -  },
    2304. 

  2304. -/* lf.rem.d $rDDF,$rADF,$rBDF */
    2305. 

  2305. -  {
    2306. 

  2306. -    OR1K_INSN_LF_REM_D, "lf-rem-d", "lf.rem.d", 32,
    2307. 

  2307. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2308. 

  2308. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2309. 

  2309.    },
    2310. 

  2310.  /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
    2311. 

  2311.    {
    2312. 

  2312. @@ -1779,12 +1691,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2313. 

  2313.  /* lf.itof.s $rDSF,$rA */
    2314. 

  2314.    {
    2315. 

  2315.      OR1K_INSN_LF_ITOF_S, "lf-itof-s", "lf.itof.s", 32,
    2316. 

  2316. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2317. 

  2317. -  },
    2318. 

  2318. -/* lf.itof.d $rDDF,$rA */
    2319. 

  2319. -  {
    2320. 

  2320. -    OR1K_INSN_LF_ITOF_D, "lf-itof-d", "lf.itof.d", 32,
    2321. 

  2321. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2322. 

  2322. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2323. 

  2323.    },
    2324. 

  2324.  /* lf.itof.d $rDD32F,$rADI */
    2325. 

  2325.    {
    2326. 

  2326. @@ -1794,12 +1701,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2327. 

  2327.  /* lf.ftoi.s $rD,$rASF */
    2328. 

  2328.    {
    2329. 

  2329.      OR1K_INSN_LF_FTOI_S, "lf-ftoi-s", "lf.ftoi.s", 32,
    2330. 

  2330. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2331. 

  2331. -  },
    2332. 

  2332. -/* lf.ftoi.d $rD,$rADF */
    2333. 

  2333. -  {
    2334. 

  2334. -    OR1K_INSN_LF_FTOI_D, "lf-ftoi-d", "lf.ftoi.d", 32,
    2335. 

  2335. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2336. 

  2336. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2337. 

  2337.    },
    2338. 

  2338.  /* lf.ftoi.d $rDDI,$rAD32F */
    2339. 

  2339.    {
    2340. 

  2340. @@ -1809,12 +1711,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2341. 

  2341.  /* lf.sfeq.s $rASF,$rBSF */
    2342. 

  2342.    {
    2343. 

  2343.      OR1K_INSN_LF_SFEQ_S, "lf-sfeq-s", "lf.sfeq.s", 32,
    2344. 

  2344. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2345. 

  2345. -  },
    2346. 

  2346. -/* lf.sfeq.d $rADF,$rBDF */
    2347. 

  2347. -  {
    2348. 

  2348. -    OR1K_INSN_LF_SFEQ_D, "lf-sfeq-d", "lf.sfeq.d", 32,
    2349. 

  2349. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2350. 

  2350. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2351. 

  2351.    },
    2352. 

  2352.  /* lf.sfeq.d $rAD32F,$rBD32F */
    2353. 

  2353.    {
    2354. 

  2354. @@ -1824,12 +1721,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2355. 

  2355.  /* lf.sfne.s $rASF,$rBSF */
    2356. 

  2356.    {
    2357. 

  2357.      OR1K_INSN_LF_SFNE_S, "lf-sfne-s", "lf.sfne.s", 32,
    2358. 

  2358. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2359. 

  2359. -  },
    2360. 

  2360. -/* lf.sfne.d $rADF,$rBDF */
    2361. 

  2361. -  {
    2362. 

  2362. -    OR1K_INSN_LF_SFNE_D, "lf-sfne-d", "lf.sfne.d", 32,
    2363. 

  2363. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2364. 

  2364. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2365. 

  2365.    },
    2366. 

  2366.  /* lf.sfne.d $rAD32F,$rBD32F */
    2367. 

  2367.    {
    2368. 

  2368. @@ -1839,12 +1731,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2369. 

  2369.  /* lf.sfge.s $rASF,$rBSF */
    2370. 

  2370.    {
    2371. 

  2371.      OR1K_INSN_LF_SFGE_S, "lf-sfge-s", "lf.sfge.s", 32,
    2372. 

  2372. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2373. 

  2373. -  },
    2374. 

  2374. -/* lf.sfge.d $rADF,$rBDF */
    2375. 

  2375. -  {
    2376. 

  2376. -    OR1K_INSN_LF_SFGE_D, "lf-sfge-d", "lf.sfge.d", 32,
    2377. 

  2377. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2378. 

  2378. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2379. 

  2379.    },
    2380. 

  2380.  /* lf.sfge.d $rAD32F,$rBD32F */
    2381. 

  2381.    {
    2382. 

  2382. @@ -1854,12 +1741,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2383. 

  2383.  /* lf.sfgt.s $rASF,$rBSF */
    2384. 

  2384.    {
    2385. 

  2385.      OR1K_INSN_LF_SFGT_S, "lf-sfgt-s", "lf.sfgt.s", 32,
    2386. 

  2386. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2387. 

  2387. -  },
    2388. 

  2388. -/* lf.sfgt.d $rADF,$rBDF */
    2389. 

  2389. -  {
    2390. 

  2390. -    OR1K_INSN_LF_SFGT_D, "lf-sfgt-d", "lf.sfgt.d", 32,
    2391. 

  2391. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2392. 

  2392. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2393. 

  2393.    },
    2394. 

  2394.  /* lf.sfgt.d $rAD32F,$rBD32F */
    2395. 

  2395.    {
    2396. 

  2396. @@ -1869,12 +1751,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2397. 

  2397.  /* lf.sflt.s $rASF,$rBSF */
    2398. 

  2398.    {
    2399. 

  2399.      OR1K_INSN_LF_SFLT_S, "lf-sflt-s", "lf.sflt.s", 32,
    2400. 

  2400. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2401. 

  2401. -  },
    2402. 

  2402. -/* lf.sflt.d $rADF,$rBDF */
    2403. 

  2403. -  {
    2404. 

  2404. -    OR1K_INSN_LF_SFLT_D, "lf-sflt-d", "lf.sflt.d", 32,
    2405. 

  2405. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2406. 

  2406. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2407. 

  2407.    },
    2408. 

  2408.  /* lf.sflt.d $rAD32F,$rBD32F */
    2409. 

  2409.    {
    2410. 

  2410. @@ -1884,12 +1761,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2411. 

  2411.  /* lf.sfle.s $rASF,$rBSF */
    2412. 

  2412.    {
    2413. 

  2413.      OR1K_INSN_LF_SFLE_S, "lf-sfle-s", "lf.sfle.s", 32,
    2414. 

  2414. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2415. 

  2415. -  },
    2416. 

  2416. -/* lf.sfle.d $rADF,$rBDF */
    2417. 

  2417. -  {
    2418. 

  2418. -    OR1K_INSN_LF_SFLE_D, "lf-sfle-d", "lf.sfle.d", 32,
    2419. 

  2419. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2420. 

  2420. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2421. 

  2421.    },
    2422. 

  2422.  /* lf.sfle.d $rAD32F,$rBD32F */
    2423. 

  2423.    {
    2424. 

  2424. @@ -1899,12 +1771,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2425. 

  2425.  /* lf.sfueq.s $rASF,$rBSF */
    2426. 

  2426.    {
    2427. 

  2427.      OR1K_INSN_LF_SFUEQ_S, "lf-sfueq-s", "lf.sfueq.s", 32,
    2428. 

  2428. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2429. 

  2429. -  },
    2430. 

  2430. -/* lf.sfueq.d $rADF,$rBDF */
    2431. 

  2431. -  {
    2432. 

  2432. -    OR1K_INSN_LF_SFUEQ_D, "lf-sfueq-d", "lf.sfueq.d", 32,
    2433. 

  2433. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2434. 

  2434. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2435. 

  2435.    },
    2436. 

  2436.  /* lf.sfueq.d $rAD32F,$rBD32F */
    2437. 

  2437.    {
    2438. 

  2438. @@ -1914,12 +1781,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2439. 

  2439.  /* lf.sfune.s $rASF,$rBSF */
    2440. 

  2440.    {
    2441. 

  2441.      OR1K_INSN_LF_SFUNE_S, "lf-sfune-s", "lf.sfune.s", 32,
    2442. 

  2442. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2443. 

  2443. -  },
    2444. 

  2444. -/* lf.sfune.d $rADF,$rBDF */
    2445. 

  2445. -  {
    2446. 

  2446. -    OR1K_INSN_LF_SFUNE_D, "lf-sfune-d", "lf.sfune.d", 32,
    2447. 

  2447. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2448. 

  2448. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2449. 

  2449.    },
    2450. 

  2450.  /* lf.sfune.d $rAD32F,$rBD32F */
    2451. 

  2451.    {
    2452. 

  2452. @@ -1929,12 +1791,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2453. 

  2453.  /* lf.sfugt.s $rASF,$rBSF */
    2454. 

  2454.    {
    2455. 

  2455.      OR1K_INSN_LF_SFUGT_S, "lf-sfugt-s", "lf.sfugt.s", 32,
    2456. 

  2456. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2457. 

  2457. -  },
    2458. 

  2458. -/* lf.sfugt.d $rADF,$rBDF */
    2459. 

  2459. -  {
    2460. 

  2460. -    OR1K_INSN_LF_SFUGT_D, "lf-sfugt-d", "lf.sfugt.d", 32,
    2461. 

  2461. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2462. 

  2462. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2463. 

  2463.    },
    2464. 

  2464.  /* lf.sfugt.d $rAD32F,$rBD32F */
    2465. 

  2465.    {
    2466. 

  2466. @@ -1944,12 +1801,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2467. 

  2467.  /* lf.sfuge.s $rASF,$rBSF */
    2468. 

  2468.    {
    2469. 

  2469.      OR1K_INSN_LF_SFUGE_S, "lf-sfuge-s", "lf.sfuge.s", 32,
    2470. 

  2470. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2471. 

  2471. -  },
    2472. 

  2472. -/* lf.sfuge.d $rADF,$rBDF */
    2473. 

  2473. -  {
    2474. 

  2474. -    OR1K_INSN_LF_SFUGE_D, "lf-sfuge-d", "lf.sfuge.d", 32,
    2475. 

  2475. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2476. 

  2476. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2477. 

  2477.    },
    2478. 

  2478.  /* lf.sfuge.d $rAD32F,$rBD32F */
    2479. 

  2479.    {
    2480. 

  2480. @@ -1959,12 +1811,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2481. 

  2481.  /* lf.sfult.s $rASF,$rBSF */
    2482. 

  2482.    {
    2483. 

  2483.      OR1K_INSN_LF_SFULT_S, "lf-sfult-s", "lf.sfult.s", 32,
    2484. 

  2484. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2485. 

  2485. -  },
    2486. 

  2486. -/* lf.sfult.d $rADF,$rBDF */
    2487. 

  2487. -  {
    2488. 

  2488. -    OR1K_INSN_LF_SFULT_D, "lf-sfult-d", "lf.sfult.d", 32,
    2489. 

  2489. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2490. 

  2490. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2491. 

  2491.    },
    2492. 

  2492.  /* lf.sfult.d $rAD32F,$rBD32F */
    2493. 

  2493.    {
    2494. 

  2494. @@ -1974,12 +1821,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2495. 

  2495.  /* lf.sfule.s $rASF,$rBSF */
    2496. 

  2496.    {
    2497. 

  2497.      OR1K_INSN_LF_SFULE_S, "lf-sfule-s", "lf.sfule.s", 32,
    2498. 

  2498. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2499. 

  2499. -  },
    2500. 

  2500. -/* lf.sfule.d $rADF,$rBDF */
    2501. 

  2501. -  {
    2502. 

  2502. -    OR1K_INSN_LF_SFULE_D, "lf-sfule-d", "lf.sfule.d", 32,
    2503. 

  2503. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2504. 

  2504. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2505. 

  2505.    },
    2506. 

  2506.  /* lf.sfule.d $rAD32F,$rBD32F */
    2507. 

  2507.    {
    2508. 

  2508. @@ -1989,12 +1831,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2509. 

  2509.  /* lf.sfun.s $rASF,$rBSF */
    2510. 

  2510.    {
    2511. 

  2511.      OR1K_INSN_LF_SFUN_S, "lf-sfun-s", "lf.sfun.s", 32,
    2512. 

  2512. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2513. 

  2513. -  },
    2514. 

  2514. -/* lf.sfun.d $rADF,$rBDF */
    2515. 

  2515. -  {
    2516. 

  2516. -    OR1K_INSN_LF_SFUN_D, "lf-sfun-d", "lf.sfun.d", 32,
    2517. 

  2517. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2518. 

  2518. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2519. 

  2519.    },
    2520. 

  2520.  /* lf.sfun.d $rAD32F,$rBD32F */
    2521. 

  2521.    {
    2522. 

  2522. @@ -2004,12 +1841,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2523. 

  2523.  /* lf.madd.s $rDSF,$rASF,$rBSF */
    2524. 

  2524.    {
    2525. 

  2525.      OR1K_INSN_LF_MADD_S, "lf-madd-s", "lf.madd.s", 32,
    2526. 

  2526. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2527. 

  2527. -  },
    2528. 

  2528. -/* lf.madd.d $rDDF,$rADF,$rBDF */
    2529. 

  2529. -  {
    2530. 

  2530. -    OR1K_INSN_LF_MADD_D, "lf-madd-d", "lf.madd.d", 32,
    2531. 

  2531. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2532. 

  2532. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2533. 

  2533.    },
    2534. 

  2534.  /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
    2535. 

  2535.    {
    2536. 

  2536. @@ -2019,12 +1851,7 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    2537. 

  2537.  /* lf.cust1.s $rASF,$rBSF */
    2538. 

  2538.    {
    2539. 

  2539.      OR1K_INSN_LF_CUST1_S, "lf-cust1-s", "lf.cust1.s", 32,
    2540. 

  2540. -    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2541. 

  2541. -  },
    2542. 

  2542. -/* lf.cust1.d */
    2543. 

  2543. -  {
    2544. 

  2544. -    OR1K_INSN_LF_CUST1_D, "lf-cust1-d", "lf.cust1.d", 32,
    2545. 

  2545. -    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    2546. 

  2546. +    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
    2547. 

  2547.    },
    2548. 

  2548.  /* lf.cust1.d */
    2549. 

  2549.    {
    2550. 

  2550. diff --git a/opcodes/or1k-desc.h b/opcodes/or1k-desc.h
    2551. 

  2551. index 1121c99e49..9b85032616 100644
    2552. 

  2552. --- a/opcodes/or1k-desc.h
    2553. 

  2553. +++ b/opcodes/or1k-desc.h
    2554. 

  2554. @@ -38,7 +38,6 @@ extern "C" {
    2555. 

  2555.  
    2556. 

  2556.  /* Selected cpu families.  */
    2557. 

  2557.  #define HAVE_CPU_OR1K32BF
    2558. 

  2558. -#define HAVE_CPU_OR1K64BF
    2559. 

  2559.  
    2560. 

  2560.  #define CGEN_INSN_LSB0_P 1
    2561. 

  2561.  
    2562. 

  2562. @@ -359,8 +358,7 @@ typedef enum insn_opcode_float_regreg {
    2563. 

  2563.  
    2564. 

  2564.  /* Enum declaration for machine type selection.  */
    2565. 

  2565.  typedef enum mach_attr {
    2566. 

  2566. -  MACH_BASE, MACH_OR32, MACH_OR32ND, MACH_OR64
    2567. 

  2567. - , MACH_OR64ND, MACH_MAX
    2568. 

  2568. +  MACH_BASE, MACH_OR32, MACH_OR32ND, MACH_MAX
    2569. 

  2569.  } MACH_ATTR;
    2570. 

  2570.  
    2571. 

  2571.  /* Enum declaration for instruction set selection.  */
    2572. 

  2572. @@ -435,166 +433,166 @@ typedef enum cgen_hw_attr {
    2573. 

  2573.  typedef enum cgen_hw_type {
    2574. 

  2574.    HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
    2575. 

  2575.   , HW_H_IADDR, HW_H_PC, HW_H_SPR, HW_H_GPR
    2576. 

  2576. - , HW_H_FSR, HW_H_FDR, HW_H_FD32R, HW_H_I64R
    2577. 

  2577. - , HW_H_SYS_VR, HW_H_SYS_UPR, HW_H_SYS_CPUCFGR, HW_H_SYS_DMMUCFGR
    2578. 

  2578. - , HW_H_SYS_IMMUCFGR, HW_H_SYS_DCCFGR, HW_H_SYS_ICCFGR, HW_H_SYS_DCFGR
    2579. 

  2579. - , HW_H_SYS_PCCFGR, HW_H_SYS_NPC, HW_H_SYS_SR, HW_H_SYS_PPC
    2580. 

  2580. - , HW_H_SYS_FPCSR, HW_H_SYS_EPCR0, HW_H_SYS_EPCR1, HW_H_SYS_EPCR2
    2581. 

  2581. - , HW_H_SYS_EPCR3, HW_H_SYS_EPCR4, HW_H_SYS_EPCR5, HW_H_SYS_EPCR6
    2582. 

  2582. - , HW_H_SYS_EPCR7, HW_H_SYS_EPCR8, HW_H_SYS_EPCR9, HW_H_SYS_EPCR10
    2583. 

  2583. - , HW_H_SYS_EPCR11, HW_H_SYS_EPCR12, HW_H_SYS_EPCR13, HW_H_SYS_EPCR14
    2584. 

  2584. - , HW_H_SYS_EPCR15, HW_H_SYS_EEAR0, HW_H_SYS_EEAR1, HW_H_SYS_EEAR2
    2585. 

  2585. - , HW_H_SYS_EEAR3, HW_H_SYS_EEAR4, HW_H_SYS_EEAR5, HW_H_SYS_EEAR6
    2586. 

  2586. - , HW_H_SYS_EEAR7, HW_H_SYS_EEAR8, HW_H_SYS_EEAR9, HW_H_SYS_EEAR10
    2587. 

  2587. - , HW_H_SYS_EEAR11, HW_H_SYS_EEAR12, HW_H_SYS_EEAR13, HW_H_SYS_EEAR14
    2588. 

  2588. - , HW_H_SYS_EEAR15, HW_H_SYS_ESR0, HW_H_SYS_ESR1, HW_H_SYS_ESR2
    2589. 

  2589. - , HW_H_SYS_ESR3, HW_H_SYS_ESR4, HW_H_SYS_ESR5, HW_H_SYS_ESR6
    2590. 

  2590. - , HW_H_SYS_ESR7, HW_H_SYS_ESR8, HW_H_SYS_ESR9, HW_H_SYS_ESR10
    2591. 

  2591. - , HW_H_SYS_ESR11, HW_H_SYS_ESR12, HW_H_SYS_ESR13, HW_H_SYS_ESR14
    2592. 

  2592. - , HW_H_SYS_ESR15, HW_H_SYS_GPR0, HW_H_SYS_GPR1, HW_H_SYS_GPR2
    2593. 

  2593. - , HW_H_SYS_GPR3, HW_H_SYS_GPR4, HW_H_SYS_GPR5, HW_H_SYS_GPR6
    2594. 

  2594. - , HW_H_SYS_GPR7, HW_H_SYS_GPR8, HW_H_SYS_GPR9, HW_H_SYS_GPR10
    2595. 

  2595. - , HW_H_SYS_GPR11, HW_H_SYS_GPR12, HW_H_SYS_GPR13, HW_H_SYS_GPR14
    2596. 

  2596. - , HW_H_SYS_GPR15, HW_H_SYS_GPR16, HW_H_SYS_GPR17, HW_H_SYS_GPR18
    2597. 

  2597. - , HW_H_SYS_GPR19, HW_H_SYS_GPR20, HW_H_SYS_GPR21, HW_H_SYS_GPR22
    2598. 

  2598. - , HW_H_SYS_GPR23, HW_H_SYS_GPR24, HW_H_SYS_GPR25, HW_H_SYS_GPR26
    2599. 

  2599. - , HW_H_SYS_GPR27, HW_H_SYS_GPR28, HW_H_SYS_GPR29, HW_H_SYS_GPR30
    2600. 

  2600. - , HW_H_SYS_GPR31, HW_H_SYS_GPR32, HW_H_SYS_GPR33, HW_H_SYS_GPR34
    2601. 

  2601. - , HW_H_SYS_GPR35, HW_H_SYS_GPR36, HW_H_SYS_GPR37, HW_H_SYS_GPR38
    2602. 

  2602. - , HW_H_SYS_GPR39, HW_H_SYS_GPR40, HW_H_SYS_GPR41, HW_H_SYS_GPR42
    2603. 

  2603. - , HW_H_SYS_GPR43, HW_H_SYS_GPR44, HW_H_SYS_GPR45, HW_H_SYS_GPR46
    2604. 

  2604. - , HW_H_SYS_GPR47, HW_H_SYS_GPR48, HW_H_SYS_GPR49, HW_H_SYS_GPR50
    2605. 

  2605. - , HW_H_SYS_GPR51, HW_H_SYS_GPR52, HW_H_SYS_GPR53, HW_H_SYS_GPR54
    2606. 

  2606. - , HW_H_SYS_GPR55, HW_H_SYS_GPR56, HW_H_SYS_GPR57, HW_H_SYS_GPR58
    2607. 

  2607. - , HW_H_SYS_GPR59, HW_H_SYS_GPR60, HW_H_SYS_GPR61, HW_H_SYS_GPR62
    2608. 

  2608. - , HW_H_SYS_GPR63, HW_H_SYS_GPR64, HW_H_SYS_GPR65, HW_H_SYS_GPR66
    2609. 

  2609. - , HW_H_SYS_GPR67, HW_H_SYS_GPR68, HW_H_SYS_GPR69, HW_H_SYS_GPR70
    2610. 

  2610. - , HW_H_SYS_GPR71, HW_H_SYS_GPR72, HW_H_SYS_GPR73, HW_H_SYS_GPR74
    2611. 

  2611. - , HW_H_SYS_GPR75, HW_H_SYS_GPR76, HW_H_SYS_GPR77, HW_H_SYS_GPR78
    2612. 

  2612. - , HW_H_SYS_GPR79, HW_H_SYS_GPR80, HW_H_SYS_GPR81, HW_H_SYS_GPR82
    2613. 

  2613. - , HW_H_SYS_GPR83, HW_H_SYS_GPR84, HW_H_SYS_GPR85, HW_H_SYS_GPR86
    2614. 

  2614. - , HW_H_SYS_GPR87, HW_H_SYS_GPR88, HW_H_SYS_GPR89, HW_H_SYS_GPR90
    2615. 

  2615. - , HW_H_SYS_GPR91, HW_H_SYS_GPR92, HW_H_SYS_GPR93, HW_H_SYS_GPR94
    2616. 

  2616. - , HW_H_SYS_GPR95, HW_H_SYS_GPR96, HW_H_SYS_GPR97, HW_H_SYS_GPR98
    2617. 

  2617. - , HW_H_SYS_GPR99, HW_H_SYS_GPR100, HW_H_SYS_GPR101, HW_H_SYS_GPR102
    2618. 

  2618. - , HW_H_SYS_GPR103, HW_H_SYS_GPR104, HW_H_SYS_GPR105, HW_H_SYS_GPR106
    2619. 

  2619. - , HW_H_SYS_GPR107, HW_H_SYS_GPR108, HW_H_SYS_GPR109, HW_H_SYS_GPR110
    2620. 

  2620. - , HW_H_SYS_GPR111, HW_H_SYS_GPR112, HW_H_SYS_GPR113, HW_H_SYS_GPR114
    2621. 

  2621. - , HW_H_SYS_GPR115, HW_H_SYS_GPR116, HW_H_SYS_GPR117, HW_H_SYS_GPR118
    2622. 

  2622. - , HW_H_SYS_GPR119, HW_H_SYS_GPR120, HW_H_SYS_GPR121, HW_H_SYS_GPR122
    2623. 

  2623. - , HW_H_SYS_GPR123, HW_H_SYS_GPR124, HW_H_SYS_GPR125, HW_H_SYS_GPR126
    2624. 

  2624. - , HW_H_SYS_GPR127, HW_H_SYS_GPR128, HW_H_SYS_GPR129, HW_H_SYS_GPR130
    2625. 

  2625. - , HW_H_SYS_GPR131, HW_H_SYS_GPR132, HW_H_SYS_GPR133, HW_H_SYS_GPR134
    2626. 

  2626. - , HW_H_SYS_GPR135, HW_H_SYS_GPR136, HW_H_SYS_GPR137, HW_H_SYS_GPR138
    2627. 

  2627. - , HW_H_SYS_GPR139, HW_H_SYS_GPR140, HW_H_SYS_GPR141, HW_H_SYS_GPR142
    2628. 

  2628. - , HW_H_SYS_GPR143, HW_H_SYS_GPR144, HW_H_SYS_GPR145, HW_H_SYS_GPR146
    2629. 

  2629. - , HW_H_SYS_GPR147, HW_H_SYS_GPR148, HW_H_SYS_GPR149, HW_H_SYS_GPR150
    2630. 

  2630. - , HW_H_SYS_GPR151, HW_H_SYS_GPR152, HW_H_SYS_GPR153, HW_H_SYS_GPR154
    2631. 

  2631. - , HW_H_SYS_GPR155, HW_H_SYS_GPR156, HW_H_SYS_GPR157, HW_H_SYS_GPR158
    2632. 

  2632. - , HW_H_SYS_GPR159, HW_H_SYS_GPR160, HW_H_SYS_GPR161, HW_H_SYS_GPR162
    2633. 

  2633. - , HW_H_SYS_GPR163, HW_H_SYS_GPR164, HW_H_SYS_GPR165, HW_H_SYS_GPR166
    2634. 

  2634. - , HW_H_SYS_GPR167, HW_H_SYS_GPR168, HW_H_SYS_GPR169, HW_H_SYS_GPR170
    2635. 

  2635. - , HW_H_SYS_GPR171, HW_H_SYS_GPR172, HW_H_SYS_GPR173, HW_H_SYS_GPR174
    2636. 

  2636. - , HW_H_SYS_GPR175, HW_H_SYS_GPR176, HW_H_SYS_GPR177, HW_H_SYS_GPR178
    2637. 

  2637. - , HW_H_SYS_GPR179, HW_H_SYS_GPR180, HW_H_SYS_GPR181, HW_H_SYS_GPR182
    2638. 

  2638. - , HW_H_SYS_GPR183, HW_H_SYS_GPR184, HW_H_SYS_GPR185, HW_H_SYS_GPR186
    2639. 

  2639. - , HW_H_SYS_GPR187, HW_H_SYS_GPR188, HW_H_SYS_GPR189, HW_H_SYS_GPR190
    2640. 

  2640. - , HW_H_SYS_GPR191, HW_H_SYS_GPR192, HW_H_SYS_GPR193, HW_H_SYS_GPR194
    2641. 

  2641. - , HW_H_SYS_GPR195, HW_H_SYS_GPR196, HW_H_SYS_GPR197, HW_H_SYS_GPR198
    2642. 

  2642. - , HW_H_SYS_GPR199, HW_H_SYS_GPR200, HW_H_SYS_GPR201, HW_H_SYS_GPR202
    2643. 

  2643. - , HW_H_SYS_GPR203, HW_H_SYS_GPR204, HW_H_SYS_GPR205, HW_H_SYS_GPR206
    2644. 

  2644. - , HW_H_SYS_GPR207, HW_H_SYS_GPR208, HW_H_SYS_GPR209, HW_H_SYS_GPR210
    2645. 

  2645. - , HW_H_SYS_GPR211, HW_H_SYS_GPR212, HW_H_SYS_GPR213, HW_H_SYS_GPR214
    2646. 

  2646. - , HW_H_SYS_GPR215, HW_H_SYS_GPR216, HW_H_SYS_GPR217, HW_H_SYS_GPR218
    2647. 

  2647. - , HW_H_SYS_GPR219, HW_H_SYS_GPR220, HW_H_SYS_GPR221, HW_H_SYS_GPR222
    2648. 

  2648. - , HW_H_SYS_GPR223, HW_H_SYS_GPR224, HW_H_SYS_GPR225, HW_H_SYS_GPR226
    2649. 

  2649. - , HW_H_SYS_GPR227, HW_H_SYS_GPR228, HW_H_SYS_GPR229, HW_H_SYS_GPR230
    2650. 

  2650. - , HW_H_SYS_GPR231, HW_H_SYS_GPR232, HW_H_SYS_GPR233, HW_H_SYS_GPR234
    2651. 

  2651. - , HW_H_SYS_GPR235, HW_H_SYS_GPR236, HW_H_SYS_GPR237, HW_H_SYS_GPR238
    2652. 

  2652. - , HW_H_SYS_GPR239, HW_H_SYS_GPR240, HW_H_SYS_GPR241, HW_H_SYS_GPR242
    2653. 

  2653. - , HW_H_SYS_GPR243, HW_H_SYS_GPR244, HW_H_SYS_GPR245, HW_H_SYS_GPR246
    2654. 

  2654. - , HW_H_SYS_GPR247, HW_H_SYS_GPR248, HW_H_SYS_GPR249, HW_H_SYS_GPR250
    2655. 

  2655. - , HW_H_SYS_GPR251, HW_H_SYS_GPR252, HW_H_SYS_GPR253, HW_H_SYS_GPR254
    2656. 

  2656. - , HW_H_SYS_GPR255, HW_H_SYS_GPR256, HW_H_SYS_GPR257, HW_H_SYS_GPR258
    2657. 

  2657. - , HW_H_SYS_GPR259, HW_H_SYS_GPR260, HW_H_SYS_GPR261, HW_H_SYS_GPR262
    2658. 

  2658. - , HW_H_SYS_GPR263, HW_H_SYS_GPR264, HW_H_SYS_GPR265, HW_H_SYS_GPR266
    2659. 

  2659. - , HW_H_SYS_GPR267, HW_H_SYS_GPR268, HW_H_SYS_GPR269, HW_H_SYS_GPR270
    2660. 

  2660. - , HW_H_SYS_GPR271, HW_H_SYS_GPR272, HW_H_SYS_GPR273, HW_H_SYS_GPR274
    2661. 

  2661. - , HW_H_SYS_GPR275, HW_H_SYS_GPR276, HW_H_SYS_GPR277, HW_H_SYS_GPR278
    2662. 

  2662. - , HW_H_SYS_GPR279, HW_H_SYS_GPR280, HW_H_SYS_GPR281, HW_H_SYS_GPR282
    2663. 

  2663. - , HW_H_SYS_GPR283, HW_H_SYS_GPR284, HW_H_SYS_GPR285, HW_H_SYS_GPR286
    2664. 

  2664. - , HW_H_SYS_GPR287, HW_H_SYS_GPR288, HW_H_SYS_GPR289, HW_H_SYS_GPR290
    2665. 

  2665. - , HW_H_SYS_GPR291, HW_H_SYS_GPR292, HW_H_SYS_GPR293, HW_H_SYS_GPR294
    2666. 

  2666. - , HW_H_SYS_GPR295, HW_H_SYS_GPR296, HW_H_SYS_GPR297, HW_H_SYS_GPR298
    2667. 

  2667. - , HW_H_SYS_GPR299, HW_H_SYS_GPR300, HW_H_SYS_GPR301, HW_H_SYS_GPR302
    2668. 

  2668. - , HW_H_SYS_GPR303, HW_H_SYS_GPR304, HW_H_SYS_GPR305, HW_H_SYS_GPR306
    2669. 

  2669. - , HW_H_SYS_GPR307, HW_H_SYS_GPR308, HW_H_SYS_GPR309, HW_H_SYS_GPR310
    2670. 

  2670. - , HW_H_SYS_GPR311, HW_H_SYS_GPR312, HW_H_SYS_GPR313, HW_H_SYS_GPR314
    2671. 

  2671. - , HW_H_SYS_GPR315, HW_H_SYS_GPR316, HW_H_SYS_GPR317, HW_H_SYS_GPR318
    2672. 

  2672. - , HW_H_SYS_GPR319, HW_H_SYS_GPR320, HW_H_SYS_GPR321, HW_H_SYS_GPR322
    2673. 

  2673. - , HW_H_SYS_GPR323, HW_H_SYS_GPR324, HW_H_SYS_GPR325, HW_H_SYS_GPR326
    2674. 

  2674. - , HW_H_SYS_GPR327, HW_H_SYS_GPR328, HW_H_SYS_GPR329, HW_H_SYS_GPR330
    2675. 

  2675. - , HW_H_SYS_GPR331, HW_H_SYS_GPR332, HW_H_SYS_GPR333, HW_H_SYS_GPR334
    2676. 

  2676. - , HW_H_SYS_GPR335, HW_H_SYS_GPR336, HW_H_SYS_GPR337, HW_H_SYS_GPR338
    2677. 

  2677. - , HW_H_SYS_GPR339, HW_H_SYS_GPR340, HW_H_SYS_GPR341, HW_H_SYS_GPR342
    2678. 

  2678. - , HW_H_SYS_GPR343, HW_H_SYS_GPR344, HW_H_SYS_GPR345, HW_H_SYS_GPR346
    2679. 

  2679. - , HW_H_SYS_GPR347, HW_H_SYS_GPR348, HW_H_SYS_GPR349, HW_H_SYS_GPR350
    2680. 

  2680. - , HW_H_SYS_GPR351, HW_H_SYS_GPR352, HW_H_SYS_GPR353, HW_H_SYS_GPR354
    2681. 

  2681. - , HW_H_SYS_GPR355, HW_H_SYS_GPR356, HW_H_SYS_GPR357, HW_H_SYS_GPR358
    2682. 

  2682. - , HW_H_SYS_GPR359, HW_H_SYS_GPR360, HW_H_SYS_GPR361, HW_H_SYS_GPR362
    2683. 

  2683. - , HW_H_SYS_GPR363, HW_H_SYS_GPR364, HW_H_SYS_GPR365, HW_H_SYS_GPR366
    2684. 

  2684. - , HW_H_SYS_GPR367, HW_H_SYS_GPR368, HW_H_SYS_GPR369, HW_H_SYS_GPR370
    2685. 

  2685. - , HW_H_SYS_GPR371, HW_H_SYS_GPR372, HW_H_SYS_GPR373, HW_H_SYS_GPR374
    2686. 

  2686. - , HW_H_SYS_GPR375, HW_H_SYS_GPR376, HW_H_SYS_GPR377, HW_H_SYS_GPR378
    2687. 

  2687. - , HW_H_SYS_GPR379, HW_H_SYS_GPR380, HW_H_SYS_GPR381, HW_H_SYS_GPR382
    2688. 

  2688. - , HW_H_SYS_GPR383, HW_H_SYS_GPR384, HW_H_SYS_GPR385, HW_H_SYS_GPR386
    2689. 

  2689. - , HW_H_SYS_GPR387, HW_H_SYS_GPR388, HW_H_SYS_GPR389, HW_H_SYS_GPR390
    2690. 

  2690. - , HW_H_SYS_GPR391, HW_H_SYS_GPR392, HW_H_SYS_GPR393, HW_H_SYS_GPR394
    2691. 

  2691. - , HW_H_SYS_GPR395, HW_H_SYS_GPR396, HW_H_SYS_GPR397, HW_H_SYS_GPR398
    2692. 

  2692. - , HW_H_SYS_GPR399, HW_H_SYS_GPR400, HW_H_SYS_GPR401, HW_H_SYS_GPR402
    2693. 

  2693. - , HW_H_SYS_GPR403, HW_H_SYS_GPR404, HW_H_SYS_GPR405, HW_H_SYS_GPR406
    2694. 

  2694. - , HW_H_SYS_GPR407, HW_H_SYS_GPR408, HW_H_SYS_GPR409, HW_H_SYS_GPR410
    2695. 

  2695. - , HW_H_SYS_GPR411, HW_H_SYS_GPR412, HW_H_SYS_GPR413, HW_H_SYS_GPR414
    2696. 

  2696. - , HW_H_SYS_GPR415, HW_H_SYS_GPR416, HW_H_SYS_GPR417, HW_H_SYS_GPR418
    2697. 

  2697. - , HW_H_SYS_GPR419, HW_H_SYS_GPR420, HW_H_SYS_GPR421, HW_H_SYS_GPR422
    2698. 

  2698. - , HW_H_SYS_GPR423, HW_H_SYS_GPR424, HW_H_SYS_GPR425, HW_H_SYS_GPR426
    2699. 

  2699. - , HW_H_SYS_GPR427, HW_H_SYS_GPR428, HW_H_SYS_GPR429, HW_H_SYS_GPR430
    2700. 

  2700. - , HW_H_SYS_GPR431, HW_H_SYS_GPR432, HW_H_SYS_GPR433, HW_H_SYS_GPR434
    2701. 

  2701. - , HW_H_SYS_GPR435, HW_H_SYS_GPR436, HW_H_SYS_GPR437, HW_H_SYS_GPR438
    2702. 

  2702. - , HW_H_SYS_GPR439, HW_H_SYS_GPR440, HW_H_SYS_GPR441, HW_H_SYS_GPR442
    2703. 

  2703. - , HW_H_SYS_GPR443, HW_H_SYS_GPR444, HW_H_SYS_GPR445, HW_H_SYS_GPR446
    2704. 

  2704. - , HW_H_SYS_GPR447, HW_H_SYS_GPR448, HW_H_SYS_GPR449, HW_H_SYS_GPR450
    2705. 

  2705. - , HW_H_SYS_GPR451, HW_H_SYS_GPR452, HW_H_SYS_GPR453, HW_H_SYS_GPR454
    2706. 

  2706. - , HW_H_SYS_GPR455, HW_H_SYS_GPR456, HW_H_SYS_GPR457, HW_H_SYS_GPR458
    2707. 

  2707. - , HW_H_SYS_GPR459, HW_H_SYS_GPR460, HW_H_SYS_GPR461, HW_H_SYS_GPR462
    2708. 

  2708. - , HW_H_SYS_GPR463, HW_H_SYS_GPR464, HW_H_SYS_GPR465, HW_H_SYS_GPR466
    2709. 

  2709. - , HW_H_SYS_GPR467, HW_H_SYS_GPR468, HW_H_SYS_GPR469, HW_H_SYS_GPR470
    2710. 

  2710. - , HW_H_SYS_GPR471, HW_H_SYS_GPR472, HW_H_SYS_GPR473, HW_H_SYS_GPR474
    2711. 

  2711. - , HW_H_SYS_GPR475, HW_H_SYS_GPR476, HW_H_SYS_GPR477, HW_H_SYS_GPR478
    2712. 

  2712. - , HW_H_SYS_GPR479, HW_H_SYS_GPR480, HW_H_SYS_GPR481, HW_H_SYS_GPR482
    2713. 

  2713. - , HW_H_SYS_GPR483, HW_H_SYS_GPR484, HW_H_SYS_GPR485, HW_H_SYS_GPR486
    2714. 

  2714. - , HW_H_SYS_GPR487, HW_H_SYS_GPR488, HW_H_SYS_GPR489, HW_H_SYS_GPR490
    2715. 

  2715. - , HW_H_SYS_GPR491, HW_H_SYS_GPR492, HW_H_SYS_GPR493, HW_H_SYS_GPR494
    2716. 

  2716. - , HW_H_SYS_GPR495, HW_H_SYS_GPR496, HW_H_SYS_GPR497, HW_H_SYS_GPR498
    2717. 

  2717. - , HW_H_SYS_GPR499, HW_H_SYS_GPR500, HW_H_SYS_GPR501, HW_H_SYS_GPR502
    2718. 

  2718. - , HW_H_SYS_GPR503, HW_H_SYS_GPR504, HW_H_SYS_GPR505, HW_H_SYS_GPR506
    2719. 

  2719. - , HW_H_SYS_GPR507, HW_H_SYS_GPR508, HW_H_SYS_GPR509, HW_H_SYS_GPR510
    2720. 

  2720. - , HW_H_SYS_GPR511, HW_H_MAC_MACLO, HW_H_MAC_MACHI, HW_H_TICK_TTMR
    2721. 

  2721. - , HW_H_SYS_VR_REV, HW_H_SYS_VR_CFG, HW_H_SYS_VR_VER, HW_H_SYS_UPR_UP
    2722. 

  2722. - , HW_H_SYS_UPR_DCP, HW_H_SYS_UPR_ICP, HW_H_SYS_UPR_DMP, HW_H_SYS_UPR_MP
    2723. 

  2723. - , HW_H_SYS_UPR_IMP, HW_H_SYS_UPR_DUP, HW_H_SYS_UPR_PCUP, HW_H_SYS_UPR_PICP
    2724. 

  2724. - , HW_H_SYS_UPR_PMP, HW_H_SYS_UPR_TTP, HW_H_SYS_UPR_CUP, HW_H_SYS_CPUCFGR_NSGR
    2725. 

  2725. - , HW_H_SYS_CPUCFGR_CGF, HW_H_SYS_CPUCFGR_OB32S, HW_H_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OF32S
    2726. 

  2726. - , HW_H_SYS_CPUCFGR_OF64S, HW_H_SYS_CPUCFGR_OV64S, HW_H_SYS_CPUCFGR_ND, HW_H_SYS_SR_SM
    2727. 

  2727. - , HW_H_SYS_SR_TEE, HW_H_SYS_SR_IEE, HW_H_SYS_SR_DCE, HW_H_SYS_SR_ICE
    2728. 

  2728. - , HW_H_SYS_SR_DME, HW_H_SYS_SR_IME, HW_H_SYS_SR_LEE, HW_H_SYS_SR_CE
    2729. 

  2729. - , HW_H_SYS_SR_F, HW_H_SYS_SR_CY, HW_H_SYS_SR_OV, HW_H_SYS_SR_OVE
    2730. 

  2730. - , HW_H_SYS_SR_DSX, HW_H_SYS_SR_EPH, HW_H_SYS_SR_FO, HW_H_SYS_SR_SUMRA
    2731. 

  2731. - , HW_H_SYS_SR_CID, HW_H_SYS_FPCSR_FPEE, HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF
    2732. 

  2732. - , HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF, HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF
    2733. 

  2733. - , HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF, HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF
    2734. 

  2734. - , HW_H_SIMM16, HW_H_UIMM16, HW_H_UIMM6, HW_H_ATOMIC_RESERVE
    2735. 

  2735. - , HW_H_ATOMIC_ADDRESS, HW_H_ROFF1, HW_MAX
    2736. 

  2736. + , HW_H_FSR, HW_H_FD32R, HW_H_I64R, HW_H_SYS_VR
    2737. 

  2737. + , HW_H_SYS_UPR, HW_H_SYS_CPUCFGR, HW_H_SYS_DMMUCFGR, HW_H_SYS_IMMUCFGR
    2738. 

  2738. + , HW_H_SYS_DCCFGR, HW_H_SYS_ICCFGR, HW_H_SYS_DCFGR, HW_H_SYS_PCCFGR
    2739. 

  2739. + , HW_H_SYS_NPC, HW_H_SYS_SR, HW_H_SYS_PPC, HW_H_SYS_FPCSR
    2740. 

  2740. + , HW_H_SYS_EPCR0, HW_H_SYS_EPCR1, HW_H_SYS_EPCR2, HW_H_SYS_EPCR3
    2741. 

  2741. + , HW_H_SYS_EPCR4, HW_H_SYS_EPCR5, HW_H_SYS_EPCR6, HW_H_SYS_EPCR7
    2742. 

  2742. + , HW_H_SYS_EPCR8, HW_H_SYS_EPCR9, HW_H_SYS_EPCR10, HW_H_SYS_EPCR11
    2743. 

  2743. + , HW_H_SYS_EPCR12, HW_H_SYS_EPCR13, HW_H_SYS_EPCR14, HW_H_SYS_EPCR15
    2744. 

  2744. + , HW_H_SYS_EEAR0, HW_H_SYS_EEAR1, HW_H_SYS_EEAR2, HW_H_SYS_EEAR3
    2745. 

  2745. + , HW_H_SYS_EEAR4, HW_H_SYS_EEAR5, HW_H_SYS_EEAR6, HW_H_SYS_EEAR7
    2746. 

  2746. + , HW_H_SYS_EEAR8, HW_H_SYS_EEAR9, HW_H_SYS_EEAR10, HW_H_SYS_EEAR11
    2747. 

  2747. + , HW_H_SYS_EEAR12, HW_H_SYS_EEAR13, HW_H_SYS_EEAR14, HW_H_SYS_EEAR15
    2748. 

  2748. + , HW_H_SYS_ESR0, HW_H_SYS_ESR1, HW_H_SYS_ESR2, HW_H_SYS_ESR3
    2749. 

  2749. + , HW_H_SYS_ESR4, HW_H_SYS_ESR5, HW_H_SYS_ESR6, HW_H_SYS_ESR7
    2750. 

  2750. + , HW_H_SYS_ESR8, HW_H_SYS_ESR9, HW_H_SYS_ESR10, HW_H_SYS_ESR11
    2751. 

  2751. + , HW_H_SYS_ESR12, HW_H_SYS_ESR13, HW_H_SYS_ESR14, HW_H_SYS_ESR15
    2752. 

  2752. + , HW_H_SYS_GPR0, HW_H_SYS_GPR1, HW_H_SYS_GPR2, HW_H_SYS_GPR3
    2753. 

  2753. + , HW_H_SYS_GPR4, HW_H_SYS_GPR5, HW_H_SYS_GPR6, HW_H_SYS_GPR7
    2754. 

  2754. + , HW_H_SYS_GPR8, HW_H_SYS_GPR9, HW_H_SYS_GPR10, HW_H_SYS_GPR11
    2755. 

  2755. + , HW_H_SYS_GPR12, HW_H_SYS_GPR13, HW_H_SYS_GPR14, HW_H_SYS_GPR15
    2756. 

  2756. + , HW_H_SYS_GPR16, HW_H_SYS_GPR17, HW_H_SYS_GPR18, HW_H_SYS_GPR19
    2757. 

  2757. + , HW_H_SYS_GPR20, HW_H_SYS_GPR21, HW_H_SYS_GPR22, HW_H_SYS_GPR23
    2758. 

  2758. + , HW_H_SYS_GPR24, HW_H_SYS_GPR25, HW_H_SYS_GPR26, HW_H_SYS_GPR27
    2759. 

  2759. + , HW_H_SYS_GPR28, HW_H_SYS_GPR29, HW_H_SYS_GPR30, HW_H_SYS_GPR31
    2760. 

  2760. + , HW_H_SYS_GPR32, HW_H_SYS_GPR33, HW_H_SYS_GPR34, HW_H_SYS_GPR35
    2761. 

  2761. + , HW_H_SYS_GPR36, HW_H_SYS_GPR37, HW_H_SYS_GPR38, HW_H_SYS_GPR39
    2762. 

  2762. + , HW_H_SYS_GPR40, HW_H_SYS_GPR41, HW_H_SYS_GPR42, HW_H_SYS_GPR43
    2763. 

  2763. + , HW_H_SYS_GPR44, HW_H_SYS_GPR45, HW_H_SYS_GPR46, HW_H_SYS_GPR47
    2764. 

  2764. + , HW_H_SYS_GPR48, HW_H_SYS_GPR49, HW_H_SYS_GPR50, HW_H_SYS_GPR51
    2765. 

  2765. + , HW_H_SYS_GPR52, HW_H_SYS_GPR53, HW_H_SYS_GPR54, HW_H_SYS_GPR55
    2766. 

  2766. + , HW_H_SYS_GPR56, HW_H_SYS_GPR57, HW_H_SYS_GPR58, HW_H_SYS_GPR59
    2767. 

  2767. + , HW_H_SYS_GPR60, HW_H_SYS_GPR61, HW_H_SYS_GPR62, HW_H_SYS_GPR63
    2768. 

  2768. + , HW_H_SYS_GPR64, HW_H_SYS_GPR65, HW_H_SYS_GPR66, HW_H_SYS_GPR67
    2769. 

  2769. + , HW_H_SYS_GPR68, HW_H_SYS_GPR69, HW_H_SYS_GPR70, HW_H_SYS_GPR71
    2770. 

  2770. + , HW_H_SYS_GPR72, HW_H_SYS_GPR73, HW_H_SYS_GPR74, HW_H_SYS_GPR75
    2771. 

  2771. + , HW_H_SYS_GPR76, HW_H_SYS_GPR77, HW_H_SYS_GPR78, HW_H_SYS_GPR79
    2772. 

  2772. + , HW_H_SYS_GPR80, HW_H_SYS_GPR81, HW_H_SYS_GPR82, HW_H_SYS_GPR83
    2773. 

  2773. + , HW_H_SYS_GPR84, HW_H_SYS_GPR85, HW_H_SYS_GPR86, HW_H_SYS_GPR87
    2774. 

  2774. + , HW_H_SYS_GPR88, HW_H_SYS_GPR89, HW_H_SYS_GPR90, HW_H_SYS_GPR91
    2775. 

  2775. + , HW_H_SYS_GPR92, HW_H_SYS_GPR93, HW_H_SYS_GPR94, HW_H_SYS_GPR95
    2776. 

  2776. + , HW_H_SYS_GPR96, HW_H_SYS_GPR97, HW_H_SYS_GPR98, HW_H_SYS_GPR99
    2777. 

  2777. + , HW_H_SYS_GPR100, HW_H_SYS_GPR101, HW_H_SYS_GPR102, HW_H_SYS_GPR103
    2778. 

  2778. + , HW_H_SYS_GPR104, HW_H_SYS_GPR105, HW_H_SYS_GPR106, HW_H_SYS_GPR107
    2779. 

  2779. + , HW_H_SYS_GPR108, HW_H_SYS_GPR109, HW_H_SYS_GPR110, HW_H_SYS_GPR111
    2780. 

  2780. + , HW_H_SYS_GPR112, HW_H_SYS_GPR113, HW_H_SYS_GPR114, HW_H_SYS_GPR115
    2781. 

  2781. + , HW_H_SYS_GPR116, HW_H_SYS_GPR117, HW_H_SYS_GPR118, HW_H_SYS_GPR119
    2782. 

  2782. + , HW_H_SYS_GPR120, HW_H_SYS_GPR121, HW_H_SYS_GPR122, HW_H_SYS_GPR123
    2783. 

  2783. + , HW_H_SYS_GPR124, HW_H_SYS_GPR125, HW_H_SYS_GPR126, HW_H_SYS_GPR127
    2784. 

  2784. + , HW_H_SYS_GPR128, HW_H_SYS_GPR129, HW_H_SYS_GPR130, HW_H_SYS_GPR131
    2785. 

  2785. + , HW_H_SYS_GPR132, HW_H_SYS_GPR133, HW_H_SYS_GPR134, HW_H_SYS_GPR135
    2786. 

  2786. + , HW_H_SYS_GPR136, HW_H_SYS_GPR137, HW_H_SYS_GPR138, HW_H_SYS_GPR139
    2787. 

  2787. + , HW_H_SYS_GPR140, HW_H_SYS_GPR141, HW_H_SYS_GPR142, HW_H_SYS_GPR143
    2788. 

  2788. + , HW_H_SYS_GPR144, HW_H_SYS_GPR145, HW_H_SYS_GPR146, HW_H_SYS_GPR147
    2789. 

  2789. + , HW_H_SYS_GPR148, HW_H_SYS_GPR149, HW_H_SYS_GPR150, HW_H_SYS_GPR151
    2790. 

  2790. + , HW_H_SYS_GPR152, HW_H_SYS_GPR153, HW_H_SYS_GPR154, HW_H_SYS_GPR155
    2791. 

  2791. + , HW_H_SYS_GPR156, HW_H_SYS_GPR157, HW_H_SYS_GPR158, HW_H_SYS_GPR159
    2792. 

  2792. + , HW_H_SYS_GPR160, HW_H_SYS_GPR161, HW_H_SYS_GPR162, HW_H_SYS_GPR163
    2793. 

  2793. + , HW_H_SYS_GPR164, HW_H_SYS_GPR165, HW_H_SYS_GPR166, HW_H_SYS_GPR167
    2794. 

  2794. + , HW_H_SYS_GPR168, HW_H_SYS_GPR169, HW_H_SYS_GPR170, HW_H_SYS_GPR171
    2795. 

  2795. + , HW_H_SYS_GPR172, HW_H_SYS_GPR173, HW_H_SYS_GPR174, HW_H_SYS_GPR175
    2796. 

  2796. + , HW_H_SYS_GPR176, HW_H_SYS_GPR177, HW_H_SYS_GPR178, HW_H_SYS_GPR179
    2797. 

  2797. + , HW_H_SYS_GPR180, HW_H_SYS_GPR181, HW_H_SYS_GPR182, HW_H_SYS_GPR183
    2798. 

  2798. + , HW_H_SYS_GPR184, HW_H_SYS_GPR185, HW_H_SYS_GPR186, HW_H_SYS_GPR187
    2799. 

  2799. + , HW_H_SYS_GPR188, HW_H_SYS_GPR189, HW_H_SYS_GPR190, HW_H_SYS_GPR191
    2800. 

  2800. + , HW_H_SYS_GPR192, HW_H_SYS_GPR193, HW_H_SYS_GPR194, HW_H_SYS_GPR195
    2801. 

  2801. + , HW_H_SYS_GPR196, HW_H_SYS_GPR197, HW_H_SYS_GPR198, HW_H_SYS_GPR199
    2802. 

  2802. + , HW_H_SYS_GPR200, HW_H_SYS_GPR201, HW_H_SYS_GPR202, HW_H_SYS_GPR203
    2803. 

  2803. + , HW_H_SYS_GPR204, HW_H_SYS_GPR205, HW_H_SYS_GPR206, HW_H_SYS_GPR207
    2804. 

  2804. + , HW_H_SYS_GPR208, HW_H_SYS_GPR209, HW_H_SYS_GPR210, HW_H_SYS_GPR211
    2805. 

  2805. + , HW_H_SYS_GPR212, HW_H_SYS_GPR213, HW_H_SYS_GPR214, HW_H_SYS_GPR215
    2806. 

  2806. + , HW_H_SYS_GPR216, HW_H_SYS_GPR217, HW_H_SYS_GPR218, HW_H_SYS_GPR219
    2807. 

  2807. + , HW_H_SYS_GPR220, HW_H_SYS_GPR221, HW_H_SYS_GPR222, HW_H_SYS_GPR223
    2808. 

  2808. + , HW_H_SYS_GPR224, HW_H_SYS_GPR225, HW_H_SYS_GPR226, HW_H_SYS_GPR227
    2809. 

  2809. + , HW_H_SYS_GPR228, HW_H_SYS_GPR229, HW_H_SYS_GPR230, HW_H_SYS_GPR231
    2810. 

  2810. + , HW_H_SYS_GPR232, HW_H_SYS_GPR233, HW_H_SYS_GPR234, HW_H_SYS_GPR235
    2811. 

  2811. + , HW_H_SYS_GPR236, HW_H_SYS_GPR237, HW_H_SYS_GPR238, HW_H_SYS_GPR239
    2812. 

  2812. + , HW_H_SYS_GPR240, HW_H_SYS_GPR241, HW_H_SYS_GPR242, HW_H_SYS_GPR243
    2813. 

  2813. + , HW_H_SYS_GPR244, HW_H_SYS_GPR245, HW_H_SYS_GPR246, HW_H_SYS_GPR247
    2814. 

  2814. + , HW_H_SYS_GPR248, HW_H_SYS_GPR249, HW_H_SYS_GPR250, HW_H_SYS_GPR251
    2815. 

  2815. + , HW_H_SYS_GPR252, HW_H_SYS_GPR253, HW_H_SYS_GPR254, HW_H_SYS_GPR255
    2816. 

  2816. + , HW_H_SYS_GPR256, HW_H_SYS_GPR257, HW_H_SYS_GPR258, HW_H_SYS_GPR259
    2817. 

  2817. + , HW_H_SYS_GPR260, HW_H_SYS_GPR261, HW_H_SYS_GPR262, HW_H_SYS_GPR263
    2818. 

  2818. + , HW_H_SYS_GPR264, HW_H_SYS_GPR265, HW_H_SYS_GPR266, HW_H_SYS_GPR267
    2819. 

  2819. + , HW_H_SYS_GPR268, HW_H_SYS_GPR269, HW_H_SYS_GPR270, HW_H_SYS_GPR271
    2820. 

  2820. + , HW_H_SYS_GPR272, HW_H_SYS_GPR273, HW_H_SYS_GPR274, HW_H_SYS_GPR275
    2821. 

  2821. + , HW_H_SYS_GPR276, HW_H_SYS_GPR277, HW_H_SYS_GPR278, HW_H_SYS_GPR279
    2822. 

  2822. + , HW_H_SYS_GPR280, HW_H_SYS_GPR281, HW_H_SYS_GPR282, HW_H_SYS_GPR283
    2823. 

  2823. + , HW_H_SYS_GPR284, HW_H_SYS_GPR285, HW_H_SYS_GPR286, HW_H_SYS_GPR287
    2824. 

  2824. + , HW_H_SYS_GPR288, HW_H_SYS_GPR289, HW_H_SYS_GPR290, HW_H_SYS_GPR291
    2825. 

  2825. + , HW_H_SYS_GPR292, HW_H_SYS_GPR293, HW_H_SYS_GPR294, HW_H_SYS_GPR295
    2826. 

  2826. + , HW_H_SYS_GPR296, HW_H_SYS_GPR297, HW_H_SYS_GPR298, HW_H_SYS_GPR299
    2827. 

  2827. + , HW_H_SYS_GPR300, HW_H_SYS_GPR301, HW_H_SYS_GPR302, HW_H_SYS_GPR303
    2828. 

  2828. + , HW_H_SYS_GPR304, HW_H_SYS_GPR305, HW_H_SYS_GPR306, HW_H_SYS_GPR307
    2829. 

  2829. + , HW_H_SYS_GPR308, HW_H_SYS_GPR309, HW_H_SYS_GPR310, HW_H_SYS_GPR311
    2830. 

  2830. + , HW_H_SYS_GPR312, HW_H_SYS_GPR313, HW_H_SYS_GPR314, HW_H_SYS_GPR315
    2831. 

  2831. + , HW_H_SYS_GPR316, HW_H_SYS_GPR317, HW_H_SYS_GPR318, HW_H_SYS_GPR319
    2832. 

  2832. + , HW_H_SYS_GPR320, HW_H_SYS_GPR321, HW_H_SYS_GPR322, HW_H_SYS_GPR323
    2833. 

  2833. + , HW_H_SYS_GPR324, HW_H_SYS_GPR325, HW_H_SYS_GPR326, HW_H_SYS_GPR327
    2834. 

  2834. + , HW_H_SYS_GPR328, HW_H_SYS_GPR329, HW_H_SYS_GPR330, HW_H_SYS_GPR331
    2835. 

  2835. + , HW_H_SYS_GPR332, HW_H_SYS_GPR333, HW_H_SYS_GPR334, HW_H_SYS_GPR335
    2836. 

  2836. + , HW_H_SYS_GPR336, HW_H_SYS_GPR337, HW_H_SYS_GPR338, HW_H_SYS_GPR339
    2837. 

  2837. + , HW_H_SYS_GPR340, HW_H_SYS_GPR341, HW_H_SYS_GPR342, HW_H_SYS_GPR343
    2838. 

  2838. + , HW_H_SYS_GPR344, HW_H_SYS_GPR345, HW_H_SYS_GPR346, HW_H_SYS_GPR347
    2839. 

  2839. + , HW_H_SYS_GPR348, HW_H_SYS_GPR349, HW_H_SYS_GPR350, HW_H_SYS_GPR351
    2840. 

  2840. + , HW_H_SYS_GPR352, HW_H_SYS_GPR353, HW_H_SYS_GPR354, HW_H_SYS_GPR355
    2841. 

  2841. + , HW_H_SYS_GPR356, HW_H_SYS_GPR357, HW_H_SYS_GPR358, HW_H_SYS_GPR359
    2842. 

  2842. + , HW_H_SYS_GPR360, HW_H_SYS_GPR361, HW_H_SYS_GPR362, HW_H_SYS_GPR363
    2843. 

  2843. + , HW_H_SYS_GPR364, HW_H_SYS_GPR365, HW_H_SYS_GPR366, HW_H_SYS_GPR367
    2844. 

  2844. + , HW_H_SYS_GPR368, HW_H_SYS_GPR369, HW_H_SYS_GPR370, HW_H_SYS_GPR371
    2845. 

  2845. + , HW_H_SYS_GPR372, HW_H_SYS_GPR373, HW_H_SYS_GPR374, HW_H_SYS_GPR375
    2846. 

  2846. + , HW_H_SYS_GPR376, HW_H_SYS_GPR377, HW_H_SYS_GPR378, HW_H_SYS_GPR379
    2847. 

  2847. + , HW_H_SYS_GPR380, HW_H_SYS_GPR381, HW_H_SYS_GPR382, HW_H_SYS_GPR383
    2848. 

  2848. + , HW_H_SYS_GPR384, HW_H_SYS_GPR385, HW_H_SYS_GPR386, HW_H_SYS_GPR387
    2849. 

  2849. + , HW_H_SYS_GPR388, HW_H_SYS_GPR389, HW_H_SYS_GPR390, HW_H_SYS_GPR391
    2850. 

  2850. + , HW_H_SYS_GPR392, HW_H_SYS_GPR393, HW_H_SYS_GPR394, HW_H_SYS_GPR395
    2851. 

  2851. + , HW_H_SYS_GPR396, HW_H_SYS_GPR397, HW_H_SYS_GPR398, HW_H_SYS_GPR399
    2852. 

  2852. + , HW_H_SYS_GPR400, HW_H_SYS_GPR401, HW_H_SYS_GPR402, HW_H_SYS_GPR403
    2853. 

  2853. + , HW_H_SYS_GPR404, HW_H_SYS_GPR405, HW_H_SYS_GPR406, HW_H_SYS_GPR407
    2854. 

  2854. + , HW_H_SYS_GPR408, HW_H_SYS_GPR409, HW_H_SYS_GPR410, HW_H_SYS_GPR411
    2855. 

  2855. + , HW_H_SYS_GPR412, HW_H_SYS_GPR413, HW_H_SYS_GPR414, HW_H_SYS_GPR415
    2856. 

  2856. + , HW_H_SYS_GPR416, HW_H_SYS_GPR417, HW_H_SYS_GPR418, HW_H_SYS_GPR419
    2857. 

  2857. + , HW_H_SYS_GPR420, HW_H_SYS_GPR421, HW_H_SYS_GPR422, HW_H_SYS_GPR423
    2858. 

  2858. + , HW_H_SYS_GPR424, HW_H_SYS_GPR425, HW_H_SYS_GPR426, HW_H_SYS_GPR427
    2859. 

  2859. + , HW_H_SYS_GPR428, HW_H_SYS_GPR429, HW_H_SYS_GPR430, HW_H_SYS_GPR431
    2860. 

  2860. + , HW_H_SYS_GPR432, HW_H_SYS_GPR433, HW_H_SYS_GPR434, HW_H_SYS_GPR435
    2861. 

  2861. + , HW_H_SYS_GPR436, HW_H_SYS_GPR437, HW_H_SYS_GPR438, HW_H_SYS_GPR439
    2862. 

  2862. + , HW_H_SYS_GPR440, HW_H_SYS_GPR441, HW_H_SYS_GPR442, HW_H_SYS_GPR443
    2863. 

  2863. + , HW_H_SYS_GPR444, HW_H_SYS_GPR445, HW_H_SYS_GPR446, HW_H_SYS_GPR447
    2864. 

  2864. + , HW_H_SYS_GPR448, HW_H_SYS_GPR449, HW_H_SYS_GPR450, HW_H_SYS_GPR451
    2865. 

  2865. + , HW_H_SYS_GPR452, HW_H_SYS_GPR453, HW_H_SYS_GPR454, HW_H_SYS_GPR455
    2866. 

  2866. + , HW_H_SYS_GPR456, HW_H_SYS_GPR457, HW_H_SYS_GPR458, HW_H_SYS_GPR459
    2867. 

  2867. + , HW_H_SYS_GPR460, HW_H_SYS_GPR461, HW_H_SYS_GPR462, HW_H_SYS_GPR463
    2868. 

  2868. + , HW_H_SYS_GPR464, HW_H_SYS_GPR465, HW_H_SYS_GPR466, HW_H_SYS_GPR467
    2869. 

  2869. + , HW_H_SYS_GPR468, HW_H_SYS_GPR469, HW_H_SYS_GPR470, HW_H_SYS_GPR471
    2870. 

  2870. + , HW_H_SYS_GPR472, HW_H_SYS_GPR473, HW_H_SYS_GPR474, HW_H_SYS_GPR475
    2871. 

  2871. + , HW_H_SYS_GPR476, HW_H_SYS_GPR477, HW_H_SYS_GPR478, HW_H_SYS_GPR479
    2872. 

  2872. + , HW_H_SYS_GPR480, HW_H_SYS_GPR481, HW_H_SYS_GPR482, HW_H_SYS_GPR483
    2873. 

  2873. + , HW_H_SYS_GPR484, HW_H_SYS_GPR485, HW_H_SYS_GPR486, HW_H_SYS_GPR487
    2874. 

  2874. + , HW_H_SYS_GPR488, HW_H_SYS_GPR489, HW_H_SYS_GPR490, HW_H_SYS_GPR491
    2875. 

  2875. + , HW_H_SYS_GPR492, HW_H_SYS_GPR493, HW_H_SYS_GPR494, HW_H_SYS_GPR495
    2876. 

  2876. + , HW_H_SYS_GPR496, HW_H_SYS_GPR497, HW_H_SYS_GPR498, HW_H_SYS_GPR499
    2877. 

  2877. + , HW_H_SYS_GPR500, HW_H_SYS_GPR501, HW_H_SYS_GPR502, HW_H_SYS_GPR503
    2878. 

  2878. + , HW_H_SYS_GPR504, HW_H_SYS_GPR505, HW_H_SYS_GPR506, HW_H_SYS_GPR507
    2879. 

  2879. + , HW_H_SYS_GPR508, HW_H_SYS_GPR509, HW_H_SYS_GPR510, HW_H_SYS_GPR511
    2880. 

  2880. + , HW_H_MAC_MACLO, HW_H_MAC_MACHI, HW_H_TICK_TTMR, HW_H_SYS_VR_REV
    2881. 

  2881. + , HW_H_SYS_VR_CFG, HW_H_SYS_VR_VER, HW_H_SYS_UPR_UP, HW_H_SYS_UPR_DCP
    2882. 

  2882. + , HW_H_SYS_UPR_ICP, HW_H_SYS_UPR_DMP, HW_H_SYS_UPR_MP, HW_H_SYS_UPR_IMP
    2883. 

  2883. + , HW_H_SYS_UPR_DUP, HW_H_SYS_UPR_PCUP, HW_H_SYS_UPR_PICP, HW_H_SYS_UPR_PMP
    2884. 

  2884. + , HW_H_SYS_UPR_TTP, HW_H_SYS_UPR_CUP, HW_H_SYS_CPUCFGR_NSGR, HW_H_SYS_CPUCFGR_CGF
    2885. 

  2885. + , HW_H_SYS_CPUCFGR_OB32S, HW_H_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OF32S, HW_H_SYS_CPUCFGR_OF64S
    2886. 

  2886. + , HW_H_SYS_CPUCFGR_OV64S, HW_H_SYS_CPUCFGR_ND, HW_H_SYS_SR_SM, HW_H_SYS_SR_TEE
    2887. 

  2887. + , HW_H_SYS_SR_IEE, HW_H_SYS_SR_DCE, HW_H_SYS_SR_ICE, HW_H_SYS_SR_DME
    2888. 

  2888. + , HW_H_SYS_SR_IME, HW_H_SYS_SR_LEE, HW_H_SYS_SR_CE, HW_H_SYS_SR_F
    2889. 

  2889. + , HW_H_SYS_SR_CY, HW_H_SYS_SR_OV, HW_H_SYS_SR_OVE, HW_H_SYS_SR_DSX
    2890. 

  2890. + , HW_H_SYS_SR_EPH, HW_H_SYS_SR_FO, HW_H_SYS_SR_SUMRA, HW_H_SYS_SR_CID
    2891. 

  2891. + , HW_H_SYS_FPCSR_FPEE, HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF, HW_H_SYS_FPCSR_UNF
    2892. 

  2892. + , HW_H_SYS_FPCSR_SNF, HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF, HW_H_SYS_FPCSR_IXF
    2893. 

  2893. + , HW_H_SYS_FPCSR_IVF, HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF, HW_H_SIMM16
    2894. 

  2894. + , HW_H_UIMM16, HW_H_UIMM6, HW_H_ATOMIC_RESERVE, HW_H_ATOMIC_ADDRESS
    2895. 

  2895. + , HW_H_ROFF1, HW_MAX
    2896. 

  2896.  } CGEN_HW_TYPE;
    2897. 

  2897.  
    2898. 

  2898.  #define MAX_HW ((int) HW_MAX)
    2899. 

  2899. @@ -631,13 +629,12 @@ typedef enum cgen_operand_type {
    2900. 

  2900.   , OR1K_OPERAND_UIMM6, OR1K_OPERAND_RD, OR1K_OPERAND_RA, OR1K_OPERAND_RB
    2901. 

  2901.   , OR1K_OPERAND_DISP26, OR1K_OPERAND_DISP21, OR1K_OPERAND_SIMM16, OR1K_OPERAND_UIMM16
    2902. 

  2902.   , OR1K_OPERAND_SIMM16_SPLIT, OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF, OR1K_OPERAND_RASF
    2903. 

  2903. - , OR1K_OPERAND_RBSF, OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF, OR1K_OPERAND_RBDF
    2904. 

  2904. - , OR1K_OPERAND_RDD32F, OR1K_OPERAND_RDDI, OR1K_OPERAND_RAD32F, OR1K_OPERAND_RADI
    2905. 

  2905. - , OR1K_OPERAND_RBD32F, OR1K_OPERAND_RBDI, OR1K_OPERAND_MAX
    2906. 

  2906. + , OR1K_OPERAND_RBSF, OR1K_OPERAND_RDD32F, OR1K_OPERAND_RDDI, OR1K_OPERAND_RAD32F
    2907. 

  2907. + , OR1K_OPERAND_RADI, OR1K_OPERAND_RBD32F, OR1K_OPERAND_RBDI, OR1K_OPERAND_MAX
    2908. 

  2908.  } CGEN_OPERAND_TYPE;
    2909. 

  2909.  
    2910. 

  2910.  /* Number of operands types.  */
    2911. 

  2911. -#define MAX_OPERANDS 38
    2912. 

  2912. +#define MAX_OPERANDS 35
    2913. 

  2913.  
    2914. 

  2914.  /* Maximum number of operands referenced by any insn.  */
    2915. 

  2915.  #define MAX_OPERAND_INSTANCES 10
    2916. 

  2916. @@ -687,7 +684,6 @@ extern const CGEN_ATTR_TABLE or1k_cgen_insn_attr_table[];
    2917. 

  2917.  
    2918. 

  2918.  extern CGEN_KEYWORD or1k_cgen_opval_h_gpr;
    2919. 

  2919.  extern CGEN_KEYWORD or1k_cgen_opval_h_fsr;
    2920. 

  2920. -extern CGEN_KEYWORD or1k_cgen_opval_h_fdr;
    2921. 

  2921.  
    2922. 

  2922.  extern const CGEN_HW_ENTRY or1k_cgen_hw_table[];
    2923. 

  2923.  
    2924. 

  2924. diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c
    2925. 

  2925. index dce00b3f28..47c0a69843 100644
    2926. 

  2926. --- a/opcodes/or1k-dis.c
    2927. 

  2927. +++ b/opcodes/or1k-dis.c
    2928. 

  2928. @@ -123,9 +123,6 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
    2929. 

  2929.      case OR1K_OPERAND_RAD32F :
    2930. 

  2930.        print_regpair (cd, info, fields->f_rad32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
    2931. 

  2931.        break;
    2932. 

  2932. -    case OR1K_OPERAND_RADF :
    2933. 

  2933. -      print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r2, 0);
    2934. 

  2934. -      break;
    2935. 

  2935.      case OR1K_OPERAND_RADI :
    2936. 

  2936.        print_regpair (cd, info, fields->f_rad32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
    2937. 

  2937.        break;
    2938. 

  2938. @@ -138,9 +135,6 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
    2939. 

  2939.      case OR1K_OPERAND_RBD32F :
    2940. 

  2940.        print_regpair (cd, info, fields->f_rbd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
    2941. 

  2941.        break;
    2942. 

  2942. -    case OR1K_OPERAND_RBDF :
    2943. 

  2943. -      print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r3, 0);
    2944. 

  2944. -      break;
    2945. 

  2945.      case OR1K_OPERAND_RBDI :
    2946. 

  2946.        print_regpair (cd, info, fields->f_rbd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
    2947. 

  2947.        break;
    2948. 

  2948. @@ -153,9 +147,6 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
    2949. 

  2949.      case OR1K_OPERAND_RDD32F :
    2950. 

  2950.        print_regpair (cd, info, fields->f_rdd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
    2951. 

  2951.        break;
    2952. 

  2952. -    case OR1K_OPERAND_RDDF :
    2953. 

  2953. -      print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
    2954. 

  2954. -      break;
    2955. 

  2955.      case OR1K_OPERAND_RDDI :
    2956. 

  2956.        print_regpair (cd, info, fields->f_rdd32, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
    2957. 

  2957.        break;
    2958. 

  2958. diff --git a/opcodes/or1k-ibld.c b/opcodes/or1k-ibld.c
    2959. 

  2959. index 6271f5c6d1..936057354d 100644
    2960. 

  2960. --- a/opcodes/or1k-ibld.c
    2961. 

  2961. +++ b/opcodes/or1k-ibld.c
    2962. 

  2962. @@ -576,14 +576,14 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
    2963. 

  2963.      case OR1K_OPERAND_DISP21 :
    2964. 

  2964.        {
    2965. 

  2965.          long value = fields->f_disp21;
    2966. 

  2966. -        value = ((((DI) (value) >> (13))) - (((DI) (pc) >> (13))));
    2967. 

  2967. +        value = ((((SI) (value) >> (13))) - (((SI) (pc) >> (13))));
    2968. 

  2968.          errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, buffer);
    2969. 

  2969.        }
    2970. 

  2970.        break;
    2971. 

  2971.      case OR1K_OPERAND_DISP26 :
    2972. 

  2972.        {
    2973. 

  2973.          long value = fields->f_disp26;
    2974. 

  2974. -        value = ((DI) (((value) - (pc))) >> (2));
    2975. 

  2975. +        value = ((SI) (((value) - (pc))) >> (2));
    2976. 

  2976.          errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer);
    2977. 

  2977.        }
    2978. 

  2978.        break;
    2979. 

  2979. @@ -604,9 +604,6 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
    2980. 

  2980.            break;
    2981. 

  2981.        }
    2982. 

  2982.        break;
    2983. 

  2983. -    case OR1K_OPERAND_RADF :
    2984. 

  2984. -      errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
    2985. 

  2985. -      break;
    2986. 

  2986.      case OR1K_OPERAND_RADI :
    2987. 

  2987.        {
    2988. 

  2988.  {
    2989. 

  2989. @@ -641,9 +638,6 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
    2990. 

  2990.            break;
    2991. 

  2991.        }
    2992. 

  2992.        break;
    2993. 

  2993. -    case OR1K_OPERAND_RBDF :
    2994. 

  2994. -      errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
    2995. 

  2995. -      break;
    2996. 

  2996.      case OR1K_OPERAND_RBDI :
    2997. 

  2997.        {
    2998. 

  2998.  {
    2999. 

  2999. @@ -678,9 +672,6 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
    3000. 

  3000.            break;
    3001. 

  3001.        }
    3002. 

  3002.        break;
    3003. 

  3003. -    case OR1K_OPERAND_RDDF :
    3004. 

  3004. -      errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
    3005. 

  3005. -      break;
    3006. 

  3006.      case OR1K_OPERAND_RDDI :
    3007. 

  3007.        {
    3008. 

  3008.  {
    3009. 

  3009. @@ -783,7 +774,7 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
    3010. 

  3010.        {
    3011. 

  3011.          long value;
    3012. 

  3012.          length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value);
    3013. 

  3013. -        value = ((((value) + (((DI) (pc) >> (13))))) << (13));
    3014. 

  3014. +        value = ((((value) + (((SI) (pc) >> (13))))) << (13));
    3015. 

  3015.          fields->f_disp21 = value;
    3016. 

  3016.        }
    3017. 

  3017.        break;
    3018. 

  3018. @@ -807,9 +798,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
    3019. 

  3019.    FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5))));
    3020. 

  3020.        }
    3021. 

  3021.        break;
    3022. 

  3022. -    case OR1K_OPERAND_RADF :
    3023. 

  3023. -      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
    3024. 

  3024. -      break;
    3025. 

  3025.      case OR1K_OPERAND_RADI :
    3026. 

  3026.        {
    3027. 

  3027.          length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
    3028. 

  3028. @@ -834,9 +822,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
    3029. 

  3029.    FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5))));
    3030. 

  3030.        }
    3031. 

  3031.        break;
    3032. 

  3032. -    case OR1K_OPERAND_RBDF :
    3033. 

  3033. -      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
    3034. 

  3034. -      break;
    3035. 

  3035.      case OR1K_OPERAND_RBDI :
    3036. 

  3036.        {
    3037. 

  3037.          length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
    3038. 

  3038. @@ -861,9 +846,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
    3039. 

  3039.    FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5))));
    3040. 

  3040.        }
    3041. 

  3041.        break;
    3042. 

  3042. -    case OR1K_OPERAND_RDDF :
    3043. 

  3043. -      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
    3044. 

  3044. -      break;
    3045. 

  3045.      case OR1K_OPERAND_RDDI :
    3046. 

  3046.        {
    3047. 

  3047.          length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
    3048. 

  3048. @@ -954,9 +936,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3049. 

  3049.      case OR1K_OPERAND_RAD32F :
    3050. 

  3050.        value = fields->f_rad32;
    3051. 

  3051.        break;
    3052. 

  3052. -    case OR1K_OPERAND_RADF :
    3053. 

  3053. -      value = fields->f_r2;
    3054. 

  3054. -      break;
    3055. 

  3055.      case OR1K_OPERAND_RADI :
    3056. 

  3056.        value = fields->f_rad32;
    3057. 

  3057.        break;
    3058. 

  3058. @@ -969,9 +948,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3059. 

  3059.      case OR1K_OPERAND_RBD32F :
    3060. 

  3060.        value = fields->f_rbd32;
    3061. 

  3061.        break;
    3062. 

  3062. -    case OR1K_OPERAND_RBDF :
    3063. 

  3063. -      value = fields->f_r3;
    3064. 

  3064. -      break;
    3065. 

  3065.      case OR1K_OPERAND_RBDI :
    3066. 

  3066.        value = fields->f_rbd32;
    3067. 

  3067.        break;
    3068. 

  3068. @@ -984,9 +960,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3069. 

  3069.      case OR1K_OPERAND_RDD32F :
    3070. 

  3070.        value = fields->f_rdd32;
    3071. 

  3071.        break;
    3072. 

  3072. -    case OR1K_OPERAND_RDDF :
    3073. 

  3073. -      value = fields->f_r1;
    3074. 

  3074. -      break;
    3075. 

  3075.      case OR1K_OPERAND_RDDI :
    3076. 

  3076.        value = fields->f_rdd32;
    3077. 

  3077.        break;
    3078. 

  3078. @@ -1041,9 +1014,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3079. 

  3079.      case OR1K_OPERAND_RAD32F :
    3080. 

  3080.        value = fields->f_rad32;
    3081. 

  3081.        break;
    3082. 

  3082. -    case OR1K_OPERAND_RADF :
    3083. 

  3083. -      value = fields->f_r2;
    3084. 

  3084. -      break;
    3085. 

  3085.      case OR1K_OPERAND_RADI :
    3086. 

  3086.        value = fields->f_rad32;
    3087. 

  3087.        break;
    3088. 

  3088. @@ -1056,9 +1026,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3089. 

  3089.      case OR1K_OPERAND_RBD32F :
    3090. 

  3090.        value = fields->f_rbd32;
    3091. 

  3091.        break;
    3092. 

  3092. -    case OR1K_OPERAND_RBDF :
    3093. 

  3093. -      value = fields->f_r3;
    3094. 

  3094. -      break;
    3095. 

  3095.      case OR1K_OPERAND_RBDI :
    3096. 

  3096.        value = fields->f_rbd32;
    3097. 

  3097.        break;
    3098. 

  3098. @@ -1071,9 +1038,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3099. 

  3099.      case OR1K_OPERAND_RDD32F :
    3100. 

  3100.        value = fields->f_rdd32;
    3101. 

  3101.        break;
    3102. 

  3102. -    case OR1K_OPERAND_RDDF :
    3103. 

  3103. -      value = fields->f_r1;
    3104. 

  3104. -      break;
    3105. 

  3105.      case OR1K_OPERAND_RDDI :
    3106. 

  3106.        value = fields->f_rdd32;
    3107. 

  3107.        break;
    3108. 

  3108. @@ -1135,9 +1099,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3109. 

  3109.      case OR1K_OPERAND_RAD32F :
    3110. 

  3110.        fields->f_rad32 = value;
    3111. 

  3111.        break;
    3112. 

  3112. -    case OR1K_OPERAND_RADF :
    3113. 

  3113. -      fields->f_r2 = value;
    3114. 

  3114. -      break;
    3115. 

  3115.      case OR1K_OPERAND_RADI :
    3116. 

  3116.        fields->f_rad32 = value;
    3117. 

  3117.        break;
    3118. 

  3118. @@ -1150,9 +1111,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3119. 

  3119.      case OR1K_OPERAND_RBD32F :
    3120. 

  3120.        fields->f_rbd32 = value;
    3121. 

  3121.        break;
    3122. 

  3122. -    case OR1K_OPERAND_RBDF :
    3123. 

  3123. -      fields->f_r3 = value;
    3124. 

  3124. -      break;
    3125. 

  3125.      case OR1K_OPERAND_RBDI :
    3126. 

  3126.        fields->f_rbd32 = value;
    3127. 

  3127.        break;
    3128. 

  3128. @@ -1165,9 +1123,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3129. 

  3129.      case OR1K_OPERAND_RDD32F :
    3130. 

  3130.        fields->f_rdd32 = value;
    3131. 

  3131.        break;
    3132. 

  3132. -    case OR1K_OPERAND_RDDF :
    3133. 

  3133. -      fields->f_r1 = value;
    3134. 

  3134. -      break;
    3135. 

  3135.      case OR1K_OPERAND_RDDI :
    3136. 

  3136.        fields->f_rdd32 = value;
    3137. 

  3137.        break;
    3138. 

  3138. @@ -1219,9 +1174,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3139. 

  3139.      case OR1K_OPERAND_RAD32F :
    3140. 

  3140.        fields->f_rad32 = value;
    3141. 

  3141.        break;
    3142. 

  3142. -    case OR1K_OPERAND_RADF :
    3143. 

  3143. -      fields->f_r2 = value;
    3144. 

  3144. -      break;
    3145. 

  3145.      case OR1K_OPERAND_RADI :
    3146. 

  3146.        fields->f_rad32 = value;
    3147. 

  3147.        break;
    3148. 

  3148. @@ -1234,9 +1186,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3149. 

  3149.      case OR1K_OPERAND_RBD32F :
    3150. 

  3150.        fields->f_rbd32 = value;
    3151. 

  3151.        break;
    3152. 

  3152. -    case OR1K_OPERAND_RBDF :
    3153. 

  3153. -      fields->f_r3 = value;
    3154. 

  3154. -      break;
    3155. 

  3155.      case OR1K_OPERAND_RBDI :
    3156. 

  3156.        fields->f_rbd32 = value;
    3157. 

  3157.        break;
    3158. 

  3158. @@ -1249,9 +1198,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
    3159. 

  3159.      case OR1K_OPERAND_RDD32F :
    3160. 

  3160.        fields->f_rdd32 = value;
    3161. 

  3161.        break;
    3162. 

  3162. -    case OR1K_OPERAND_RDDF :
    3163. 

  3163. -      fields->f_r1 = value;
    3164. 

  3164. -      break;
    3165. 

  3165.      case OR1K_OPERAND_RDDI :
    3166. 

  3166.        fields->f_rdd32 = value;
    3167. 

  3167.        break;
    3168. 

  3168. diff --git a/opcodes/or1k-opc.c b/opcodes/or1k-opc.c
    3169. 

  3169. index 86e421099a..c390f85e52 100644
    3170. 

  3170. --- a/opcodes/or1k-opc.c
    3171. 

  3171. +++ b/opcodes/or1k-opc.c
    3172. 

  3172. @@ -163,10 +163,6 @@ static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED = {
    3173. 

  3173.    32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3174. 

  3174.  };
    3175. 

  3175.  
    3176. 

  3176. -static const CGEN_IFMT ifmt_lf_add_d ATTRIBUTE_UNUSED = {
    3177. 

  3177. -  32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3178. 

  3178. -};
    3179. 

  3179. -
    3180. 

  3180.  static const CGEN_IFMT ifmt_lf_add_d32 ATTRIBUTE_UNUSED = {
    3181. 

  3181.    32, 32, 0xfc0000ff, { { F (F_OPCODE) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } }
    3182. 

  3182.  };
    3183. 

  3183. @@ -175,10 +171,6 @@ static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED = {
    3184. 

  3184.    32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3185. 

  3185.  };
    3186. 

  3186.  
    3187. 

  3187. -static const CGEN_IFMT ifmt_lf_itof_d ATTRIBUTE_UNUSED = {
    3188. 

  3188. -  32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3189. 

  3189. -};
    3190. 

  3190. -
    3191. 

  3191.  static const CGEN_IFMT ifmt_lf_itof_d32 ATTRIBUTE_UNUSED = {
    3192. 

  3192.    32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } }
    3193. 

  3193.  };
    3194. 

  3194. @@ -187,10 +179,6 @@ static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED = {
    3195. 

  3195.    32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3196. 

  3196.  };
    3197. 

  3197.  
    3198. 

  3198. -static const CGEN_IFMT ifmt_lf_ftoi_d ATTRIBUTE_UNUSED = {
    3199. 

  3199. -  32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3200. 

  3200. -};
    3201. 

  3201. -
    3202. 

  3202.  static const CGEN_IFMT ifmt_lf_ftoi_d32 ATTRIBUTE_UNUSED = {
    3203. 

  3203.    32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } }
    3204. 

  3204.  };
    3205. 

  3205. @@ -199,10 +187,6 @@ static const CGEN_IFMT ifmt_lf_sfeq_s ATTRIBUTE_UNUSED = {
    3206. 

  3206.    32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3207. 

  3207.  };
    3208. 

  3208.  
    3209. 

  3209. -static const CGEN_IFMT ifmt_lf_sfeq_d ATTRIBUTE_UNUSED = {
    3210. 

  3210. -  32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3211. 

  3211. -};
    3212. 

  3212. -
    3213. 

  3213.  static const CGEN_IFMT ifmt_lf_sfeq_d32 ATTRIBUTE_UNUSED = {
    3214. 

  3214.    32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } }
    3215. 

  3215.  };
    3216. 

  3216. @@ -211,10 +195,6 @@ static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED = {
    3217. 

  3217.    32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3218. 

  3218.  };
    3219. 

  3219.  
    3220. 

  3220. -static const CGEN_IFMT ifmt_lf_cust1_d ATTRIBUTE_UNUSED = {
    3221. 

  3221. -  32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
    3222. 

  3222. -};
    3223. 

  3223. -
    3224. 

  3224.  static const CGEN_IFMT ifmt_lf_cust1_d32 ATTRIBUTE_UNUSED = {
    3225. 

  3225.    32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } }
    3226. 

  3226.  };
    3227. 

  3227. @@ -828,12 +808,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3228. 

  3228.      { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } },
    3229. 

  3229.      & ifmt_lf_add_s, { 0xc8000000 }
    3230. 

  3230.    },
    3231. 

  3231. -/* lf.add.d $rDDF,$rADF,$rBDF */
    3232. 

  3232. -  {
    3233. 

  3233. -    { 0, 0, 0, 0 },
    3234. 

  3234. -    { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
    3235. 

  3235. -    & ifmt_lf_add_d, { 0xc8000010 }
    3236. 

  3236. -  },
    3237. 

  3237.  /* lf.add.d $rDD32F,$rAD32F,$rBD32F */
    3238. 

  3238.    {
    3239. 

  3239.      { 0, 0, 0, 0 },
    3240. 

  3240. @@ -846,12 +820,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3241. 

  3241.      { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } },
    3242. 

  3242.      & ifmt_lf_add_s, { 0xc8000001 }
    3243. 

  3243.    },
    3244. 

  3244. -/* lf.sub.d $rDDF,$rADF,$rBDF */
    3245. 

  3245. -  {
    3246. 

  3246. -    { 0, 0, 0, 0 },
    3247. 

  3247. -    { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
    3248. 

  3248. -    & ifmt_lf_add_d, { 0xc8000011 }
    3249. 

  3249. -  },
    3250. 

  3250.  /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
    3251. 

  3251.    {
    3252. 

  3252.      { 0, 0, 0, 0 },
    3253. 

  3253. @@ -864,12 +832,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3254. 

  3254.      { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } },
    3255. 

  3255.      & ifmt_lf_add_s, { 0xc8000002 }
    3256. 

  3256.    },
    3257. 

  3257. -/* lf.mul.d $rDDF,$rADF,$rBDF */
    3258. 

  3258. -  {
    3259. 

  3259. -    { 0, 0, 0, 0 },
    3260. 

  3260. -    { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
    3261. 

  3261. -    & ifmt_lf_add_d, { 0xc8000012 }
    3262. 

  3262. -  },
    3263. 

  3263.  /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
    3264. 

  3264.    {
    3265. 

  3265.      { 0, 0, 0, 0 },
    3266. 

  3266. @@ -882,12 +844,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3267. 

  3267.      { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } },
    3268. 

  3268.      & ifmt_lf_add_s, { 0xc8000003 }
    3269. 

  3269.    },
    3270. 

  3270. -/* lf.div.d $rDDF,$rADF,$rBDF */
    3271. 

  3271. -  {
    3272. 

  3272. -    { 0, 0, 0, 0 },
    3273. 

  3273. -    { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
    3274. 

  3274. -    & ifmt_lf_add_d, { 0xc8000013 }
    3275. 

  3275. -  },
    3276. 

  3276.  /* lf.div.d $rDD32F,$rAD32F,$rBD32F */
    3277. 

  3277.    {
    3278. 

  3278.      { 0, 0, 0, 0 },
    3279. 

  3279. @@ -900,12 +856,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3280. 

  3280.      { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } },
    3281. 

  3281.      & ifmt_lf_add_s, { 0xc8000006 }
    3282. 

  3282.    },
    3283. 

  3283. -/* lf.rem.d $rDDF,$rADF,$rBDF */
    3284. 

  3284. -  {
    3285. 

  3285. -    { 0, 0, 0, 0 },
    3286. 

  3286. -    { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
    3287. 

  3287. -    & ifmt_lf_add_d, { 0xc8000016 }
    3288. 

  3288. -  },
    3289. 

  3289.  /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
    3290. 

  3290.    {
    3291. 

  3291.      { 0, 0, 0, 0 },
    3292. 

  3292. @@ -918,12 +868,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3293. 

  3293.      { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } },
    3294. 

  3294.      & ifmt_lf_itof_s, { 0xc8000004 }
    3295. 

  3295.    },
    3296. 

  3296. -/* lf.itof.d $rDDF,$rA */
    3297. 

  3297. -  {
    3298. 

  3298. -    { 0, 0, 0, 0 },
    3299. 

  3299. -    { { MNEM, ' ', OP (RDDF), ',', OP (RA), 0 } },
    3300. 

  3300. -    & ifmt_lf_itof_d, { 0xc8000014 }
    3301. 

  3301. -  },
    3302. 

  3302.  /* lf.itof.d $rDD32F,$rADI */
    3303. 

  3303.    {
    3304. 

  3304.      { 0, 0, 0, 0 },
    3305. 

  3305. @@ -936,12 +880,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3306. 

  3306.      { { MNEM, ' ', OP (RD), ',', OP (RASF), 0 } },
    3307. 

  3307.      & ifmt_lf_ftoi_s, { 0xc8000005 }
    3308. 

  3308.    },
    3309. 

  3309. -/* lf.ftoi.d $rD,$rADF */
    3310. 

  3310. -  {
    3311. 

  3311. -    { 0, 0, 0, 0 },
    3312. 

  3312. -    { { MNEM, ' ', OP (RD), ',', OP (RADF), 0 } },
    3313. 

  3313. -    & ifmt_lf_ftoi_d, { 0xc8000015 }
    3314. 

  3314. -  },
    3315. 

  3315.  /* lf.ftoi.d $rDDI,$rAD32F */
    3316. 

  3316.    {
    3317. 

  3317.      { 0, 0, 0, 0 },
    3318. 

  3318. @@ -954,12 +892,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3319. 

  3319.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3320. 

  3320.      & ifmt_lf_sfeq_s, { 0xc8000008 }
    3321. 

  3321.    },
    3322. 

  3322. -/* lf.sfeq.d $rADF,$rBDF */
    3323. 

  3323. -  {
    3324. 

  3324. -    { 0, 0, 0, 0 },
    3325. 

  3325. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3326. 

  3326. -    & ifmt_lf_sfeq_d, { 0xc8000018 }
    3327. 

  3327. -  },
    3328. 

  3328.  /* lf.sfeq.d $rAD32F,$rBD32F */
    3329. 

  3329.    {
    3330. 

  3330.      { 0, 0, 0, 0 },
    3331. 

  3331. @@ -972,12 +904,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3332. 

  3332.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3333. 

  3333.      & ifmt_lf_sfeq_s, { 0xc8000009 }
    3334. 

  3334.    },
    3335. 

  3335. -/* lf.sfne.d $rADF,$rBDF */
    3336. 

  3336. -  {
    3337. 

  3337. -    { 0, 0, 0, 0 },
    3338. 

  3338. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3339. 

  3339. -    & ifmt_lf_sfeq_d, { 0xc8000019 }
    3340. 

  3340. -  },
    3341. 

  3341.  /* lf.sfne.d $rAD32F,$rBD32F */
    3342. 

  3342.    {
    3343. 

  3343.      { 0, 0, 0, 0 },
    3344. 

  3344. @@ -990,12 +916,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3345. 

  3345.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3346. 

  3346.      & ifmt_lf_sfeq_s, { 0xc800000b }
    3347. 

  3347.    },
    3348. 

  3348. -/* lf.sfge.d $rADF,$rBDF */
    3349. 

  3349. -  {
    3350. 

  3350. -    { 0, 0, 0, 0 },
    3351. 

  3351. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3352. 

  3352. -    & ifmt_lf_sfeq_d, { 0xc800001b }
    3353. 

  3353. -  },
    3354. 

  3354.  /* lf.sfge.d $rAD32F,$rBD32F */
    3355. 

  3355.    {
    3356. 

  3356.      { 0, 0, 0, 0 },
    3357. 

  3357. @@ -1008,12 +928,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3358. 

  3358.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3359. 

  3359.      & ifmt_lf_sfeq_s, { 0xc800000a }
    3360. 

  3360.    },
    3361. 

  3361. -/* lf.sfgt.d $rADF,$rBDF */
    3362. 

  3362. -  {
    3363. 

  3363. -    { 0, 0, 0, 0 },
    3364. 

  3364. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3365. 

  3365. -    & ifmt_lf_sfeq_d, { 0xc800001a }
    3366. 

  3366. -  },
    3367. 

  3367.  /* lf.sfgt.d $rAD32F,$rBD32F */
    3368. 

  3368.    {
    3369. 

  3369.      { 0, 0, 0, 0 },
    3370. 

  3370. @@ -1026,12 +940,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3371. 

  3371.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3372. 

  3372.      & ifmt_lf_sfeq_s, { 0xc800000c }
    3373. 

  3373.    },
    3374. 

  3374. -/* lf.sflt.d $rADF,$rBDF */
    3375. 

  3375. -  {
    3376. 

  3376. -    { 0, 0, 0, 0 },
    3377. 

  3377. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3378. 

  3378. -    & ifmt_lf_sfeq_d, { 0xc800001c }
    3379. 

  3379. -  },
    3380. 

  3380.  /* lf.sflt.d $rAD32F,$rBD32F */
    3381. 

  3381.    {
    3382. 

  3382.      { 0, 0, 0, 0 },
    3383. 

  3383. @@ -1044,12 +952,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3384. 

  3384.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3385. 

  3385.      & ifmt_lf_sfeq_s, { 0xc800000d }
    3386. 

  3386.    },
    3387. 

  3387. -/* lf.sfle.d $rADF,$rBDF */
    3388. 

  3388. -  {
    3389. 

  3389. -    { 0, 0, 0, 0 },
    3390. 

  3390. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3391. 

  3391. -    & ifmt_lf_sfeq_d, { 0xc800001d }
    3392. 

  3392. -  },
    3393. 

  3393.  /* lf.sfle.d $rAD32F,$rBD32F */
    3394. 

  3394.    {
    3395. 

  3395.      { 0, 0, 0, 0 },
    3396. 

  3396. @@ -1062,12 +964,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3397. 

  3397.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3398. 

  3398.      & ifmt_lf_sfeq_s, { 0xc8000028 }
    3399. 

  3399.    },
    3400. 

  3400. -/* lf.sfueq.d $rADF,$rBDF */
    3401. 

  3401. -  {
    3402. 

  3402. -    { 0, 0, 0, 0 },
    3403. 

  3403. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3404. 

  3404. -    & ifmt_lf_sfeq_d, { 0xc8000038 }
    3405. 

  3405. -  },
    3406. 

  3406.  /* lf.sfueq.d $rAD32F,$rBD32F */
    3407. 

  3407.    {
    3408. 

  3408.      { 0, 0, 0, 0 },
    3409. 

  3409. @@ -1080,12 +976,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3410. 

  3410.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3411. 

  3411.      & ifmt_lf_sfeq_s, { 0xc8000029 }
    3412. 

  3412.    },
    3413. 

  3413. -/* lf.sfune.d $rADF,$rBDF */
    3414. 

  3414. -  {
    3415. 

  3415. -    { 0, 0, 0, 0 },
    3416. 

  3416. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3417. 

  3417. -    & ifmt_lf_sfeq_d, { 0xc8000039 }
    3418. 

  3418. -  },
    3419. 

  3419.  /* lf.sfune.d $rAD32F,$rBD32F */
    3420. 

  3420.    {
    3421. 

  3421.      { 0, 0, 0, 0 },
    3422. 

  3422. @@ -1098,12 +988,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3423. 

  3423.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3424. 

  3424.      & ifmt_lf_sfeq_s, { 0xc800002a }
    3425. 

  3425.    },
    3426. 

  3426. -/* lf.sfugt.d $rADF,$rBDF */
    3427. 

  3427. -  {
    3428. 

  3428. -    { 0, 0, 0, 0 },
    3429. 

  3429. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3430. 

  3430. -    & ifmt_lf_sfeq_d, { 0xc800003a }
    3431. 

  3431. -  },
    3432. 

  3432.  /* lf.sfugt.d $rAD32F,$rBD32F */
    3433. 

  3433.    {
    3434. 

  3434.      { 0, 0, 0, 0 },
    3435. 

  3435. @@ -1116,12 +1000,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3436. 

  3436.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3437. 

  3437.      & ifmt_lf_sfeq_s, { 0xc800002b }
    3438. 

  3438.    },
    3439. 

  3439. -/* lf.sfuge.d $rADF,$rBDF */
    3440. 

  3440. -  {
    3441. 

  3441. -    { 0, 0, 0, 0 },
    3442. 

  3442. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3443. 

  3443. -    & ifmt_lf_sfeq_d, { 0xc800003b }
    3444. 

  3444. -  },
    3445. 

  3445.  /* lf.sfuge.d $rAD32F,$rBD32F */
    3446. 

  3446.    {
    3447. 

  3447.      { 0, 0, 0, 0 },
    3448. 

  3448. @@ -1134,12 +1012,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3449. 

  3449.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3450. 

  3450.      & ifmt_lf_sfeq_s, { 0xc800002c }
    3451. 

  3451.    },
    3452. 

  3452. -/* lf.sfult.d $rADF,$rBDF */
    3453. 

  3453. -  {
    3454. 

  3454. -    { 0, 0, 0, 0 },
    3455. 

  3455. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3456. 

  3456. -    & ifmt_lf_sfeq_d, { 0xc800003c }
    3457. 

  3457. -  },
    3458. 

  3458.  /* lf.sfult.d $rAD32F,$rBD32F */
    3459. 

  3459.    {
    3460. 

  3460.      { 0, 0, 0, 0 },
    3461. 

  3461. @@ -1152,12 +1024,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3462. 

  3462.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3463. 

  3463.      & ifmt_lf_sfeq_s, { 0xc800002d }
    3464. 

  3464.    },
    3465. 

  3465. -/* lf.sfule.d $rADF,$rBDF */
    3466. 

  3466. -  {
    3467. 

  3467. -    { 0, 0, 0, 0 },
    3468. 

  3468. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3469. 

  3469. -    & ifmt_lf_sfeq_d, { 0xc800003d }
    3470. 

  3470. -  },
    3471. 

  3471.  /* lf.sfule.d $rAD32F,$rBD32F */
    3472. 

  3472.    {
    3473. 

  3473.      { 0, 0, 0, 0 },
    3474. 

  3474. @@ -1170,12 +1036,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3475. 

  3475.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3476. 

  3476.      & ifmt_lf_sfeq_s, { 0xc800002e }
    3477. 

  3477.    },
    3478. 

  3478. -/* lf.sfun.d $rADF,$rBDF */
    3479. 

  3479. -  {
    3480. 

  3480. -    { 0, 0, 0, 0 },
    3481. 

  3481. -    { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
    3482. 

  3482. -    & ifmt_lf_sfeq_d, { 0xc800003e }
    3483. 

  3483. -  },
    3484. 

  3484.  /* lf.sfun.d $rAD32F,$rBD32F */
    3485. 

  3485.    {
    3486. 

  3486.      { 0, 0, 0, 0 },
    3487. 

  3487. @@ -1188,12 +1048,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3488. 

  3488.      { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } },
    3489. 

  3489.      & ifmt_lf_add_s, { 0xc8000007 }
    3490. 

  3490.    },
    3491. 

  3491. -/* lf.madd.d $rDDF,$rADF,$rBDF */
    3492. 

  3492. -  {
    3493. 

  3493. -    { 0, 0, 0, 0 },
    3494. 

  3494. -    { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
    3495. 

  3495. -    & ifmt_lf_add_d, { 0xc8000017 }
    3496. 

  3496. -  },
    3497. 

  3497.  /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
    3498. 

  3498.    {
    3499. 

  3499.      { 0, 0, 0, 0 },
    3500. 

  3500. @@ -1206,12 +1060,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
    3501. 

  3501.      { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
    3502. 

  3502.      & ifmt_lf_cust1_s, { 0xc80000d0 }
    3503. 

  3503.    },
    3504. 

  3504. -/* lf.cust1.d */
    3505. 

  3505. -  {
    3506. 

  3506. -    { 0, 0, 0, 0 },
    3507. 

  3507. -    { { MNEM, 0 } },
    3508. 

  3508. -    & ifmt_lf_cust1_d, { 0xc80000e0 }
    3509. 

  3509. -  },
    3510. 

  3510.  /* lf.cust1.d */
    3511. 

  3511.    {
    3512. 

  3512.      { 0, 0, 0, 0 },
    3513. 

  3513. diff --git a/opcodes/or1k-opc.h b/opcodes/or1k-opc.h
    3514. 

  3514. index 2ec4b4b323..0c392274a2 100644
    3515. 

  3515. --- a/opcodes/or1k-opc.h
    3516. 

  3516. +++ b/opcodes/or1k-opc.h
    3517. 

  3517. @@ -70,23 +70,17 @@ typedef enum cgen_insn_type {
    3518. 

  3518.   , OR1K_INSN_L_MACU, OR1K_INSN_L_MSB, OR1K_INSN_L_MSBU, OR1K_INSN_L_CUST1
    3519. 

  3519.   , OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5
    3520. 

  3520.   , OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S
    3521. 

  3521. - , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D
    3522. 

  3522. - , OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_MUL_D32
    3523. 

  3523. - , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S
    3524. 

  3524. - , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D
    3525. 

  3525. - , OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_FTOI_D32
    3526. 

  3526. - , OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S
    3527. 

  3527. - , OR1K_INSN_LF_SFNE_D, OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D
    3528. 

  3528. - , OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S, OR1K_INSN_LF_SFGT_D, OR1K_INSN_LF_SFGT_D32
    3529. 

  3529. - , OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S
    3530. 

  3530. - , OR1K_INSN_LF_SFLE_D, OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D
    3531. 

  3531. - , OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S, OR1K_INSN_LF_SFUNE_D, OR1K_INSN_LF_SFUNE_D32
    3532. 

  3532. - , OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S
    3533. 

  3533. - , OR1K_INSN_LF_SFUGE_D, OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D
    3534. 

  3534. - , OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S, OR1K_INSN_LF_SFULE_D, OR1K_INSN_LF_SFULE_D32
    3535. 

  3535. - , OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S
    3536. 

  3536. - , OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D
    3537. 

  3537. - , OR1K_INSN_LF_CUST1_D32
    3538. 

  3538. + , OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S
    3539. 

  3539. + , OR1K_INSN_LF_MUL_D32, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S
    3540. 

  3540. + , OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S
    3541. 

  3541. + , OR1K_INSN_LF_FTOI_D32, OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S
    3542. 

  3542. + , OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S
    3543. 

  3543. + , OR1K_INSN_LF_SFGT_D32, OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S
    3544. 

  3544. + , OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S
    3545. 

  3545. + , OR1K_INSN_LF_SFUNE_D32, OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S
    3546. 

  3546. + , OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S
    3547. 

  3547. + , OR1K_INSN_LF_SFULE_D32, OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S
    3548. 

  3548. + , OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D32
    3549. 

  3549.  } CGEN_INSN_TYPE;
    3550. 

  3550.  
    3551. 

  3551.  /* Index of `invalid' insn place holder.  */
    3552. 

  3552. diff --git a/opcodes/or1k-opinst.c b/opcodes/or1k-opinst.c
    3553. 

  3553. index 84a0dfe9bc..7be3e5210d 100644
    3554. 

  3554. --- a/opcodes/or1k-opinst.c
    3555. 

  3555. +++ b/opcodes/or1k-opinst.c
    3556. 

  3556. @@ -43,54 +43,54 @@ static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = {
    3557. 

  3557.  };
    3558. 

  3558.  
    3559. 

  3559.  static const CGEN_OPINST sfmt_l_j_ops[] ATTRIBUTE_UNUSED = {
    3560. 

  3560. -  { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 },
    3561. 

  3561. -  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
    3562. 

  3562. -  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
    3563. 

  3563. +  { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, 0 },
    3564. 

  3564. +  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 },
    3565. 

  3565. +  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
    3566. 

  3566.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3567. 

  3567.  };
    3568. 

  3568.  
    3569. 

  3569.  static const CGEN_OPINST sfmt_l_adrp_ops[] ATTRIBUTE_UNUSED = {
    3570. 

  3570. -  { INPUT, "disp21", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP21), 0, 0 },
    3571. 

  3571. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3572. 

  3572. +  { INPUT, "disp21", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP21), 0, 0 },
    3573. 

  3573. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3574. 

  3574.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3575. 

  3575.  };
    3576. 

  3576.  
    3577. 

  3577.  static const CGEN_OPINST sfmt_l_jal_ops[] ATTRIBUTE_UNUSED = {
    3578. 

  3578. -  { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 },
    3579. 

  3579. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
    3580. 

  3580. -  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
    3581. 

  3581. -  { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 },
    3582. 

  3582. -  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
    3583. 

  3583. +  { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, 0 },
    3584. 

  3584. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
    3585. 

  3585. +  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 },
    3586. 

  3586. +  { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 },
    3587. 

  3587. +  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
    3588. 

  3588.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3589. 

  3589.  };
    3590. 

  3590.  
    3591. 

  3591.  static const CGEN_OPINST sfmt_l_jr_ops[] ATTRIBUTE_UNUSED = {
    3592. 

  3592. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3593. 

  3593. -  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
    3594. 

  3594. -  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
    3595. 

  3595. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3596. 

  3596. +  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 },
    3597. 

  3597. +  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
    3598. 

  3598.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3599. 

  3599.  };
    3600. 

  3600.  
    3601. 

  3601.  static const CGEN_OPINST sfmt_l_jalr_ops[] ATTRIBUTE_UNUSED = {
    3602. 

  3602. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
    3603. 

  3603. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3604. 

  3604. -  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
    3605. 

  3605. -  { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 },
    3606. 

  3606. -  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
    3607. 

  3607. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
    3608. 

  3608. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3609. 

  3609. +  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 },
    3610. 

  3610. +  { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 },
    3611. 

  3611. +  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
    3612. 

  3612.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3613. 

  3613.  };
    3614. 

  3614.  
    3615. 

  3615.  static const CGEN_OPINST sfmt_l_bnf_ops[] ATTRIBUTE_UNUSED = {
    3616. 

  3616. -  { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, COND_REF },
    3617. 

  3617. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3618. 

  3618. -  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, COND_REF },
    3619. 

  3619. -  { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    3620. 

  3620. -  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3621. 

  3621. +  { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, COND_REF },
    3622. 

  3622. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3623. 

  3623. +  { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, COND_REF },
    3624. 

  3624. +  { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    3625. 

  3625. +  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3626. 

  3626.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3627. 

  3627.  };
    3628. 

  3628.  
    3629. 

  3629.  static const CGEN_OPINST sfmt_l_trap_ops[] ATTRIBUTE_UNUSED = {
    3630. 

  3630. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
    3631. 

  3631. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
    3632. 

  3632.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3633. 

  3633.  };
    3634. 

  3634.  
    3635. 

  3635. @@ -105,94 +105,94 @@ static const CGEN_OPINST sfmt_l_nop_imm_ops[] ATTRIBUTE_UNUSED = {
    3636. 

  3636.  
    3637. 

  3637.  static const CGEN_OPINST sfmt_l_movhi_ops[] ATTRIBUTE_UNUSED = {
    3638. 

  3638.    { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
    3639. 

  3639. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3640. 

  3640. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3641. 

  3641.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3642. 

  3642.  };
    3643. 

  3643.  
    3644. 

  3644.  static const CGEN_OPINST sfmt_l_macrc_ops[] ATTRIBUTE_UNUSED = {
    3645. 

  3645. -  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    3646. 

  3646. -  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    3647. 

  3647. -  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    3648. 

  3648. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3649. 

  3649. +  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    3650. 

  3650. +  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    3651. 

  3651. +  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    3652. 

  3652. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3653. 

  3653.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3654. 

  3654.  };
    3655. 

  3655.  
    3656. 

  3656.  static const CGEN_OPINST sfmt_l_mfspr_ops[] ATTRIBUTE_UNUSED = {
    3657. 

  3657. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3658. 

  3658. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3659. 

  3659.    { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
    3660. 

  3660. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3661. 

  3661. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3662. 

  3662.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3663. 

  3663.  };
    3664. 

  3664.  
    3665. 

  3665.  static const CGEN_OPINST sfmt_l_mtspr_ops[] ATTRIBUTE_UNUSED = {
    3666. 

  3666. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3667. 

  3667. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3668. 

  3668. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3669. 

  3669. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3670. 

  3670.    { INPUT, "uimm16_split", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16_SPLIT), 0, 0 },
    3671. 

  3671.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3672. 

  3672.  };
    3673. 

  3673.  
    3674. 

  3674.  static const CGEN_OPINST sfmt_l_lwz_ops[] ATTRIBUTE_UNUSED = {
    3675. 

  3675.    { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
    3676. 

  3676. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3677. 

  3677. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3678. 

  3678.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3679. 

  3679. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3680. 

  3680. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3681. 

  3681.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3682. 

  3682.  };
    3683. 

  3683.  
    3684. 

  3684.  static const CGEN_OPINST sfmt_l_lws_ops[] ATTRIBUTE_UNUSED = {
    3685. 

  3685.    { INPUT, "h_memory_SI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
    3686. 

  3686. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3687. 

  3687. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3688. 

  3688.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3689. 

  3689. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3690. 

  3690. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3691. 

  3691.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3692. 

  3692.  };
    3693. 

  3693.  
    3694. 

  3694.  static const CGEN_OPINST sfmt_l_lwa_ops[] ATTRIBUTE_UNUSED = {
    3695. 

  3695.    { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
    3696. 

  3696. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3697. 

  3697. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3698. 

  3698.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3699. 

  3699.    { OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
    3700. 

  3700.    { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
    3701. 

  3701. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3702. 

  3702. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3703. 

  3703.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3704. 

  3704.  };
    3705. 

  3705.  
    3706. 

  3706.  static const CGEN_OPINST sfmt_l_lbz_ops[] ATTRIBUTE_UNUSED = {
    3707. 

  3707.    { INPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
    3708. 

  3708. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3709. 

  3709. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3710. 

  3710.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3711. 

  3711. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3712. 

  3712. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3713. 

  3713.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3714. 

  3714.  };
    3715. 

  3715.  
    3716. 

  3716.  static const CGEN_OPINST sfmt_l_lbs_ops[] ATTRIBUTE_UNUSED = {
    3717. 

  3717.    { INPUT, "h_memory_QI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
    3718. 

  3718. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3719. 

  3719. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3720. 

  3720.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3721. 

  3721. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3722. 

  3722. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3723. 

  3723.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3724. 

  3724.  };
    3725. 

  3725.  
    3726. 

  3726.  static const CGEN_OPINST sfmt_l_lhz_ops[] ATTRIBUTE_UNUSED = {
    3727. 

  3727.    { INPUT, "h_memory_UHI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
    3728. 

  3728. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3729. 

  3729. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3730. 

  3730.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3731. 

  3731. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3732. 

  3732. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3733. 

  3733.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3734. 

  3734.  };
    3735. 

  3735.  
    3736. 

  3736.  static const CGEN_OPINST sfmt_l_lhs_ops[] ATTRIBUTE_UNUSED = {
    3737. 

  3737.    { INPUT, "h_memory_HI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
    3738. 

  3738. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3739. 

  3739. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3740. 

  3740.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3741. 

  3741. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3742. 

  3742. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3743. 

  3743.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3744. 

  3744.  };
    3745. 

  3745.  
    3746. 

  3746.  static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = {
    3747. 

  3747.    { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
    3748. 

  3748. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3749. 

  3749. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3750. 

  3750. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3751. 

  3751. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3752. 

  3752.    { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
    3753. 

  3753.    { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
    3754. 

  3754.    { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
    3755. 

  3755. @@ -201,8 +201,8 @@ static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = {
    3756. 

  3756.  
    3757. 

  3757.  static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = {
    3758. 

  3758.    { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
    3759. 

  3759. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3760. 

  3760. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3761. 

  3761. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3762. 

  3762. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3763. 

  3763.    { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
    3764. 

  3764.    { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
    3765. 

  3765.    { OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
    3766. 

  3766. @@ -211,8 +211,8 @@ static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = {
    3767. 

  3767.  
    3768. 

  3768.  static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = {
    3769. 

  3769.    { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
    3770. 

  3770. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3771. 

  3771. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3772. 

  3772. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3773. 

  3773. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3774. 

  3774.    { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
    3775. 

  3775.    { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
    3776. 

  3776.    { OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
    3777. 

  3777. @@ -222,228 +222,228 @@ static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = {
    3778. 

  3778.  static const CGEN_OPINST sfmt_l_swa_ops[] ATTRIBUTE_UNUSED = {
    3779. 

  3779.    { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
    3780. 

  3780.    { INPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
    3781. 

  3781. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3782. 

  3782. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF },
    3783. 

  3783. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3784. 

  3784. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, COND_REF },
    3785. 

  3785.    { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
    3786. 

  3786. -  { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    3787. 

  3787. +  { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    3788. 

  3788.    { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
    3789. 

  3789.    { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF },
    3790. 

  3790. -  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    3791. 

  3791. +  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    3792. 

  3792.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3793. 

  3793.  };
    3794. 

  3794.  
    3795. 

  3795.  static const CGEN_OPINST sfmt_l_sll_ops[] ATTRIBUTE_UNUSED = {
    3796. 

  3796. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3797. 

  3797. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3798. 

  3798. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3799. 

  3799. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3800. 

  3800. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3801. 

  3801. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3802. 

  3802.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3803. 

  3803.  };
    3804. 

  3804.  
    3805. 

  3805.  static const CGEN_OPINST sfmt_l_slli_ops[] ATTRIBUTE_UNUSED = {
    3806. 

  3806. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3807. 

  3807. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3808. 

  3808.    { INPUT, "uimm6", HW_H_UIMM6, CGEN_MODE_UINT, OP_ENT (UIMM6), 0, 0 },
    3809. 

  3809. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3810. 

  3810. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3811. 

  3811.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3812. 

  3812.  };
    3813. 

  3813.  
    3814. 

  3814.  static const CGEN_OPINST sfmt_l_and_ops[] ATTRIBUTE_UNUSED = {
    3815. 

  3815. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3816. 

  3816. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3817. 

  3817. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3818. 

  3818. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3819. 

  3819. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3820. 

  3820. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3821. 

  3821.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3822. 

  3822.  };
    3823. 

  3823.  
    3824. 

  3824.  static const CGEN_OPINST sfmt_l_add_ops[] ATTRIBUTE_UNUSED = {
    3825. 

  3825. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3826. 

  3826. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3827. 

  3827. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3828. 

  3828. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3829. 

  3829. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    3830. 

  3830. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3831. 

  3831. -  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3832. 

  3832. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3833. 

  3833. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3834. 

  3834. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3835. 

  3835. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3836. 

  3836. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3837. 

  3837. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    3838. 

  3838. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3839. 

  3839. +  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3840. 

  3840. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3841. 

  3841.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3842. 

  3842.  };
    3843. 

  3843.  
    3844. 

  3844.  static const CGEN_OPINST sfmt_l_addc_ops[] ATTRIBUTE_UNUSED = {
    3845. 

  3845. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3846. 

  3846. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3847. 

  3847. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3848. 

  3848. -  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3849. 

  3849. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3850. 

  3850. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    3851. 

  3851. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3852. 

  3852. -  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3853. 

  3853. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3854. 

  3854. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3855. 

  3855. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3856. 

  3856. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3857. 

  3857. +  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3858. 

  3858. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3859. 

  3859. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    3860. 

  3860. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3861. 

  3861. +  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3862. 

  3862. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3863. 

  3863.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3864. 

  3864.  };
    3865. 

  3865.  
    3866. 

  3866.  static const CGEN_OPINST sfmt_l_mul_ops[] ATTRIBUTE_UNUSED = {
    3867. 

  3867. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3868. 

  3868. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3869. 

  3869. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3870. 

  3870. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3871. 

  3871. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    3872. 

  3872. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3873. 

  3873. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3874. 

  3874. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3875. 

  3875. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3876. 

  3876. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3877. 

  3877. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3878. 

  3878. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    3879. 

  3879. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3880. 

  3880. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3881. 

  3881.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3882. 

  3882.  };
    3883. 

  3883.  
    3884. 

  3884.  static const CGEN_OPINST sfmt_l_muld_ops[] ATTRIBUTE_UNUSED = {
    3885. 

  3885. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3886. 

  3886. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3887. 

  3887. -  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    3888. 

  3888. -  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    3889. 

  3889. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3890. 

  3890. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3891. 

  3891. +  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    3892. 

  3892. +  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    3893. 

  3893.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3894. 

  3894.  };
    3895. 

  3895.  
    3896. 

  3896.  static const CGEN_OPINST sfmt_l_mulu_ops[] ATTRIBUTE_UNUSED = {
    3897. 

  3897. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3898. 

  3898. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3899. 

  3899. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3900. 

  3900. -  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3901. 

  3901. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    3902. 

  3902. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3903. 

  3903. -  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3904. 

  3904. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3905. 

  3905. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3906. 

  3906. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3907. 

  3907. +  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3908. 

  3908. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    3909. 

  3909. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3910. 

  3910. +  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3911. 

  3911.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3912. 

  3912.  };
    3913. 

  3913.  
    3914. 

  3914.  static const CGEN_OPINST sfmt_l_div_ops[] ATTRIBUTE_UNUSED = {
    3915. 

  3915. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3916. 

  3916. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF },
    3917. 

  3917. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3918. 

  3918. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF },
    3919. 

  3919. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF },
    3920. 

  3920. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, COND_REF },
    3921. 

  3921. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3922. 

  3922. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF },
    3923. 

  3923. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3924. 

  3924. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, COND_REF },
    3925. 

  3925. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF },
    3926. 

  3926. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, COND_REF },
    3927. 

  3927.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3928. 

  3928.  };
    3929. 

  3929.  
    3930. 

  3930.  static const CGEN_OPINST sfmt_l_divu_ops[] ATTRIBUTE_UNUSED = {
    3931. 

  3931. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3932. 

  3932. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF },
    3933. 

  3933. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    3934. 

  3934. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF },
    3935. 

  3935. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF },
    3936. 

  3936. -  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, COND_REF },
    3937. 

  3937. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3938. 

  3938. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF },
    3939. 

  3939. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    3940. 

  3940. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, COND_REF },
    3941. 

  3941. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF },
    3942. 

  3942. +  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, COND_REF },
    3943. 

  3943.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3944. 

  3944.  };
    3945. 

  3945.  
    3946. 

  3946.  static const CGEN_OPINST sfmt_l_ff1_ops[] ATTRIBUTE_UNUSED = {
    3947. 

  3947. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3948. 

  3948. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3949. 

  3949. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3950. 

  3950. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3951. 

  3951.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3952. 

  3952.  };
    3953. 

  3953.  
    3954. 

  3954.  static const CGEN_OPINST sfmt_l_xori_ops[] ATTRIBUTE_UNUSED = {
    3955. 

  3955. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3956. 

  3956. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3957. 

  3957.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3958. 

  3958. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3959. 

  3959. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3960. 

  3960.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3961. 

  3961.  };
    3962. 

  3962.  
    3963. 

  3963.  static const CGEN_OPINST sfmt_l_addi_ops[] ATTRIBUTE_UNUSED = {
    3964. 

  3964. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3965. 

  3965. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3966. 

  3966. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3967. 

  3967. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3968. 

  3968.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3969. 

  3969. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3970. 

  3970. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    3971. 

  3971. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3972. 

  3972. -  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3973. 

  3973. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3974. 

  3974. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3975. 

  3975. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    3976. 

  3976. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3977. 

  3977. +  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3978. 

  3978. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3979. 

  3979.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    3980. 

  3980.  };
    3981. 

  3981.  
    3982. 

  3982.  static const CGEN_OPINST sfmt_l_addic_ops[] ATTRIBUTE_UNUSED = {
    3983. 

  3983. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    3984. 

  3984. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    3985. 

  3985. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    3986. 

  3986. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    3987. 

  3987.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    3988. 

  3988. -  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3989. 

  3989. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3990. 

  3990. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    3991. 

  3991. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    3992. 

  3992. -  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    3993. 

  3993. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    3994. 

  3994. +  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3995. 

  3995. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    3996. 

  3996. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    3997. 

  3997. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    3998. 

  3998. +  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    3999. 

  3999. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    4000. 

  4000.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4001. 

  4001.  };
    4002. 

  4002.  
    4003. 

  4003.  static const CGEN_OPINST sfmt_l_muli_ops[] ATTRIBUTE_UNUSED = {
    4004. 

  4004. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    4005. 

  4005. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4006. 

  4006. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    4007. 

  4007. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4008. 

  4008.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    4009. 

  4009. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    4010. 

  4010. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    4011. 

  4011. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    4012. 

  4012. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    4013. 

  4013. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    4014. 

  4014. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    4015. 

  4015. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    4016. 

  4016. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    4017. 

  4017.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4018. 

  4018.  };
    4019. 

  4019.  
    4020. 

  4020.  static const CGEN_OPINST sfmt_l_exths_ops[] ATTRIBUTE_UNUSED = {
    4021. 

  4021. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4022. 

  4022. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    4023. 

  4023. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4024. 

  4024. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    4025. 

  4025.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4026. 

  4026.  };
    4027. 

  4027.  
    4028. 

  4028.  static const CGEN_OPINST sfmt_l_cmov_ops[] ATTRIBUTE_UNUSED = {
    4029. 

  4029. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF },
    4030. 

  4030. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF },
    4031. 

  4031. -  { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    4032. 

  4032. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF },
    4033. 

  4033. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF },
    4034. 

  4034. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, COND_REF },
    4035. 

  4035. +  { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    4036. 

  4036. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF },
    4037. 

  4037.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4038. 

  4038.  };
    4039. 

  4039.  
    4040. 

  4040.  static const CGEN_OPINST sfmt_l_sfgts_ops[] ATTRIBUTE_UNUSED = {
    4041. 

  4041. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4042. 

  4042. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    4043. 

  4043. -  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    4044. 

  4044. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4045. 

  4045. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    4046. 

  4046. +  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    4047. 

  4047.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4048. 

  4048.  };
    4049. 

  4049.  
    4050. 

  4050.  static const CGEN_OPINST sfmt_l_sfgtsi_ops[] ATTRIBUTE_UNUSED = {
    4051. 

  4051. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4052. 

  4052. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4053. 

  4053.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    4054. 

  4054. -  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    4055. 

  4055. +  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    4056. 

  4056.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4057. 

  4057.  };
    4058. 

  4058.  
    4059. 

  4059.  static const CGEN_OPINST sfmt_l_mac_ops[] ATTRIBUTE_UNUSED = {
    4060. 

  4060. -  { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    4061. 

  4061. -  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    4062. 

  4062. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    4063. 

  4063. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4064. 

  4064. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    4065. 

  4065. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    4066. 

  4066. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    4067. 

  4067. -  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    4068. 

  4068. -  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    4069. 

  4069. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    4070. 

  4070. +  { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    4071. 

  4071. +  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    4072. 

  4072. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    4073. 

  4073. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4074. 

  4074. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    4075. 

  4075. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    4076. 

  4076. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    4077. 

  4077. +  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    4078. 

  4078. +  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    4079. 

  4079. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    4080. 

  4080.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4081. 

  4081.  };
    4082. 

  4082.  
    4083. 

  4083.  static const CGEN_OPINST sfmt_l_maci_ops[] ATTRIBUTE_UNUSED = {
    4084. 

  4084. -  { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    4085. 

  4085. -  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    4086. 

  4086. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    4087. 

  4087. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4088. 

  4088. +  { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    4089. 

  4089. +  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    4090. 

  4090. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    4091. 

  4091. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4092. 

  4092.    { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
    4093. 

  4093. -  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    4094. 

  4094. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    4095. 

  4095. -  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    4096. 

  4096. -  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    4097. 

  4097. -  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
    4098. 

  4098. +  { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    4099. 

  4099. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    4100. 

  4100. +  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    4101. 

  4101. +  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    4102. 

  4102. +  { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
    4103. 

  4103.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4104. 

  4104.  };
    4105. 

  4105.  
    4106. 

  4106.  static const CGEN_OPINST sfmt_l_macu_ops[] ATTRIBUTE_UNUSED = {
    4107. 

  4107. -  { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    4108. 

  4108. -  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    4109. 

  4109. -  { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
    4110. 

  4110. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4111. 

  4111. -  { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
    4112. 

  4112. -  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    4113. 

  4113. -  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
    4114. 

  4114. -  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
    4115. 

  4115. -  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
    4116. 

  4116. -  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
    4117. 

  4117. +  { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    4118. 

  4118. +  { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    4119. 

  4119. +  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
    4120. 

  4120. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4121. 

  4121. +  { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 },
    4122. 

  4122. +  { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    4123. 

  4123. +  { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 },
    4124. 

  4124. +  { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
    4125. 

  4125. +  { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
    4126. 

  4126. +  { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
    4127. 

  4127.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4128. 

  4128.  };
    4129. 

  4129.  
    4130. 

  4130. @@ -454,13 +454,6 @@ static const CGEN_OPINST sfmt_lf_add_s_ops[] ATTRIBUTE_UNUSED = {
    4131. 

  4131.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4132. 

  4132.  };
    4133. 

  4133.  
    4134. 

  4134. -static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = {
    4135. 

  4135. -  { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
    4136. 

  4136. -  { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 },
    4137. 

  4137. -  { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
    4138. 

  4138. -  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4139. 

  4139. -};
    4140. 

  4140. -
    4141. 

  4141.  static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = {
    4142. 

  4142.    { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
    4143. 

  4143.    { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
    4144. 

  4144. @@ -469,43 +462,29 @@ static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = {
    4145. 

  4145.  };
    4146. 

  4146.  
    4147. 

  4147.  static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = {
    4148. 

  4148. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4149. 

  4149. -  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
    4150. 

  4150. +  { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 },
    4151. 

  4151. +  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 },
    4152. 

  4152.    { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
    4153. 

  4153.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4154. 

  4154.  };
    4155. 

  4155.  
    4156. 

  4156. -static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = {
    4157. 

  4157. -  { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
    4158. 

  4158. -  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
    4159. 

  4159. -  { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
    4160. 

  4160. -  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4161. 

  4161. -};
    4162. 

  4162. -
    4163. 

  4163.  static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = {
    4164. 

  4164.    { INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 },
    4165. 

  4165. -  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
    4166. 

  4166. +  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 },
    4167. 

  4167.    { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
    4168. 

  4168.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4169. 

  4169.  };
    4170. 

  4170.  
    4171. 

  4171.  static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = {
    4172. 

  4172.    { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
    4173. 

  4173. -  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
    4174. 

  4174. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    4175. 

  4175. -  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4176. 

  4176. -};
    4177. 

  4177. -
    4178. 

  4178. -static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = {
    4179. 

  4179. -  { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
    4180. 

  4180. -  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
    4181. 

  4181. -  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
    4182. 

  4182. +  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 },
    4183. 

  4183. +  { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
    4184. 

  4184.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4185. 

  4185.  };
    4186. 

  4186.  
    4187. 

  4187.  static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = {
    4188. 

  4188.    { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
    4189. 

  4189. -  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
    4190. 

  4190. +  { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 },
    4191. 

  4191.    { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 },
    4192. 

  4192.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4193. 

  4193.  };
    4194. 

  4194. @@ -513,21 +492,14 @@ static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = {
    4195. 

  4195.  static const CGEN_OPINST sfmt_lf_sfeq_s_ops[] ATTRIBUTE_UNUSED = {
    4196. 

  4196.    { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
    4197. 

  4197.    { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
    4198. 

  4198. -  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    4199. 

  4199. -  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4200. 

  4200. -};
    4201. 

  4201. -
    4202. 

  4202. -static const CGEN_OPINST sfmt_lf_sfeq_d_ops[] ATTRIBUTE_UNUSED = {
    4203. 

  4203. -  { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
    4204. 

  4204. -  { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 },
    4205. 

  4205. -  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    4206. 

  4206. +  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    4207. 

  4207.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4208. 

  4208.  };
    4209. 

  4209.  
    4210. 

  4210.  static const CGEN_OPINST sfmt_lf_sfeq_d32_ops[] ATTRIBUTE_UNUSED = {
    4211. 

  4211.    { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
    4212. 

  4212.    { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
    4213. 

  4213. -  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
    4214. 

  4214. +  { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
    4215. 

  4215.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4216. 

  4216.  };
    4217. 

  4217.  
    4218. 

  4218. @@ -539,14 +511,6 @@ static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = {
    4219. 

  4219.    { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4220. 

  4220.  };
    4221. 

  4221.  
    4222. 

  4222. -static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = {
    4223. 

  4223. -  { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
    4224. 

  4224. -  { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 },
    4225. 

  4225. -  { INPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
    4226. 

  4226. -  { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
    4227. 

  4227. -  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
    4228. 

  4228. -};
    4229. 

  4229. -
    4230. 

  4230.  static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = {
    4231. 

  4231.    { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
    4232. 

  4232.    { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
    4233. 

  4233. @@ -664,71 +628,49 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = {
    4234. 

  4234.    & sfmt_l_msync_ops[0],
    4235. 

  4235.    & sfmt_l_msync_ops[0],
    4236. 

  4236.    & sfmt_lf_add_s_ops[0],
    4237. 

  4237. -  & sfmt_lf_add_d_ops[0],
    4238. 

  4238.    & sfmt_lf_add_d32_ops[0],
    4239. 

  4239.    & sfmt_lf_add_s_ops[0],
    4240. 

  4240. -  & sfmt_lf_add_d_ops[0],
    4241. 

  4241.    & sfmt_lf_add_d32_ops[0],
    4242. 

  4242.    & sfmt_lf_add_s_ops[0],
    4243. 

  4243. -  & sfmt_lf_add_d_ops[0],
    4244. 

  4244.    & sfmt_lf_add_d32_ops[0],
    4245. 

  4245.    & sfmt_lf_add_s_ops[0],
    4246. 

  4246. -  & sfmt_lf_add_d_ops[0],
    4247. 

  4247.    & sfmt_lf_add_d32_ops[0],
    4248. 

  4248.    & sfmt_lf_add_s_ops[0],
    4249. 

  4249. -  & sfmt_lf_add_d_ops[0],
    4250. 

  4250.    & sfmt_lf_add_d32_ops[0],
    4251. 

  4251.    & sfmt_lf_itof_s_ops[0],
    4252. 

  4252. -  & sfmt_lf_itof_d_ops[0],
    4253. 

  4253.    & sfmt_lf_itof_d32_ops[0],
    4254. 

  4254.    & sfmt_lf_ftoi_s_ops[0],
    4255. 

  4255. -  & sfmt_lf_ftoi_d_ops[0],
    4256. 

  4256.    & sfmt_lf_ftoi_d32_ops[0],
    4257. 

  4257.    & sfmt_lf_sfeq_s_ops[0],
    4258. 

  4258. -  & sfmt_lf_sfeq_d_ops[0],
    4259. 

  4259.    & sfmt_lf_sfeq_d32_ops[0],
    4260. 

  4260.    & sfmt_lf_sfeq_s_ops[0],
    4261. 

  4261. -  & sfmt_lf_sfeq_d_ops[0],
    4262. 

  4262.    & sfmt_lf_sfeq_d32_ops[0],
    4263. 

  4263.    & sfmt_lf_sfeq_s_ops[0],
    4264. 

  4264. -  & sfmt_lf_sfeq_d_ops[0],
    4265. 

  4265.    & sfmt_lf_sfeq_d32_ops[0],
    4266. 

  4266.    & sfmt_lf_sfeq_s_ops[0],
    4267. 

  4267. -  & sfmt_lf_sfeq_d_ops[0],
    4268. 

  4268.    & sfmt_lf_sfeq_d32_ops[0],
    4269. 

  4269.    & sfmt_lf_sfeq_s_ops[0],
    4270. 

  4270. -  & sfmt_lf_sfeq_d_ops[0],
    4271. 

  4271.    & sfmt_lf_sfeq_d32_ops[0],
    4272. 

  4272.    & sfmt_lf_sfeq_s_ops[0],
    4273. 

  4273. -  & sfmt_lf_sfeq_d_ops[0],
    4274. 

  4274.    & sfmt_lf_sfeq_d32_ops[0],
    4275. 

  4275.    & sfmt_lf_sfeq_s_ops[0],
    4276. 

  4276. -  & sfmt_lf_sfeq_d_ops[0],
    4277. 

  4277.    & sfmt_lf_sfeq_d32_ops[0],
    4278. 

  4278.    & sfmt_lf_sfeq_s_ops[0],
    4279. 

  4279. -  & sfmt_lf_sfeq_d_ops[0],
    4280. 

  4280.    & sfmt_lf_sfeq_d32_ops[0],
    4281. 

  4281.    & sfmt_lf_sfeq_s_ops[0],
    4282. 

  4282. -  & sfmt_lf_sfeq_d_ops[0],
    4283. 

  4283.    & sfmt_lf_sfeq_d32_ops[0],
    4284. 

  4284.    & sfmt_lf_sfeq_s_ops[0],
    4285. 

  4285. -  & sfmt_lf_sfeq_d_ops[0],
    4286. 

  4286.    & sfmt_lf_sfeq_d32_ops[0],
    4287. 

  4287.    & sfmt_lf_sfeq_s_ops[0],
    4288. 

  4288. -  & sfmt_lf_sfeq_d_ops[0],
    4289. 

  4289.    & sfmt_lf_sfeq_d32_ops[0],
    4290. 

  4290.    & sfmt_lf_sfeq_s_ops[0],
    4291. 

  4291. -  & sfmt_lf_sfeq_d_ops[0],
    4292. 

  4292.    & sfmt_lf_sfeq_d32_ops[0],
    4293. 

  4293.    & sfmt_lf_sfeq_s_ops[0],
    4294. 

  4294. -  & sfmt_lf_sfeq_d_ops[0],
    4295. 

  4295.    & sfmt_lf_sfeq_d32_ops[0],
    4296. 

  4296.    & sfmt_lf_madd_s_ops[0],
    4297. 

  4297. -  & sfmt_lf_madd_d_ops[0],
    4298. 

  4298.    & sfmt_lf_madd_d32_ops[0],
    4299. 

  4299.    & sfmt_l_msync_ops[0],
    4300. 

  4300.    & sfmt_l_msync_ops[0],
    4301. 

  4301. -  & sfmt_l_msync_ops[0],
    4302. 

  4302.  };
    4303. 

  4303.  
    4304. 

  4304.  /* Function to call before using the operand instance table.  */
    4305. 

  4305. -- 
    4306. 

  4306. 2.21.0
    4307. 

  4307. 

  4308.