src/disassembler.rs: Add support for 32-bit jumps in disassembler

Add support and tests for disassembling programs using 32-bit jump
instructions.

Signed-off-by: Quentin Monnet <quentin@isovalent.com>

src/disassembler.rs

@@ -306,6 +306,30 @@ pub fn to_insn_vec(prog: &[u8]) -> Vec<HLInsn> {
             ebpf::TAIL_CALL  => { name = "tail_call"; desc = name.to_string(); },
             ebpf::EXIT       => { name = "exit";      desc = name.to_string(); },
 
+            // BPF_JMP32 class
+            ebpf::JEQ_IMM32  => { name = "jeq32";  desc = jmp_imm_str(name, &insn); },
+            ebpf::JEQ_REG32  => { name = "jeq32";  desc = jmp_reg_str(name, &insn); },
+            ebpf::JGT_IMM32  => { name = "jgt32";  desc = jmp_imm_str(name, &insn); },
+            ebpf::JGT_REG32  => { name = "jgt32";  desc = jmp_reg_str(name, &insn); },
+            ebpf::JGE_IMM32  => { name = "jge32";  desc = jmp_imm_str(name, &insn); },
+            ebpf::JGE_REG32  => { name = "jge32";  desc = jmp_reg_str(name, &insn); },
+            ebpf::JLT_IMM32  => { name = "jlt32";  desc = jmp_imm_str(name, &insn); },
+            ebpf::JLT_REG32  => { name = "jlt32";  desc = jmp_reg_str(name, &insn); },
+            ebpf::JLE_IMM32  => { name = "jle32";  desc = jmp_imm_str(name, &insn); },
+            ebpf::JLE_REG32  => { name = "jle32";  desc = jmp_reg_str(name, &insn); },
+            ebpf::JSET_IMM32 => { name = "jset32"; desc = jmp_imm_str(name, &insn); },
+            ebpf::JSET_REG32 => { name = "jset32"; desc = jmp_reg_str(name, &insn); },
+            ebpf::JNE_IMM32  => { name = "jne32";  desc = jmp_imm_str(name, &insn); },
+            ebpf::JNE_REG32  => { name = "jne32";  desc = jmp_reg_str(name, &insn); },
+            ebpf::JSGT_IMM32 => { name = "jsgt32"; desc = jmp_imm_str(name, &insn); },
+            ebpf::JSGT_REG32 => { name = "jsgt32"; desc = jmp_reg_str(name, &insn); },
+            ebpf::JSGE_IMM32 => { name = "jsge32"; desc = jmp_imm_str(name, &insn); },
+            ebpf::JSGE_REG32 => { name = "jsge32"; desc = jmp_reg_str(name, &insn); },
+            ebpf::JSLT_IMM32 => { name = "jslt32"; desc = jmp_imm_str(name, &insn); },
+            ebpf::JSLT_REG32 => { name = "jslt32"; desc = jmp_reg_str(name, &insn); },
+            ebpf::JSLE_IMM32 => { name = "jsle32"; desc = jmp_imm_str(name, &insn); },
+            ebpf::JSLE_REG32 => { name = "jsle32"; desc = jmp_reg_str(name, &insn); },
+
             _                => {
                 panic!("[Disassembler] Error: unknown eBPF opcode {:#2x} (insn #{:?})",
                        insn.opc, insn_ptr);

tests/disassembler.rs

@@ -261,6 +261,30 @@ jsgt r1, 0x2, +0x3
 jsge r1, 0x2, -0x3
 jslt r1, 0x2, +0x3
 jsle r1, 0x2, -0x3");
+
+    disasm!("jeq32 r1, r2, +0x3
+jgt32 r1, r2, +0x3
+jge32 r1, r2, +0x3
+jlt32 r1, r2, +0x3
+jle32 r1, r2, +0x3
+jset32 r1, r2, +0x3
+jne32 r1, r2, +0x3
+jsgt32 r1, r2, +0x3
+jsge32 r1, r2, -0x3
+jslt32 r1, r2, +0x3
+jsle32 r1, r2, -0x3");
+
+    disasm!("jeq32 r1, 0x2, +0x3
+jgt32 r1, 0x2, +0x3
+jge32 r1, 0x2, +0x3
+jlt32 r1, 0x2, +0x3
+jle32 r1, 0x2, +0x3
+jset32 r1, 0x2, +0x3
+jne32 r1, 0x2, +0x3
+jsgt32 r1, 0x2, +0x3
+jsge32 r1, 0x2, -0x3
+jslt32 r1, 0x2, +0x3
+jsle32 r1, 0x2, -0x3");
 }
 
 // Test all supported Endian mnemonics.