src/: reorganize comments around `LD_DW_IMM` in match arms

`LD_DW_IMM` operation is not part of `BPF_LDX` class; move comments
accordingly between match arms.

src/disassembler.rs

@@ -174,13 +174,14 @@ pub fn to_insn_vec(prog: &[u8]) -> Vec<HLInsn> {
             ebpf::LD_IND_W   => { name = "ldindw";  desc = ldind_str(name, &insn); },
             ebpf::LD_IND_DW  => { name = "ldinddw"; desc = ldind_str(name, &insn); },
 
-            // BPF_LDX class
             ebpf::LD_DW_IMM  => {
                 insn_ptr += 1;
                 let next_insn = ebpf::get_insn(prog, insn_ptr);
                 imm = ((insn.imm as u32) as u64 + ((next_insn.imm as u64) << 32)) as i64;
                 name = "lddw"; desc = format!("{} r{:}, {:#x}", name, insn.dst, imm);
             },
+
+            // BPF_LDX class
             ebpf::LD_B_REG   => { name = "ldxb";  desc = ld_st_reg_str(name, &insn); },
             ebpf::LD_H_REG   => { name = "ldxh";  desc = ld_st_reg_str(name, &insn); },
             ebpf::LD_W_REG   => { name = "ldxw";  desc = ld_st_reg_str(name, &insn); },

src/jit.rs

@@ -547,13 +547,14 @@ impl<'a> JitMemory<'a> {
                     emit_load(self, OperandSize::S64, R11, RAX, insn.imm); // ld R0, mem[src+imm]
                 },
 
-                // BPF_LDX class
                 ebpf::LD_DW_IMM  => {
                     insn_ptr += 1;
                     let second_part = ebpf::get_insn(prog, insn_ptr).imm as u64;
                     let imm = (insn.imm as u32) as u64 | second_part.wrapping_shl(32);
                     emit_load_imm(self, dst, imm as i64);
                 },
+
+                // BPF_LDX class
                 ebpf::LD_B_REG   =>
                     emit_load(self, OperandSize::S8,  src, dst, insn.off as i32),
                 ebpf::LD_H_REG   =>

src/lib.rs

@@ -297,12 +297,13 @@ impl<'a> EbpfVmMbuff<'a> {
                     *x as u64
                 },
 
-                // BPF_LDX class
                 ebpf::LD_DW_IMM  => {
                     let next_insn = ebpf::get_insn(self.prog, insn_ptr);
                     insn_ptr += 1;
                     reg[_dst] = ((insn.imm as u32) as u64) + ((next_insn.imm as u64) << 32);
                 },
+
+                // BPF_LDX class
                 ebpf::LD_B_REG   => reg[_dst] = unsafe {
                     let x = (reg[_src] as *const u8).offset(insn.off as isize) as *const u8;
                     check_mem_load(x as u64, 1, insn_ptr);

src/verifier.rs

@@ -120,12 +120,13 @@ pub fn check(prog: &[u8]) -> bool {
             ebpf::LD_IND_W   => {},
             ebpf::LD_IND_DW  => {},
 
-            // BPF_LDX class
             ebpf::LD_DW_IMM  => {
                 store = true;
                 check_load_dw(prog, insn_ptr);
                 insn_ptr += 1;
             },
+
+            // BPF_LDX class
             ebpf::LD_B_REG   => {},
             ebpf::LD_H_REG   => {},
             ebpf::LD_W_REG   => {},