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@@ -449,13 +449,10 @@ impl<'a> EbpfVmMbuff<'a> {
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ebpf::SUB32_REG => reg[_dst] = (reg[_dst] as i32).wrapping_sub(reg[_src] as i32) as u64,
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ebpf::SUB32_REG => reg[_dst] = (reg[_dst] as i32).wrapping_sub(reg[_src] as i32) as u64,
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ebpf::MUL32_IMM => reg[_dst] = (reg[_dst] as i32).wrapping_mul(insn.imm) as u64,
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ebpf::MUL32_IMM => reg[_dst] = (reg[_dst] as i32).wrapping_mul(insn.imm) as u64,
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ebpf::MUL32_REG => reg[_dst] = (reg[_dst] as i32).wrapping_mul(reg[_src] as i32) as u64,
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ebpf::MUL32_REG => reg[_dst] = (reg[_dst] as i32).wrapping_mul(reg[_src] as i32) as u64,
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+ ebpf::DIV32_IMM if insn.imm == 0 => reg[_dst] = 0,
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ebpf::DIV32_IMM => reg[_dst] = (reg[_dst] as u32 / insn.imm as u32) as u64,
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ebpf::DIV32_IMM => reg[_dst] = (reg[_dst] as u32 / insn.imm as u32) as u64,
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- ebpf::DIV32_REG => {
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- if reg[_src] == 0 {
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- Err(Error::new(ErrorKind::Other,"Error: division by 0"))?;
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- }
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- reg[_dst] = (reg[_dst] as u32 / reg[_src] as u32) as u64;
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- },
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+ ebpf::DIV32_REG if reg[_src] == 0 => reg[_dst] = 0,
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+ ebpf::DIV32_REG => reg[_dst] = (reg[_dst] as u32 / reg[_src] as u32) as u64,
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ebpf::OR32_IMM => reg[_dst] = (reg[_dst] as u32 | insn.imm as u32) as u64,
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ebpf::OR32_IMM => reg[_dst] = (reg[_dst] as u32 | insn.imm as u32) as u64,
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ebpf::OR32_REG => reg[_dst] = (reg[_dst] as u32 | reg[_src] as u32) as u64,
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ebpf::OR32_REG => reg[_dst] = (reg[_dst] as u32 | reg[_src] as u32) as u64,
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ebpf::AND32_IMM => reg[_dst] = (reg[_dst] as u32 & insn.imm as u32) as u64,
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ebpf::AND32_IMM => reg[_dst] = (reg[_dst] as u32 & insn.imm as u32) as u64,
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@@ -465,13 +462,10 @@ impl<'a> EbpfVmMbuff<'a> {
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ebpf::RSH32_IMM => reg[_dst] = (reg[_dst] as u32).wrapping_shr(insn.imm as u32) as u64,
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ebpf::RSH32_IMM => reg[_dst] = (reg[_dst] as u32).wrapping_shr(insn.imm as u32) as u64,
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ebpf::RSH32_REG => reg[_dst] = (reg[_dst] as u32).wrapping_shr(reg[_src] as u32) as u64,
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ebpf::RSH32_REG => reg[_dst] = (reg[_dst] as u32).wrapping_shr(reg[_src] as u32) as u64,
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ebpf::NEG32 => { reg[_dst] = (reg[_dst] as i32).wrapping_neg() as u64; reg[_dst] &= U32MAX; },
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ebpf::NEG32 => { reg[_dst] = (reg[_dst] as i32).wrapping_neg() as u64; reg[_dst] &= U32MAX; },
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+ ebpf::MOD32_IMM if insn.imm == 0 => (),
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ebpf::MOD32_IMM => reg[_dst] = (reg[_dst] as u32 % insn.imm as u32) as u64,
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ebpf::MOD32_IMM => reg[_dst] = (reg[_dst] as u32 % insn.imm as u32) as u64,
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- ebpf::MOD32_REG => {
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- if reg[_src] == 0 {
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- Err(Error::new(ErrorKind::Other,"Error: division by 0"))?;
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- }
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- reg[_dst] = (reg[_dst] as u32 % reg[_src] as u32) as u64;
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- },
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+ ebpf::MOD32_REG if reg[_src] == 0 => (),
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+ ebpf::MOD32_REG => reg[_dst] = (reg[_dst] as u32 % reg[_src] as u32) as u64,
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ebpf::XOR32_IMM => reg[_dst] = (reg[_dst] as u32 ^ insn.imm as u32) as u64,
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ebpf::XOR32_IMM => reg[_dst] = (reg[_dst] as u32 ^ insn.imm as u32) as u64,
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ebpf::XOR32_REG => reg[_dst] = (reg[_dst] as u32 ^ reg[_src] as u32) as u64,
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ebpf::XOR32_REG => reg[_dst] = (reg[_dst] as u32 ^ reg[_src] as u32) as u64,
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ebpf::MOV32_IMM => reg[_dst] = insn.imm as u32 as u64,
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ebpf::MOV32_IMM => reg[_dst] = insn.imm as u32 as u64,
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@@ -502,13 +496,10 @@ impl<'a> EbpfVmMbuff<'a> {
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ebpf::SUB64_REG => reg[_dst] = reg[_dst].wrapping_sub(reg[_src]),
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ebpf::SUB64_REG => reg[_dst] = reg[_dst].wrapping_sub(reg[_src]),
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ebpf::MUL64_IMM => reg[_dst] = reg[_dst].wrapping_mul(insn.imm as u64),
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ebpf::MUL64_IMM => reg[_dst] = reg[_dst].wrapping_mul(insn.imm as u64),
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ebpf::MUL64_REG => reg[_dst] = reg[_dst].wrapping_mul(reg[_src]),
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ebpf::MUL64_REG => reg[_dst] = reg[_dst].wrapping_mul(reg[_src]),
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+ ebpf::DIV64_IMM if insn.imm == 0 => reg[_dst] = 0,
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ebpf::DIV64_IMM => reg[_dst] /= insn.imm as u64,
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ebpf::DIV64_IMM => reg[_dst] /= insn.imm as u64,
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- ebpf::DIV64_REG => {
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- if reg[_src] == 0 {
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- Err(Error::new(ErrorKind::Other,"Error: division by 0"))?;
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- }
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- reg[_dst] /= reg[_src];
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- },
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+ ebpf::DIV64_REG if reg[_src] == 0 => reg[_dst] = 0,
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+ ebpf::DIV64_REG => reg[_dst] /= reg[_src],
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ebpf::OR64_IMM => reg[_dst] |= insn.imm as u64,
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ebpf::OR64_IMM => reg[_dst] |= insn.imm as u64,
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ebpf::OR64_REG => reg[_dst] |= reg[_src],
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ebpf::OR64_REG => reg[_dst] |= reg[_src],
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ebpf::AND64_IMM => reg[_dst] &= insn.imm as u64,
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ebpf::AND64_IMM => reg[_dst] &= insn.imm as u64,
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@@ -518,13 +509,10 @@ impl<'a> EbpfVmMbuff<'a> {
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ebpf::RSH64_IMM => reg[_dst] >>= insn.imm as u64,
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ebpf::RSH64_IMM => reg[_dst] >>= insn.imm as u64,
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ebpf::RSH64_REG => reg[_dst] >>= reg[_src],
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ebpf::RSH64_REG => reg[_dst] >>= reg[_src],
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ebpf::NEG64 => reg[_dst] = -(reg[_dst] as i64) as u64,
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ebpf::NEG64 => reg[_dst] = -(reg[_dst] as i64) as u64,
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+ ebpf::MOD64_IMM if insn.imm == 0 => (),
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ebpf::MOD64_IMM => reg[_dst] %= insn.imm as u64,
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ebpf::MOD64_IMM => reg[_dst] %= insn.imm as u64,
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- ebpf::MOD64_REG => {
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- if reg[_src] == 0 {
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- Err(Error::new(ErrorKind::Other,"Error: division by 0"))?;
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- }
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- reg[_dst] %= reg[_src];
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- },
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+ ebpf::MOD64_REG if reg[_src] == 0 => (),
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+ ebpf::MOD64_REG => reg[_dst] %= reg[_src],
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ebpf::XOR64_IMM => reg[_dst] ^= insn.imm as u64,
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ebpf::XOR64_IMM => reg[_dst] ^= insn.imm as u64,
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ebpf::XOR64_REG => reg[_dst] ^= reg[_src],
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ebpf::XOR64_REG => reg[_dst] ^= reg[_src],
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ebpf::MOV64_IMM => reg[_dst] = insn.imm as u64,
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ebpf::MOV64_IMM => reg[_dst] = insn.imm as u64,
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@@ -1058,7 +1046,7 @@ impl<'a> EbpfVmFixedMbuff<'a> {
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0 => std::ptr::null_mut(),
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0 => std::ptr::null_mut(),
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_ => mem.as_ptr() as *mut u8
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_ => mem.as_ptr() as *mut u8
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};
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};
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-
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+
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match self.parent.jit {
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match self.parent.jit {
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Some(jit) => Ok(jit(self.mbuff.buffer.as_ptr() as *mut u8,
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Some(jit) => Ok(jit(self.mbuff.buffer.as_ptr() as *mut u8,
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self.mbuff.buffer.len(),
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self.mbuff.buffer.len(),
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