Low level access to RISC-V processors
LoGin 4241a97627 feat: Add update_sum method to Sstatus struct (#8) | 6 months ago | |
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.github | 8 months ago | |
riscv | 6 months ago | |
riscv-pac | 8 months ago | |
riscv-peripheral | 8 months ago | |
riscv-rt | 7 months ago | |
riscv-semihosting | 10 months ago | |
.gitignore | 1 year ago | |
CODE_OF_CONDUCT.md | 4 years ago | |
Cargo.toml | 10 months ago | |
README.md | 10 months ago |
This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:
riscv
: CPU registers access and intrinsicsriscv-pac
: Common traits to be implemented by RISC-V PACsriscv-peripheral
: Interfaces for standard RISC-V peripheralsriscv-rt
: Startup code and interrupt handlingriscv-semihosting
: Semihosting for RISC-V processorsThis project is developed and maintained by the RISC-V team.
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.
Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.