Add examples

riscv-rt/Cargo.toml

@@ -15,3 +15,8 @@ riscv-rt-macros = { path = "macros", version = "0.1.5" }
 
 [features]
 inline-asm = ["riscv/inline-asm"]
+
+[dev-dependencies]
+riscv = "0.5.3"
+riscv-rt = "0.5.0"
+panic-halt = "0.2.0"

riscv-rt/examples/empty.rs

@@ -0,0 +1,13 @@
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+extern crate riscv_rt;
+
+use riscv_rt::entry;
+
+#[entry]
+fn main() -> ! {
+    // do something here
+    loop { }
+}

riscv-rt/examples/multi_core.rs

@@ -0,0 +1,56 @@
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+extern crate riscv;
+extern crate riscv_rt;
+
+use riscv::register::{mie, mip, mhartid};
+use riscv::asm::wfi;
+use riscv_rt::entry;
+
+#[export_name = "_mp_hook"]
+pub extern "Rust" fn user_mp_hook() -> bool {
+    let hartid = mhartid::read();
+    if hartid == 0 {
+        true
+    } else {
+        let addr = 0x02000000 + hartid * 4;
+        unsafe {
+            // Clear IPI
+            (addr as *mut u32).write_volatile(0);
+
+            // Start listening for software interrupts
+            mie::set_msoft();
+
+            loop {
+                wfi();
+                if mip::read().msoft() {
+                    break;
+                }
+            }
+
+            // Start listening for software interrupts
+            mie::clear_msoft();
+
+            // Clear IPI
+            (addr as *mut u32).write_volatile(0);
+        }
+        false
+    }
+}
+
+#[entry]
+fn main() -> ! {
+    let hartid = mhartid::read();
+
+    if hartid == 0 {
+        // Waking hart 1...
+        let addr = 0x02000004;
+        unsafe {
+            (addr as *mut u32).write_volatile(1);
+        }
+    }
+
+    loop { }
+}