Merge #28

28: Add support for 64-bit targets r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

riscv-rt/.travis.yml

@@ -1,36 +1,21 @@
 language: rust
 
-matrix:
-  include:
-    #- env: TARGET=x86_64-unknown-linux-gnu
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    #- env: TARGET=riscv32imac-unknown-none-elf
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    #- env: TARGET=x86_64-unknown-linux-gnu
-    #  rust: beta
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+rust:
+- nightly
+- stable
 
-    #- env: TARGET=riscv32imac-unknown-none-elf
-    #  rust: beta
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+env:
+- TARGET=x86_64-unknown-linux-gnu
+- TARGET=riscv32imac-unknown-none-elf
+- TARGET=riscv64imac-unknown-none-elf
 
-    - env: TARGET=x86_64-unknown-linux-gnu
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
-    - env: TARGET=riscv32imac-unknown-none-elf
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    - env: TARGET=x86_64-unknown-linux-gnu
-      rust: stable
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+matrix:
+  exclude:
+    - rust: stable
+      env: TARGET=riscv64imac-unknown-none-elf
 
-    - env: TARGET=riscv32imac-unknown-none-elf
-      rust: stable
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
 before_install: set -e
 

riscv-rt/Cargo.toml

@@ -10,7 +10,7 @@ license = "ISC"
 
 [dependencies]
 r0 = "0.2.2"
-riscv = "0.4.0"
+riscv = "0.5.0"
 
 [features]
 inline-asm = ["riscv/inline-asm"]

riscv-rt/asm.S

@@ -13,14 +13,12 @@ _start:
     .cfi_startproc
     .cfi_undefined ra
 
-    // .option push
-    // .option norelax
-    lui gp, %hi(__global_pointer$)
-    addi gp, gp, %lo(__global_pointer$)
-    // .option pop
-
-    lui sp, %hi(_stack_start)
-    addi sp, sp, %lo(_stack_start)
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop
+
+    la sp, _stack_start
 
     add s0, sp, zero
 

riscv-rt/assemble.sh

@@ -9,6 +9,10 @@ rm -f bin/*.a
 
 riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
 ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
-cp bin/riscv32imac-unknown-none-elf.a bin/riscv32imc-unknown-none-elf.a
+ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
+ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
 
 rm bin/$crate.o