use core::arch::global_asm

riscv-rt/asm/riscv32i-unknown-none-elf-m.s

@@ -0,0 +1,123 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0"
+	.file	"zk0t2u2b1an050m"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	mie, 0
+	csrwi	mip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	csrr	t2, mhartid
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	beqz	t2, .Ltmp0
+	mv	t1, t2
+	mv	t3, t0
+.Ltmp1:
+	add	t0, t0, t3
+	addi	t1, t1, -1
+	bnez	t1, .Ltmp1
+.Ltmp0:
+	sub	sp, sp, t0
+	add	s0, sp, zero
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	mret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort

riscv-rt/asm/riscv32i-unknown-none-elf-s.s

@@ -0,0 +1,123 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0"
+	.file	"eaqpawb8fun9h0d"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	sie, 0
+	csrwi	sip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	mv	t2, a0
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	beqz	t2, .Ltmp0
+	mv	t1, t2
+	mv	t3, t0
+.Ltmp1:
+	add	t0, t0, t3
+	addi	t1, t1, -1
+	bnez	t1, .Ltmp1
+.Ltmp0:
+	sub	sp, sp, t0
+	add	s0, sp, zero
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	sret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort

riscv-rt/asm/riscv32imac-unknown-none-elf-m.s

@@ -0,0 +1,116 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
+	.file	"3wdx7lxc78dgym21"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	mie, 0
+	csrwi	mip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	csrr	t2, mhartid
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	mret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort

riscv-rt/asm/riscv32imac-unknown-none-elf-s.s

@@ -0,0 +1,116 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
+	.file	"2mpkjzuft8hmeuib"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	sie, 0
+	csrwi	sip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	mv	t2, a0
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	sret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort

riscv-rt/asm/riscv64imac-unknown-none-elf-m.s

@@ -0,0 +1,126 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
+	.file	"1ruuache5c4x1fns"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	.option	push
+
+	.option	norelax
+.Ltmp0:
+	auipc	ra, %pcrel_hi(.Ltmp1)
+	ld	ra, %pcrel_lo(.Ltmp0)(ra)
+	ret
+	.p2align	3
+.Ltmp1:
+	.quad	_abs_start
+	.option	pop
+
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	mie, 0
+	csrwi	mip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	csrr	t2, mhartid
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -128
+	sd	ra, 0(sp)
+	sd	t0, 8(sp)
+	sd	t1, 16(sp)
+	sd	t2, 24(sp)
+	sd	t3, 32(sp)
+	sd	t4, 40(sp)
+	sd	t5, 48(sp)
+	sd	t6, 56(sp)
+	sd	a0, 64(sp)
+	sd	a1, 72(sp)
+	sd	a2, 80(sp)
+	sd	a3, 88(sp)
+	sd	a4, 96(sp)
+	sd	a5, 104(sp)
+	sd	a6, 112(sp)
+	sd	a7, 120(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	ld	ra, 0(sp)
+	ld	t0, 8(sp)
+	ld	t1, 16(sp)
+	ld	t2, 24(sp)
+	ld	t3, 32(sp)
+	ld	t4, 40(sp)
+	ld	t5, 48(sp)
+	ld	t6, 56(sp)
+	ld	a0, 64(sp)
+	ld	a1, 72(sp)
+	ld	a2, 80(sp)
+	ld	a3, 88(sp)
+	ld	a4, 96(sp)
+	ld	a5, 104(sp)
+	ld	a6, 112(sp)
+	ld	a7, 120(sp)
+	addi	sp, sp, 128
+	mret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort

riscv-rt/asm/riscv64imac-unknown-none-elf-s.s

@@ -0,0 +1,126 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
+	.file	"5194e8m2dkkkh98p"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	.option	push
+
+	.option	norelax
+.Ltmp0:
+	auipc	ra, %pcrel_hi(.Ltmp1)
+	ld	ra, %pcrel_lo(.Ltmp0)(ra)
+	ret
+	.p2align	3
+.Ltmp1:
+	.quad	_abs_start
+	.option	pop
+
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	sie, 0
+	csrwi	sip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	mv	t2, a0
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -128
+	sd	ra, 0(sp)
+	sd	t0, 8(sp)
+	sd	t1, 16(sp)
+	sd	t2, 24(sp)
+	sd	t3, 32(sp)
+	sd	t4, 40(sp)
+	sd	t5, 48(sp)
+	sd	t6, 56(sp)
+	sd	a0, 64(sp)
+	sd	a1, 72(sp)
+	sd	a2, 80(sp)
+	sd	a3, 88(sp)
+	sd	a4, 96(sp)
+	sd	a5, 104(sp)
+	sd	a6, 112(sp)
+	sd	a7, 120(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	ld	ra, 0(sp)
+	ld	t0, 8(sp)
+	ld	t1, 16(sp)
+	ld	t2, 24(sp)
+	ld	t3, 32(sp)
+	ld	t4, 40(sp)
+	ld	t5, 48(sp)
+	ld	t6, 56(sp)
+	ld	a0, 64(sp)
+	ld	a1, 72(sp)
+	ld	a2, 80(sp)
+	ld	a3, 88(sp)
+	ld	a4, 96(sp)
+	ld	a5, 104(sp)
+	ld	a6, 112(sp)
+	ld	a7, 120(sp)
+	addi	sp, sp, 128
+	sret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort

riscv-rt/assemble.ps1

@@ -1,27 +0,0 @@
-New-Item -Force -Name bin -Type Directory
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-Remove-Item -Force bin/*.a
-
-$crate = "riscv-rt"
-
-$extension_sets = @("i", "im", "ic", "imc", "if", "ifc", "imf", "imfc", "ifd", "ifdc", "imfd", "imfdc")
-
-$pwd = Get-Location
-
-foreach ($ext in $extension_sets)
-{
-    $abi = ""
-    if ($ext.contains("d"))
-        {$abi = "d"}
-    elseif ($ext.contains("f"))
-        {$abi = "f"}
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=ilp32$abi" "-march=rv32$ext" asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32$ext-unknown-none-elf.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=lp64$abi" "-march=rv64$ext" asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64$ext-unknown-none-elf.a bin/$crate.o
-}
-
-Remove-Item bin/$crate.o

riscv-rt/assemble.sh

@@ -1,44 +0,0 @@
-#!/bin/bash
-
-set -euxo pipefail
-
-crate=riscv-rt
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-rm -f bin/*.a
-
-exts=('i' 'ic' 'im' 'imc' 'if' 'ifc' 'imf' 'imfc' 'ifd' 'ifdc' 'imfd' 'imfdc')
-
-for ext in ${exts[@]}
-do
-    case $ext in
-
-        *'d'*)
-            abi='d'
-            ;;
-        
-        *'f'*)
-            abi='f'
-            ;;
-        
-        *)
-            abi=''
-            ;;
-    esac
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
-
-    #s-mode
-    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-smode.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-smode.a bin/$crate.o
-
-done
-
-rm bin/$crate.o

riscv-rt/build.rs

@@ -1,5 +1,4 @@
 // NOTE: Adapted from cortex-m/build.rs
-extern crate riscv_target;
 
 use riscv_target::Target;
 use std::env;
@@ -9,22 +8,24 @@ use std::path::PathBuf;
 fn main() {
     let target = env::var("TARGET").unwrap();
     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
-    let name = env::var("CARGO_PKG_NAME").unwrap();
+    let _name = env::var("CARGO_PKG_NAME").unwrap();
 
+    // set configuration flags depending on the target
     if target.starts_with("riscv") {
-        let mut target = Target::from_target_str(&target);
-        target.retain_extensions("imfdc");
-        let archive: String;
-        if cfg!(feature = "s-mode") {
-            println!("======== compiling riscv-rt for s-mode");
-            archive = format!("bin/{}-smode.a", target.to_string());
-        } else {
-            archive = format!("bin/{}.a", target.to_string());
+        println!("cargo:rustc-cfg=riscv");
+        let target = Target::from_target_str(&target);
+        match target.bits {
+            32 => {
+                println!("cargo:rustc-cfg=riscv32");
+            }
+            64 => {
+                println!("cargo:rustc-cfg=riscv64");
+            }
+            _ => panic!("Unsupported bit width"),
+        }
+        if target.has_extension('m') {
+            println!("cargo:rustc-cfg=riscvm"); // we can expose extensions this way
         }
-
-        fs::copy(&archive, out_dir.join(format!("lib{}.a", name))).unwrap();
-        println!("cargo:rerun-if-changed={}", archive);
-        println!("cargo:rustc-link-lib=static={}", name);
     }
 
     // Put the linker script somewhere the linker can find it

riscv-rt/check-blobs.sh

@@ -1,21 +1,3 @@
 #!/bin/bash
 
-# Checks that the blobs are up to date with the committed assembly files
-
-set -euxo pipefail
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.before
-done
-
-./assemble.sh
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.after
-done
-
-for cksum in $(ls bin/*.after); do
-    diff -u $cksum ${cksum%.after}.before
-done
+return 0 # not needed anymore

riscv-rt/examples/device.x

@@ -0,0 +1,14 @@
+MEMORY
+{
+    RAM : ORIGIN = 0x80000000, LENGTH = 16K
+    FLASH : ORIGIN = 0x20000000, LENGTH = 4M
+}
+
+REGION_ALIAS("REGION_TEXT", FLASH);
+REGION_ALIAS("REGION_RODATA", FLASH);
+REGION_ALIAS("REGION_DATA", RAM);
+REGION_ALIAS("REGION_BSS", RAM);
+REGION_ALIAS("REGION_HEAP", RAM);
+REGION_ALIAS("REGION_STACK", RAM);
+
+INCLUDE link.x

riscv-rt/src/asm.rs

@@ -0,0 +1,186 @@
+use core::arch::global_asm;
+
+/// Parse cfg attributes inside a global_asm call.
+macro_rules! cfg_global_asm {
+    {@inner, [$($x:tt)*], } => {
+        global_asm!{$($x)*}
+    };
+    (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
+        #[cfg($meta)]
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+        #[cfg(not($meta))]
+        cfg_global_asm!{@inner, [$($x)*], $($rest)*}
+    };
+    {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+    };
+    {$($asms:tt)*} => {
+        cfg_global_asm!{@inner, [], $($asms)*}
+    };
+}
+
+// Entry point of all programs (_start). It initializes DWARF call frame information,
+// the stack pointer, the frame pointer (needed for closures to work in start_rust)
+// and the global pointer. Then it calls _start_rust.
+cfg_global_asm!(
+    ".section .init, \"ax\"
+    .global _start
+
+_start:",
+    #[cfg(riscv32)]
+    "lui ra, %hi(_abs_start)
+     jr %lo(_abs_start)(ra)",
+    #[cfg(riscv64)]
+    ".option push
+    .option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
+1:
+    auipc ra, %pcrel_hi(1f)
+    ld ra, %pcrel_lo(1b)(ra)
+    jr ra
+    .align  3
+1:
+    .dword _abs_start
+    .option pop",
+    "
+_abs_start:
+    .option norelax
+    .cfi_startproc
+    .cfi_undefined ra",
+    #[cfg(feature = "s-mode")]
+    "csrw sie, 0
+    csrw sip, 0",
+    #[cfg(not(feature = "s-mode"))]
+    "csrw mie, 0
+    csrw mip, 0",
+    "li  x1, 0
+    li  x2, 0
+    li  x3, 0
+    li  x4, 0
+    li  x5, 0
+    li  x6, 0
+    li  x7, 0
+    li  x8, 0
+    li  x9, 0
+    // a0..a2 (x10..x12) skipped
+    li  x13, 0
+    li  x14, 0
+    li  x15, 0
+    li  x16, 0
+    li  x17, 0
+    li  x18, 0
+    li  x19, 0
+    li  x20, 0
+    li  x21, 0
+    li  x22, 0
+    li  x23, 0
+    li  x24, 0
+    li  x25, 0
+    li  x26, 0
+    li  x27, 0
+    li  x28, 0
+    li  x29, 0
+    li  x30, 0
+    li  x31, 0
+
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop",
+    #[cfg(feature = "s-mode")]
+    "mv t2, a0 // the hartid is passed as parameter by SMODE",
+    #[cfg(not(feature = "s-mode"))]
+    "csrr t2, mhartid",
+    "lui t0, %hi(_max_hart_id)
+    add t0, t0, %lo(_max_hart_id)
+    bgtu t2, t0, abort
+
+    // Allocate stacks
+    la sp, _stack_start
+    lui t0, %hi(_hart_stack_size)
+    add t0, t0, %lo(_hart_stack_size)",
+    #[cfg(riscvm)]
+    "mul t0, t2, t0",
+    #[cfg(not(riscvm))]
+    "beqz t2, 2f  // Jump if single-hart
+    mv t1, t2
+    mv t3, t0
+1:
+    add t0, t0, t3
+    addi t1, t1, -1
+    bnez t1, 1b
+2:  ",
+    "sub sp, sp, t0
+    
+    // Set frame pointer 
+    add s0, sp, zero
+
+    jal zero, _start_rust
+
+    .cfi_endproc",
+);
+
+/// Trap entry point (_start_trap). It saves caller saved registers, calls
+/// _start_trap_rust, restores caller saved registers and then returns.
+/// 
+/// # Usage
+/// 
+/// The macro takes 5 arguments:
+/// - `$STORE`: the instruction used to store a register in the stack (e.g. `sd` for riscv64)
+/// - `$LOAD`: the instruction used to load a register from the stack (e.g. `ld` for riscv64)
+/// - `$BYTES`: the number of bytes used to store a register (e.g. 8 for riscv64)
+/// - `$TRAP_SIZE`: the number of registers to store in the stack (e.g. 32 for all the user registers)
+/// - list of tuples of the form `($REG, $LOCATION)`, where:
+///     - `$REG`: the register to store/load
+///     - `$LOCATION`: the location in the stack where to store/load the register
+#[rustfmt::skip]
+macro_rules! trap_handler {
+    ($STORE:ident, $LOAD:ident, $BYTES:literal, $TRAP_SIZE:literal, [$(($REG:ident, $LOCATION:literal)),*]) => {
+        global_asm!(
+        "
+            .section .trap, \"ax\"
+            .global default_start_trap
+        default_start_trap:",
+            // save space for trap handler in stack
+            concat!("addi sp, sp, -", stringify!($TRAP_SIZE * $BYTES)),
+            // save registers in the desired order
+            $(concat!(stringify!($STORE), " ", stringify!($REG), ", ", stringify!($LOCATION * $BYTES), "(sp)"),)*
+            // call rust trap handler
+            "add a0, sp, zero
+            jal ra, _start_trap_rust",
+            // restore registers in the desired order
+            $(concat!(stringify!($LOAD), " ", stringify!($REG), ", ", stringify!($LOCATION * $BYTES), "(sp)"),)*
+            // free stack
+            concat!("addi sp, sp, ", stringify!($TRAP_SIZE * $BYTES)),
+        );
+        cfg_global_asm!(
+            // return from trap
+            #[cfg(feature = "s-mode")]
+            "sret",
+            #[cfg(not(feature = "s-mode"))]
+            "mret",
+        );
+    };
+}
+
+#[rustfmt::skip]
+#[cfg(riscv32)]
+trap_handler!(
+    sw, lw, 4, 16,
+    [(ra, 0), (t0, 1), (t1, 2), (t2, 3), (t3, 4), (t4, 5), (t5, 6), (t6, 7),
+     (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
+);
+#[rustfmt::skip]
+#[cfg(riscv64)]
+trap_handler!(
+    sd, ld, 8, 16,
+    [(ra, 0), (t0, 1), (t1, 2), (t2, 3), (t3, 4), (t4, 5), (t5, 6), (t6, 7),
+     (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
+);
+
+// Make sure there is an abort when linking
+global_asm!(
+    ".section .text.abort
+     .globl abort
+abort:
+    j abort"
+);

riscv-rt/src/lib.rs

@@ -359,6 +359,9 @@
 #![no_std]
 #![deny(missing_docs)]
 
+#[cfg(riscv)]
+mod asm;
+
 #[cfg(feature = "s-mode")]
 use riscv::register::{scause as xcause, stvec as xtvec, stvec::TrapMode as xTrapMode};