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+//! Minimal startup / runtime for RISC-V CPU's
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+//!
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+//! # Minimum Supported Rust Version (MSRV)
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+//!
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+//! This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
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+//! compile with older versions but that may change in any new patch release.
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+//!
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+//! # Features
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+//!
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+//! This crate provides
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+//!
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+//! - Before main initialization of the `.bss` and `.data` sections.
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+//!
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+//! - `#[entry]` to declare the entry point of the program
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+//! - `#[pre_init]` to run code *before* `static` variables are initialized
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+//!
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+//! - A linker script that encodes the memory layout of a generic RISC-V
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+//! microcontroller. This linker script is missing some information that must
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+//! be supplied through a `memory.x` file (see example below). This file
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+//! must be supplied using rustflags and listed *before* `link.x`. Arbitrary
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+//! filename can be use instead of `memory.x`.
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+//!
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+//! - A `_sheap` symbol at whose address you can locate a heap.
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+//!
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+//! - Support for a runtime in supervisor mode, that can be bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc)
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+//!
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+//! ``` text
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+//! $ cargo new --bin app && cd $_
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+//!
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+//! $ # add this crate as a dependency
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+//! $ edit Cargo.toml && cat $_
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+//! [dependencies]
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+//! riscv-rt = "0.6.1"
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+//! panic-halt = "0.2.0"
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+//!
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+//! $ # memory layout of the device
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+//! $ edit memory.x && cat $_
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+//! MEMORY
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+//! {
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+//! RAM : ORIGIN = 0x80000000, LENGTH = 16K
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+//! FLASH : ORIGIN = 0x20000000, LENGTH = 16M
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+//! }
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+//!
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+//! REGION_ALIAS("REGION_TEXT", FLASH);
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+//! REGION_ALIAS("REGION_RODATA", FLASH);
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+//! REGION_ALIAS("REGION_DATA", RAM);
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+//! REGION_ALIAS("REGION_BSS", RAM);
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+//! REGION_ALIAS("REGION_HEAP", RAM);
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+//! REGION_ALIAS("REGION_STACK", RAM);
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+//!
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+//! $ edit src/main.rs && cat $_
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+//! ```
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+//!
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+//! ``` ignore,no_run
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+//! #![no_std]
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+//! #![no_main]
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+//!
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+//! extern crate panic_halt;
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+//!
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+//! use riscv_rt::entry;
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+//!
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+//! // use `main` as the entry point of this application
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+//! // `main` is not allowed to return
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+//! #[entry]
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+//! fn main() -> ! {
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+//! // do something here
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+//! loop { }
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+//! }
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+//! ```
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+//!
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+//! ``` text
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+//! $ mkdir .cargo && edit .cargo/config && cat $_
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+//! [target.riscv32imac-unknown-none-elf]
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+//! rustflags = [
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+//! "-C", "link-arg=-Tmemory.x",
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+//! "-C", "link-arg=-Tlink.x",
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+//! ]
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+//!
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+//! [build]
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+//! target = "riscv32imac-unknown-none-elf"
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+//! $ edit build.rs && cat $_
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+//! ```
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+//!
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+//! ``` ignore,no_run
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+//! use std::env;
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+//! use std::fs;
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+//! use std::path::PathBuf;
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+//!
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+//! fn main() {
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+//! let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
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+//!
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+//! // Put the linker script somewhere the linker can find it.
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+//! fs::write(out_dir.join("memory.x"), include_bytes!("memory.x")).unwrap();
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+//! println!("cargo:rustc-link-search={}", out_dir.display());
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+//! println!("cargo:rerun-if-changed=memory.x");
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+//!
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+//! println!("cargo:rerun-if-changed=build.rs");
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+//! }
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+//! ```
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+//!
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+//! ``` text
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+//! $ cargo build
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+//!
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+//! $ riscv32-unknown-elf-objdump -Cd $(find target -name app) | head
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+//!
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+//! Disassembly of section .text:
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+//!
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+//! 20000000 <_start>:
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+//! 20000000: 800011b7 lui gp,0x80001
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+//! 20000004: 80018193 addi gp,gp,-2048 # 80000800 <_stack_start+0xffffc800>
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+//! 20000008: 80004137 lui sp,0x80004
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+//! ```
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+//!
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+//! # Symbol interfaces
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+//!
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+//! This crate makes heavy use of symbols, linker sections and linker scripts to
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+//! provide most of its functionality. Below are described the main symbol
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+//! interfaces.
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+//!
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+//! ## `memory.x`
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+//!
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+//! This file supplies the information about the device to the linker.
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+//!
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+//! ### `MEMORY`
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+//!
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+//! The main information that this file must provide is the memory layout of
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+//! the device in the form of the `MEMORY` command. The command is documented
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+//! [here][2], but at a minimum you'll want to create at least one memory region.
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+//!
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+//! [2]: https://sourceware.org/binutils/docs/ld/MEMORY.html
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+//!
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+//! To support different relocation models (RAM-only, FLASH+RAM) multiple regions are used:
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+//!
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+//! - `REGION_TEXT` - for `.init`, `.trap` and `.text` sections
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+//! - `REGION_RODATA` - for `.rodata` section and storing initial values for `.data` section
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+//! - `REGION_DATA` - for `.data` section
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+//! - `REGION_BSS` - for `.bss` section
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+//! - `REGION_HEAP` - for the heap area
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+//! - `REGION_STACK` - for hart stacks
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+//!
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+//! Specific aliases for these regions must be defined in `memory.x` file (see example below).
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+//!
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+//! ### `_stext`
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+//!
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+//! This symbol provides the loading address of `.text` section. This value can be changed
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+//! to override the loading address of the firmware (for example, in case of bootloader present).
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+//!
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+//! If omitted this symbol value will default to `ORIGIN(REGION_TEXT)`.
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+//!
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+//! ### `_stack_start`
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+//!
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+//! This symbol provides the address at which the call stack will be allocated.
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+//! The call stack grows downwards so this address is usually set to the highest
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+//! valid RAM address plus one (this *is* an invalid address but the processor
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+//! will decrement the stack pointer *before* using its value as an address).
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+//!
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+//! In case of multiple harts present, this address defines the initial stack pointer for hart 0.
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+//! Stack pointer for hart `N` is calculated as `_stack_start - N * _hart_stack_size`.
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+//!
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+//! If omitted this symbol value will default to `ORIGIN(REGION_STACK) + LENGTH(REGION_STACK)`.
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+//!
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+//! #### Example
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+//!
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+//! Allocating the call stack on a different RAM region.
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+//!
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+//! ``` text
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+//! MEMORY
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+//! {
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+//! L2_LIM : ORIGIN = 0x08000000, LENGTH = 1M
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+//! RAM : ORIGIN = 0x80000000, LENGTH = 16K
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+//! FLASH : ORIGIN = 0x20000000, LENGTH = 16M
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+//! }
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+//!
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+//! REGION_ALIAS("REGION_TEXT", FLASH);
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+//! REGION_ALIAS("REGION_RODATA", FLASH);
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+//! REGION_ALIAS("REGION_DATA", RAM);
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+//! REGION_ALIAS("REGION_BSS", RAM);
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+//! REGION_ALIAS("REGION_HEAP", RAM);
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+//! REGION_ALIAS("REGION_STACK", L2_LIM);
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+//!
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+//! _stack_start = ORIGIN(L2_LIM) + LENGTH(L2_LIM);
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+//! ```
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+//!
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+//! ### `_max_hart_id`
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+//!
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+//! This symbol defines the maximum hart id supported. All harts with id
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+//! greater than `_max_hart_id` will be redirected to `abort()`.
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+//!
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+//! This symbol is supposed to be redefined in platform support crates for
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+//! multi-core targets.
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+//!
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+//! If omitted this symbol value will default to 0 (single core).
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+//!
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+//! ### `_hart_stack_size`
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+//!
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+//! This symbol defines stack area size for *one* hart.
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+//!
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+//! If omitted this symbol value will default to 2K.
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+//!
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+//! ### `_heap_size`
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+//!
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+//! This symbol provides the size of a heap region. The default value is 0. You can set `_heap_size`
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+//! to a non-zero value if you are planning to use heap allocations.
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+//!
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+//! ### `_sheap`
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+//!
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+//! This symbol is located in RAM right after the `.bss` and `.data` sections.
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+//! You can use the address of this symbol as the start address of a heap
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+//! region. This symbol is 4 byte aligned so that address will be a multiple of 4.
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+//!
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+//! #### Example
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+//!
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+//! ``` no_run
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+//! extern crate some_allocator;
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+//!
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+//! extern "C" {
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+//! static _sheap: u8;
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+//! static _heap_size: u8;
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+//! }
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+//!
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+//! fn main() {
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+//! unsafe {
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+//! let heap_bottom = &_sheap as *const u8 as usize;
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+//! let heap_size = &_heap_size as *const u8 as usize;
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+//! some_allocator::initialize(heap_bottom, heap_size);
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+//! }
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+//! }
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+//! ```
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+//!
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+//! ### `_mp_hook`
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+//!
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+//! This function is called from all the harts and must return true only for one hart,
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+//! which will perform memory initialization. For other harts it must return false
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+//! and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
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+//! The parameter `hartid` specifies the hartid of the caller.
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+//!
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+//! This function can be redefined in the following way:
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+//!
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+//! ``` no_run
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+//! #[export_name = "_mp_hook"]
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+//! pub extern "Rust" fn mp_hook(hartid: usize) -> bool {
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+//! // ...
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+//! }
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+//! ```
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+//!
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+//! Default implementation of this function wakes hart 0 and busy-loops all the other harts.
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+//!
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+//! ### `ExceptionHandler`
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+//!
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+//! This function is called when exception is occured. The exception reason can be decoded from the
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+//! `mcause`/`scause` register.
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+//!
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+//! This function can be redefined in the following way:
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+//!
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+//! ``` no_run
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+//! #[export_name = "ExceptionHandler"]
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+//! fn custom_exception_handler(trap_frame: &riscv_rt::TrapFrame) -> ! {
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+//! // ...
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+//! }
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+//! ```
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+//! or
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+//! ``` no_run
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+//! #[no_mangle]
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+//! fn ExceptionHandler(trap_frame: &riscv_rt::TrapFrame) -> ! {
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+//! // ...
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+//! }
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+//! ```
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+//!
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+//! Default implementation of this function stucks in a busy-loop.
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+//!
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+//!
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+//! ### Core interrupt handlers
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+//!
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+//! This functions are called when corresponding interrupt is occured.
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+//! You can define an interrupt handler with one of the following names:
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+//! * `UserSoft`
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+//! * `SupervisorSoft`
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+//! * `MachineSoft`
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+//! * `UserTimer`
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+//! * `SupervisorTimer`
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+//! * `MachineTimer`
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+//! * `UserExternal`
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+//! * `SupervisorExternal`
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+//! * `MachineExternal`
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+//!
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+//! For example:
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+//! ``` no_run
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+//! #[export_name = "MachineTimer"]
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+//! fn custom_timer_handler() {
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+//! // ...
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+//! }
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+//! ```
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+//! or
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+//! ``` no_run
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+//! #[no_mangle]
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+//! fn MachineTimer() {
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+//! // ...
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+//! }
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+//! ```
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+//!
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+//! If interrupt handler is not explicitly defined, `DefaultHandler` is called.
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+//!
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+//! ### `DefaultHandler`
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+//!
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+//! This function is called when interrupt without defined interrupt handler is occured.
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+//! The interrupt reason can be decoded from the `mcause`/`scause` register.
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+//!
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+//! This function can be redefined in the following way:
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+//!
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+//! ``` no_run
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+//! #[export_name = "DefaultHandler"]
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+//! fn custom_interrupt_handler() {
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+//! // ...
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+//! }
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+//! ```
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+//! or
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+//! ``` no_run
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+//! #[no_mangle]
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+//! fn DefaultHandler() {
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+//! // ...
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+//! }
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+//! ```
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+//!
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+//! Default implementation of this function stucks in a busy-loop.
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+//!
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+//! # Features
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+//!
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+//! ## `single-hart`
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+//!
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+//! This feature saves a little code size if there is only one hart on the target.
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+//!
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+//! ## `s-mode`
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+//!
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+//! The supervisor mode feature (`s-mode`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).
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+//!
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+//! For example:
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+//! ``` text
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+//! [dependencies]
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+//! riscv-rt = {features=["s-mode"]}
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+//! ```
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+//! Internally, riscv-rt uses different versions of precompiled static libraries
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+//! for (i) machine mode and (ii) supervisor mode. If the `s-mode` feature was activated,
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+//! the build script selects the s-mode library. While most registers/instructions have variants for
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+//! both `mcause` and `scause`, the `mhartid` hardware thread register is not available in supervisor
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+//! mode. Instead, the hartid is passed as parameter by a bootstrapping firmware (i.e., SBI).
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+//!
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+//! Use case: QEMU supports [OpenSBI](https://github.com/riscv-software-src/opensbi) as default firmware.
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+//! Using the SBI requires riscv-rt to be run in supervisor mode instead of machine mode.
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+//! ``` text
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+//! APP_BINARY=$(find target -name app)
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+//! sudo qemu-system-riscv64 -m 2G -nographic -machine virt -kernel $APP_BINARY
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+//! ```
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+//! It requires the memory layout to be non-overlapping, like
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+//! ``` text
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+//! MEMORY
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+//! {
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+//! RAM : ORIGIN = 0x80200000, LENGTH = 0x8000000
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+//! FLASH : ORIGIN = 0x20000000, LENGTH = 16M
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+//! }
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+//! ```
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+
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+// NOTE: Adapted from cortex-m/src/lib.rs
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+#![no_std]
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+#![deny(missing_docs)]
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+
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+#[cfg(riscv)]
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+mod asm;
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+
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+use core::sync::atomic::{compiler_fence, Ordering};
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+
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+#[cfg(feature = "s-mode")]
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+use riscv::register::{scause as xcause, stvec as xtvec, stvec::TrapMode as xTrapMode};
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+
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+#[cfg(not(feature = "s-mode"))]
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+use riscv::register::{mcause as xcause, mtvec as xtvec, mtvec::TrapMode as xTrapMode};
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+
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+#[cfg(all(not(feature = "single-hart"), not(feature = "s-mode")))]
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+use riscv::register::mhartid;
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+
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+pub use riscv_rt_macros::{entry, pre_init};
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+
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+#[export_name = "error: riscv-rt appears more than once in the dependency graph"]
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+#[doc(hidden)]
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+pub static __ONCE__: () = ();
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+
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+/// Rust entry point (_start_rust)
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+///
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+/// Zeros bss section, initializes data section and calls main. This function never returns.
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+///
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+/// # Safety
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+///
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+/// This function must be called only from assembly `_start` function.
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|
+/// Do **NOT** call this function directly.
|
|
|
+#[link_section = ".init.rust"]
|
|
|
+#[export_name = "_start_rust"]
|
|
|
+pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
|
|
|
+ #[rustfmt::skip]
|
|
|
+ extern "Rust" {
|
|
|
+ // This symbol will be provided by the user via `#[entry]`
|
|
|
+ fn main(a0: usize, a1: usize, a2: usize) -> !;
|
|
|
+
|
|
|
+ // This symbol will be provided by the user via `#[pre_init]`
|
|
|
+ fn __pre_init();
|
|
|
+
|
|
|
+ fn _setup_interrupts();
|
|
|
+
|
|
|
+ fn _mp_hook(hartid: usize) -> bool;
|
|
|
+ }
|
|
|
+
|
|
|
+ #[cfg(not(feature = "single-hart"))]
|
|
|
+ let run_init = {
|
|
|
+ // sbi passes hartid as first parameter (a0)
|
|
|
+ #[cfg(feature = "s-mode")]
|
|
|
+ let hartid = a0;
|
|
|
+ #[cfg(not(feature = "s-mode"))]
|
|
|
+ let hartid = mhartid::read();
|
|
|
+
|
|
|
+ _mp_hook(hartid)
|
|
|
+ };
|
|
|
+ #[cfg(feature = "single-hart")]
|
|
|
+ let run_init = true;
|
|
|
+
|
|
|
+ if run_init {
|
|
|
+ __pre_init();
|
|
|
+
|
|
|
+ // Initialize RAM
|
|
|
+ // 1. Copy over .data from flash to RAM
|
|
|
+ // 2. Zero out .bss
|
|
|
+
|
|
|
+ #[cfg(target_arch = "riscv32")]
|
|
|
+ core::arch::asm!(
|
|
|
+ "
|
|
|
+ // Copy over .data
|
|
|
+ la {start},_sdata
|
|
|
+ la {end},_edata
|
|
|
+ la {input},_sidata
|
|
|
+
|
|
|
+ bgeu {start},{end},2f
|
|
|
+ 1:
|
|
|
+ lw {a},0({input})
|
|
|
+ addi {input},{input},4
|
|
|
+ sw {a},0({start})
|
|
|
+ addi {start},{start},4
|
|
|
+ bltu {start},{end},1b
|
|
|
+
|
|
|
+ 2:
|
|
|
+ li {a},0
|
|
|
+ li {input},0
|
|
|
+
|
|
|
+ // Zero out .bss
|
|
|
+ la {start},_sbss
|
|
|
+ la {end},_ebss
|
|
|
+
|
|
|
+ bgeu {start},{end},3f
|
|
|
+ 2:
|
|
|
+ sw zero,0({start})
|
|
|
+ addi {start},{start},4
|
|
|
+ bltu {start},{end},2b
|
|
|
+
|
|
|
+ 3:
|
|
|
+ li {start},0
|
|
|
+ li {end},0
|
|
|
+ ",
|
|
|
+ start = out(reg) _,
|
|
|
+ end = out(reg) _,
|
|
|
+ input = out(reg) _,
|
|
|
+ a = out(reg) _,
|
|
|
+ );
|
|
|
+
|
|
|
+ #[cfg(target_arch = "riscv64")]
|
|
|
+ core::arch::asm!(
|
|
|
+ "
|
|
|
+ // Copy over .data
|
|
|
+ la {start},_sdata
|
|
|
+ la {end},_edata
|
|
|
+ la {input},_sidata
|
|
|
+
|
|
|
+ bgeu {start},{end},2f
|
|
|
+
|
|
|
+ 1: // .data Main Loop
|
|
|
+ ld {a},0({input})
|
|
|
+ addi {input},{input},8
|
|
|
+ sd {a},0({start})
|
|
|
+ addi {start},{start},8
|
|
|
+ bltu {start},{end},1b
|
|
|
+
|
|
|
+ 2: // .data zero registers
|
|
|
+ li {a},0
|
|
|
+ li {input},0
|
|
|
+
|
|
|
+ la {start},_sbss
|
|
|
+ la {end},_ebss
|
|
|
+
|
|
|
+ bgeu {start},{end},4f
|
|
|
+
|
|
|
+ 3: // .bss main loop
|
|
|
+ sd zero,0({start})
|
|
|
+ addi {start},{start},8
|
|
|
+ bltu {start},{end},3b
|
|
|
+
|
|
|
+ 4: // .bss zero registers
|
|
|
+ // Zero out used registers
|
|
|
+ li {start},0
|
|
|
+ li {end},0
|
|
|
+ ",
|
|
|
+ start = out(reg) _,
|
|
|
+ end = out(reg) _,
|
|
|
+ input = out(reg) _,
|
|
|
+ a = out(reg) _,
|
|
|
+ );
|
|
|
+
|
|
|
+ compiler_fence(Ordering::SeqCst);
|
|
|
+ }
|
|
|
+
|
|
|
+ // TODO: Enable FPU when available
|
|
|
+
|
|
|
+ _setup_interrupts();
|
|
|
+
|
|
|
+ main(a0, a1, a2);
|
|
|
+}
|
|
|
+
|
|
|
+/// Registers saved in trap handler
|
|
|
+#[allow(missing_docs)]
|
|
|
+#[repr(C)]
|
|
|
+#[derive(Debug)]
|
|
|
+pub struct TrapFrame {
|
|
|
+ pub ra: usize,
|
|
|
+ pub t0: usize,
|
|
|
+ pub t1: usize,
|
|
|
+ pub t2: usize,
|
|
|
+ pub t3: usize,
|
|
|
+ pub t4: usize,
|
|
|
+ pub t5: usize,
|
|
|
+ pub t6: usize,
|
|
|
+ pub a0: usize,
|
|
|
+ pub a1: usize,
|
|
|
+ pub a2: usize,
|
|
|
+ pub a3: usize,
|
|
|
+ pub a4: usize,
|
|
|
+ pub a5: usize,
|
|
|
+ pub a6: usize,
|
|
|
+ pub a7: usize,
|
|
|
+}
|
|
|
+
|
|
|
+/// Trap entry point rust (_start_trap_rust)
|
|
|
+///
|
|
|
+/// `scause`/`mcause` is read to determine the cause of the trap. XLEN-1 bit indicates
|
|
|
+/// if it's an interrupt or an exception. The result is examined and ExceptionHandler
|
|
|
+/// or one of the core interrupt handlers is called.
|
|
|
+///
|
|
|
+/// # Safety
|
|
|
+///
|
|
|
+/// This function must be called only from assembly `_start_trap` function.
|
|
|
+/// Do **NOT** call this function directly.
|
|
|
+#[link_section = ".trap.rust"]
|
|
|
+#[export_name = "_start_trap_rust"]
|
|
|
+pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
|
|
|
+ extern "C" {
|
|
|
+ fn ExceptionHandler(trap_frame: &TrapFrame);
|
|
|
+ fn DefaultHandler();
|
|
|
+ }
|
|
|
+
|
|
|
+ let cause = xcause::read();
|
|
|
+
|
|
|
+ if cause.is_exception() {
|
|
|
+ ExceptionHandler(&*trap_frame)
|
|
|
+ } else if cause.code() < __INTERRUPTS.len() {
|
|
|
+ let h = &__INTERRUPTS[cause.code()];
|
|
|
+ if h.reserved == 0 {
|
|
|
+ DefaultHandler();
|
|
|
+ } else {
|
|
|
+ (h.handler)();
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ DefaultHandler();
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#[doc(hidden)]
|
|
|
+#[no_mangle]
|
|
|
+#[allow(unused_variables, non_snake_case)]
|
|
|
+pub fn DefaultExceptionHandler(trap_frame: &TrapFrame) -> ! {
|
|
|
+ loop {
|
|
|
+ // Prevent this from turning into a UDF instruction
|
|
|
+ // see rust-lang/rust#28728 for details
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#[doc(hidden)]
|
|
|
+#[no_mangle]
|
|
|
+#[allow(unused_variables, non_snake_case)]
|
|
|
+pub fn DefaultInterruptHandler() {
|
|
|
+ loop {
|
|
|
+ // Prevent this from turning into a UDF instruction
|
|
|
+ // see rust-lang/rust#28728 for details
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/* Interrupts */
|
|
|
+#[doc(hidden)]
|
|
|
+pub enum Interrupt {
|
|
|
+ UserSoft,
|
|
|
+ SupervisorSoft,
|
|
|
+ MachineSoft,
|
|
|
+ UserTimer,
|
|
|
+ SupervisorTimer,
|
|
|
+ MachineTimer,
|
|
|
+ UserExternal,
|
|
|
+ SupervisorExternal,
|
|
|
+ MachineExternal,
|
|
|
+}
|
|
|
+
|
|
|
+pub use self::Interrupt as interrupt;
|
|
|
+
|
|
|
+extern "C" {
|
|
|
+ fn UserSoft();
|
|
|
+ fn SupervisorSoft();
|
|
|
+ fn MachineSoft();
|
|
|
+ fn UserTimer();
|
|
|
+ fn SupervisorTimer();
|
|
|
+ fn MachineTimer();
|
|
|
+ fn UserExternal();
|
|
|
+ fn SupervisorExternal();
|
|
|
+ fn MachineExternal();
|
|
|
+}
|
|
|
+
|
|
|
+#[doc(hidden)]
|
|
|
+pub union Vector {
|
|
|
+ pub handler: unsafe extern "C" fn(),
|
|
|
+ pub reserved: usize,
|
|
|
+}
|
|
|
+
|
|
|
+#[doc(hidden)]
|
|
|
+#[no_mangle]
|
|
|
+pub static __INTERRUPTS: [Vector; 12] = [
|
|
|
+ Vector { handler: UserSoft },
|
|
|
+ Vector {
|
|
|
+ handler: SupervisorSoft,
|
|
|
+ },
|
|
|
+ Vector { reserved: 0 },
|
|
|
+ Vector {
|
|
|
+ handler: MachineSoft,
|
|
|
+ },
|
|
|
+ Vector { handler: UserTimer },
|
|
|
+ Vector {
|
|
|
+ handler: SupervisorTimer,
|
|
|
+ },
|
|
|
+ Vector { reserved: 0 },
|
|
|
+ Vector {
|
|
|
+ handler: MachineTimer,
|
|
|
+ },
|
|
|
+ Vector {
|
|
|
+ handler: UserExternal,
|
|
|
+ },
|
|
|
+ Vector {
|
|
|
+ handler: SupervisorExternal,
|
|
|
+ },
|
|
|
+ Vector { reserved: 0 },
|
|
|
+ Vector {
|
|
|
+ handler: MachineExternal,
|
|
|
+ },
|
|
|
+];
|
|
|
+
|
|
|
+#[doc(hidden)]
|
|
|
+#[no_mangle]
|
|
|
+#[rustfmt::skip]
|
|
|
+pub unsafe extern "Rust" fn default_pre_init() {}
|
|
|
+
|
|
|
+#[doc(hidden)]
|
|
|
+#[no_mangle]
|
|
|
+#[rustfmt::skip]
|
|
|
+#[cfg(not(feature = "single-hart"))]
|
|
|
+pub extern "Rust" fn default_mp_hook(hartid: usize) -> bool {
|
|
|
+ match hartid {
|
|
|
+ 0 => true,
|
|
|
+ _ => loop {
|
|
|
+ unsafe { riscv::asm::wfi() }
|
|
|
+ },
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/// Default implementation of `_setup_interrupts` that sets `mtvec`/`stvec` to a trap handler address.
|
|
|
+#[doc(hidden)]
|
|
|
+#[no_mangle]
|
|
|
+#[rustfmt::skip]
|
|
|
+pub unsafe extern "Rust" fn default_setup_interrupts() {
|
|
|
+ extern "C" {
|
|
|
+ fn _start_trap();
|
|
|
+ }
|
|
|
+
|
|
|
+ xtvec::write(_start_trap as usize, xTrapMode::Direct);
|
|
|
+}
|
Román Cárdenas