Merge pull request #118 from rust-embedded/global_asm

Use inline assembly instead of pre-compiled blobs

riscv-rt/.github/workflows/blobs.yaml

@@ -1,17 +0,0 @@
-on:
-  push:
-    branches: [ master ]
-  pull_request:
-  merge_group:
-
-name: Check blobs
-
-jobs:
-  blobs:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v3
-      - name: Install riscv gcc
-        run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
-      - name: Check blobs
-        run: ./check-blobs.sh

riscv-rt/.github/workflows/build.yaml

@@ -18,6 +18,9 @@ jobs:
           - riscv32imac-unknown-none-elf
           - riscv64imac-unknown-none-elf
           - riscv64gc-unknown-none-elf
+        example:
+          - empty
+          - multi_core
         cargo_flags: [ "--no-default-features", "--all-features" ]
         include:
           # Nightly is only for reference and allowed to fail
@@ -33,6 +36,8 @@ jobs:
           targets: ${{ matrix.target }}
       - name: Build library
         run: cargo build --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
+      - name: Build example
+        run: RUSTFLAGS="-C link-arg=-Texamples/device.x" cargo build --target ${{ matrix.target }} --example ${{ matrix.example }} ${{ matrix.cargo_flags }}
   
   # Job to check that all the builds succeeded
   build-check:
@@ -42,4 +47,3 @@ jobs:
     if: always()
     steps:
       - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
-  

riscv-rt/.gitignore

@@ -3,3 +3,5 @@ target/
 bin/*.after
 bin/*.before
 bin/*.o
+
+.vscode/

riscv-rt/CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Use inline assembly instead of pre-compiled blobs
 - Removed bors in favor of GitHub Merge Queue
 
 ## [v0.11.0] - 2023-01-18

riscv-rt/asm.S

@@ -1,189 +0,0 @@
-#if __riscv_xlen == 64
-# define STORE    sd
-# define LOAD     ld
-# define LOG_REGBYTES 3
-#else
-# define STORE    sw
-# define LOAD     lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-/*
-    Entry point of all programs (_start).
-
-    It initializes DWARF call frame information, the stack pointer, the
-    frame pointer (needed for closures to work in start_rust) and the global
-    pointer. Then it calls _start_rust.
-*/
-
-.section .init, "ax"
-.global _start
-
-_start:
-    /* Jump to the absolute address defined by the linker script. */
-    // for 32bit
-    .if __riscv_xlen == 32
-    lui ra, %hi(_abs_start)
-    jr %lo(_abs_start)(ra)
-    .endif
-
-    // for 64bit
-    .if __riscv_xlen == 64
-.option push
-.option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
-1:
-    auipc ra, %pcrel_hi(1f)
-    ld ra, %pcrel_lo(1b)(ra)
-    jr ra
-    .align  3
-1:
-    .dword _abs_start
-.option pop
-    .endif
-
-_abs_start:
-    .cfi_startproc
-    .cfi_undefined ra
-
-    #ifdef SMODE
-    csrw sie, 0     // interrupt disable 
-    csrw sip, 0     // no pending interrupts
-    #else
-    csrw mie, 0
-    csrw mip, 0
-    #endif
-    
-
-    li  x1, 0
-    li  x2, 0
-    li  x3, 0
-    li  x4, 0
-    li  x5, 0
-    li  x6, 0
-    li  x7, 0
-    li  x8, 0
-    li  x9, 0
-    // a0..a2 (x10..x12) skipped
-    li  x13,0
-    li  x14,0
-    li  x15,0
-    li  x16,0
-    li  x17,0
-    li  x18,0
-    li  x19,0
-    li  x20,0
-    li  x21,0
-    li  x22,0
-    li  x23,0
-    li  x24,0
-    li  x25,0
-    li  x26,0
-    li  x27,0
-    li  x28,0
-    li  x29,0
-    li  x30,0
-    li  x31,0
-
-    .option push
-    .option norelax
-    la gp, __global_pointer$
-    .option pop
-
-    #ifdef SMODE
-    // there is no equivalent of mhartid in supervisor mode.
-    // instead, the hartid is passed as paramter by SMODE
-    mv t2, a0   
-    #else 
-    csrr t2, mhartid
-    #endif
-    lui t0, %hi(_max_hart_id)
-    add t0, t0, %lo(_max_hart_id)
-    bgtu t2, t0, abort
-
-    // Allocate stacks
-    la sp, _stack_start
-    lui t0, %hi(_hart_stack_size)
-    add t0, t0, %lo(_hart_stack_size)
-#ifdef __riscv_mul
-    mul t0, t2, t0
-#else
-    beqz t2, 2f  // Jump if single-hart
-    mv t1, t2
-    mv t3, t0
-1:
-    add t0, t0, t3
-    addi t1, t1, -1
-    bnez t1, 1b
-2:
-#endif
-    sub sp, sp, t0
-
-    // Set frame pointer
-    add s0, sp, zero
-
-    jal zero, _start_rust
-
-    .cfi_endproc
-
-/*
-    Trap entry point (_start_trap)
-
-    Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
-    restores caller saved registers and then returns.
-*/
-.section .trap, "ax"
-.global default_start_trap
-
-default_start_trap:
-    addi sp, sp, -16*REGBYTES
-
-    STORE ra, 0*REGBYTES(sp)
-    STORE t0, 1*REGBYTES(sp)
-    STORE t1, 2*REGBYTES(sp)
-    STORE t2, 3*REGBYTES(sp)
-    STORE t3, 4*REGBYTES(sp)
-    STORE t4, 5*REGBYTES(sp)
-    STORE t5, 6*REGBYTES(sp)
-    STORE t6, 7*REGBYTES(sp)
-    STORE a0, 8*REGBYTES(sp)
-    STORE a1, 9*REGBYTES(sp)
-    STORE a2, 10*REGBYTES(sp)
-    STORE a3, 11*REGBYTES(sp)
-    STORE a4, 12*REGBYTES(sp)
-    STORE a5, 13*REGBYTES(sp)
-    STORE a6, 14*REGBYTES(sp)
-    STORE a7, 15*REGBYTES(sp)
-
-    add a0, sp, zero
-    jal ra, _start_trap_rust
-
-    LOAD ra, 0*REGBYTES(sp)
-    LOAD t0, 1*REGBYTES(sp)
-    LOAD t1, 2*REGBYTES(sp)
-    LOAD t2, 3*REGBYTES(sp)
-    LOAD t3, 4*REGBYTES(sp)
-    LOAD t4, 5*REGBYTES(sp)
-    LOAD t5, 6*REGBYTES(sp)
-    LOAD t6, 7*REGBYTES(sp)
-    LOAD a0, 8*REGBYTES(sp)
-    LOAD a1, 9*REGBYTES(sp)
-    LOAD a2, 10*REGBYTES(sp)
-    LOAD a3, 11*REGBYTES(sp)
-    LOAD a4, 12*REGBYTES(sp)
-    LOAD a5, 13*REGBYTES(sp)
-    LOAD a6, 14*REGBYTES(sp)
-    LOAD a7, 15*REGBYTES(sp)
-
-    addi sp, sp, 16*REGBYTES
-    #ifdef SMODE
-    sret
-    #else
-    mret
-    #endif
-
-/* Make sure there is an abort when linking */
-.section .text.abort
-.globl abort
-abort:
-    j abort

riscv-rt/assemble.ps1

@@ -1,27 +0,0 @@
-New-Item -Force -Name bin -Type Directory
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-Remove-Item -Force bin/*.a
-
-$crate = "riscv-rt"
-
-$extension_sets = @("i", "im", "ic", "imc", "if", "ifc", "imf", "imfc", "ifd", "ifdc", "imfd", "imfdc")
-
-$pwd = Get-Location
-
-foreach ($ext in $extension_sets)
-{
-    $abi = ""
-    if ($ext.contains("d"))
-        {$abi = "d"}
-    elseif ($ext.contains("f"))
-        {$abi = "f"}
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=ilp32$abi" "-march=rv32$ext" asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32$ext-unknown-none-elf.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=lp64$abi" "-march=rv64$ext" asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64$ext-unknown-none-elf.a bin/$crate.o
-}
-
-Remove-Item bin/$crate.o

riscv-rt/assemble.sh

@@ -1,44 +0,0 @@
-#!/bin/bash
-
-set -euxo pipefail
-
-crate=riscv-rt
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-rm -f bin/*.a
-
-exts=('i' 'ic' 'im' 'imc' 'if' 'ifc' 'imf' 'imfc' 'ifd' 'ifdc' 'imfd' 'imfdc')
-
-for ext in ${exts[@]}
-do
-    case $ext in
-
-        *'d'*)
-            abi='d'
-            ;;
-        
-        *'f'*)
-            abi='f'
-            ;;
-        
-        *)
-            abi=''
-            ;;
-    esac
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
-
-    #s-mode
-    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-smode.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-smode.a bin/$crate.o
-
-done
-
-rm bin/$crate.o

riscv-rt/build.rs

@@ -1,5 +1,4 @@
 // NOTE: Adapted from cortex-m/build.rs
-extern crate riscv_target;
 
 use riscv_target::Target;
 use std::env;
@@ -9,22 +8,24 @@ use std::path::PathBuf;
 fn main() {
     let target = env::var("TARGET").unwrap();
     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
-    let name = env::var("CARGO_PKG_NAME").unwrap();
+    let _name = env::var("CARGO_PKG_NAME").unwrap();
 
+    // set configuration flags depending on the target
     if target.starts_with("riscv") {
-        let mut target = Target::from_target_str(&target);
-        target.retain_extensions("imfdc");
-        let archive: String;
-        if cfg!(feature = "s-mode") {
-            println!("======== compiling riscv-rt for s-mode");
-            archive = format!("bin/{}-smode.a", target.to_string());
-        } else {
-            archive = format!("bin/{}.a", target.to_string());
+        println!("cargo:rustc-cfg=riscv");
+        let target = Target::from_target_str(&target);
+        match target.bits {
+            32 => {
+                println!("cargo:rustc-cfg=riscv32");
+            }
+            64 => {
+                println!("cargo:rustc-cfg=riscv64");
+            }
+            _ => panic!("Unsupported bit width"),
+        }
+        if target.has_extension('m') {
+            println!("cargo:rustc-cfg=riscvm"); // we can expose extensions this way
         }
-
-        fs::copy(&archive, out_dir.join(format!("lib{}.a", name))).unwrap();
-        println!("cargo:rerun-if-changed={}", archive);
-        println!("cargo:rustc-link-lib=static={}", name);
     }
 
     // Put the linker script somewhere the linker can find it

riscv-rt/check-blobs.sh

@@ -1,21 +0,0 @@
-#!/bin/bash
-
-# Checks that the blobs are up to date with the committed assembly files
-
-set -euxo pipefail
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.before
-done
-
-./assemble.sh
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.after
-done
-
-for cksum in $(ls bin/*.after); do
-    diff -u $cksum ${cksum%.after}.before
-done

riscv-rt/examples/device.x

@@ -0,0 +1,14 @@
+MEMORY
+{
+    RAM : ORIGIN = 0x80000000, LENGTH = 16K
+    FLASH : ORIGIN = 0x20000000, LENGTH = 4M
+}
+
+REGION_ALIAS("REGION_TEXT", FLASH);
+REGION_ALIAS("REGION_RODATA", FLASH);
+REGION_ALIAS("REGION_DATA", RAM);
+REGION_ALIAS("REGION_BSS", RAM);
+REGION_ALIAS("REGION_HEAP", RAM);
+REGION_ALIAS("REGION_STACK", RAM);
+
+INCLUDE link.x

riscv-rt/link.x

@@ -57,7 +57,7 @@ SECTIONS
     . = ALIGN(4);
     *(.trap);
     *(.trap.rust);
-
+    *(.text.abort);
     *(.text .text.*);
   } > REGION_TEXT
 

riscv-rt/src/asm.rs

@@ -0,0 +1,186 @@
+use core::arch::global_asm;
+
+/// Parse cfg attributes inside a global_asm call.
+macro_rules! cfg_global_asm {
+    {@inner, [$($x:tt)*], } => {
+        global_asm!{$($x)*}
+    };
+    (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
+        #[cfg($meta)]
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+        #[cfg(not($meta))]
+        cfg_global_asm!{@inner, [$($x)*], $($rest)*}
+    };
+    {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+    };
+    {$($asms:tt)*} => {
+        cfg_global_asm!{@inner, [], $($asms)*}
+    };
+}
+
+// Entry point of all programs (_start). It initializes DWARF call frame information,
+// the stack pointer, the frame pointer (needed for closures to work in start_rust)
+// and the global pointer. Then it calls _start_rust.
+cfg_global_asm!(
+    ".section .init, \"ax\"
+    .global _start
+
+_start:",
+    #[cfg(riscv32)]
+    "lui ra, %hi(_abs_start)
+     jr %lo(_abs_start)(ra)",
+    #[cfg(riscv64)]
+    ".option push
+    .option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
+1:
+    auipc ra, %pcrel_hi(1f)
+    ld ra, %pcrel_lo(1b)(ra)
+    jr ra
+    .align  3
+1:
+    .dword _abs_start
+    .option pop",
+    "
+_abs_start:
+    .option norelax
+    .cfi_startproc
+    .cfi_undefined ra",
+    #[cfg(feature = "s-mode")]
+    "csrw sie, 0
+    csrw sip, 0",
+    #[cfg(not(feature = "s-mode"))]
+    "csrw mie, 0
+    csrw mip, 0",
+    "li  x1, 0
+    li  x2, 0
+    li  x3, 0
+    li  x4, 0
+    li  x5, 0
+    li  x6, 0
+    li  x7, 0
+    li  x8, 0
+    li  x9, 0
+    // a0..a2 (x10..x12) skipped
+    li  x13, 0
+    li  x14, 0
+    li  x15, 0
+    li  x16, 0
+    li  x17, 0
+    li  x18, 0
+    li  x19, 0
+    li  x20, 0
+    li  x21, 0
+    li  x22, 0
+    li  x23, 0
+    li  x24, 0
+    li  x25, 0
+    li  x26, 0
+    li  x27, 0
+    li  x28, 0
+    li  x29, 0
+    li  x30, 0
+    li  x31, 0
+
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop",
+    #[cfg(feature = "s-mode")]
+    "mv t2, a0 // the hartid is passed as parameter by SMODE",
+    #[cfg(not(feature = "s-mode"))]
+    "csrr t2, mhartid",
+    "lui t0, %hi(_max_hart_id)
+    add t0, t0, %lo(_max_hart_id)
+    bgtu t2, t0, abort
+
+    // Allocate stacks
+    la sp, _stack_start
+    lui t0, %hi(_hart_stack_size)
+    add t0, t0, %lo(_hart_stack_size)",
+    #[cfg(riscvm)]
+    "mul t0, t2, t0",
+    #[cfg(not(riscvm))]
+    "beqz t2, 2f  // Jump if single-hart
+    mv t1, t2
+    mv t3, t0
+1:
+    add t0, t0, t3
+    addi t1, t1, -1
+    bnez t1, 1b
+2:  ",
+    "sub sp, sp, t0
+    
+    // Set frame pointer 
+    add s0, sp, zero
+
+    jal zero, _start_rust
+
+    .cfi_endproc",
+);
+
+/// Trap entry point (_start_trap). It saves caller saved registers, calls
+/// _start_trap_rust, restores caller saved registers and then returns.
+/// 
+/// # Usage
+/// 
+/// The macro takes 5 arguments:
+/// - `$STORE`: the instruction used to store a register in the stack (e.g. `sd` for riscv64)
+/// - `$LOAD`: the instruction used to load a register from the stack (e.g. `ld` for riscv64)
+/// - `$BYTES`: the number of bytes used to store a register (e.g. 8 for riscv64)
+/// - `$TRAP_SIZE`: the number of registers to store in the stack (e.g. 32 for all the user registers)
+/// - list of tuples of the form `($REG, $LOCATION)`, where:
+///     - `$REG`: the register to store/load
+///     - `$LOCATION`: the location in the stack where to store/load the register
+#[rustfmt::skip]
+macro_rules! trap_handler {
+    ($STORE:ident, $LOAD:ident, $BYTES:literal, $TRAP_SIZE:literal, [$(($REG:ident, $LOCATION:literal)),*]) => {
+        global_asm!(
+        "
+            .section .trap, \"ax\"
+            .global default_start_trap
+        default_start_trap:",
+            // save space for trap handler in stack
+            concat!("addi sp, sp, -", stringify!($TRAP_SIZE * $BYTES)),
+            // save registers in the desired order
+            $(concat!(stringify!($STORE), " ", stringify!($REG), ", ", stringify!($LOCATION * $BYTES), "(sp)"),)*
+            // call rust trap handler
+            "add a0, sp, zero
+            jal ra, _start_trap_rust",
+            // restore registers in the desired order
+            $(concat!(stringify!($LOAD), " ", stringify!($REG), ", ", stringify!($LOCATION * $BYTES), "(sp)"),)*
+            // free stack
+            concat!("addi sp, sp, ", stringify!($TRAP_SIZE * $BYTES)),
+        );
+        cfg_global_asm!(
+            // return from trap
+            #[cfg(feature = "s-mode")]
+            "sret",
+            #[cfg(not(feature = "s-mode"))]
+            "mret",
+        );
+    };
+}
+
+#[rustfmt::skip]
+#[cfg(riscv32)]
+trap_handler!(
+    sw, lw, 4, 16,
+    [(ra, 0), (t0, 1), (t1, 2), (t2, 3), (t3, 4), (t4, 5), (t5, 6), (t6, 7),
+     (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
+);
+#[rustfmt::skip]
+#[cfg(riscv64)]
+trap_handler!(
+    sd, ld, 8, 16,
+    [(ra, 0), (t0, 1), (t1, 2), (t2, 3), (t3, 4), (t4, 5), (t5, 6), (t6, 7),
+     (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
+);
+
+// Make sure there is an abort when linking
+global_asm!(
+    ".section .text.abort
+     .globl abort
+abort:
+    j abort"
+);

riscv-rt/src/lib.rs

@@ -359,6 +359,9 @@
 #![no_std]
 #![deny(missing_docs)]
 
+#[cfg(riscv)]
+mod asm;
+
 #[cfg(feature = "s-mode")]
 use riscv::register::{scause as xcause, stvec as xtvec, stvec::TrapMode as xTrapMode};