fix cargo fmt

build.rs

@@ -13,12 +13,13 @@ fn main() {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("ic");
 
-        let target = target.to_string();    
+        let target = target.to_string();
 
         fs::copy(
             format!("bin/{}.a", target),
             out_dir.join(format!("lib{}.a", name)),
-        ).unwrap();
+        )
+        .unwrap();
 
         println!("cargo:rustc-link-lib=static={}", name);
         println!("cargo:rustc-link-search={}", out_dir.display());

src/asm.rs

@@ -25,7 +25,6 @@ macro_rules! instruction {
     )
 }
 
-
 instruction!(
     /// `EBREAK` instruction wrapper
     ///
@@ -47,7 +46,6 @@ instruction!(
     /// `SFENCE.VMA` are ordered before all implicit references subsequent to the `SFENCE.VMA`.
     , sfence_vma_all, "sfence.vma", __sfence_vma_all);
 
-
 /// `SFENCE.VMA` instruction wrapper
 ///
 /// Synchronizes updates to in-memory memory-management data structures with current execution.

src/interrupt.rs

@@ -40,14 +40,18 @@ where
     let mstatus = mstatus::read();
 
     // disable interrupts
-    unsafe { disable(); }
+    unsafe {
+        disable();
+    }
 
     let r = f(unsafe { &CriticalSection::new() });
 
     // If the interrupts were active before our `disable` call, then re-enable
     // them. Otherwise, keep them disabled
     if mstatus.mie() {
-        unsafe { enable(); }
+        unsafe {
+            enable();
+        }
     }
 
     r

src/register/fcsr.rs

@@ -107,7 +107,9 @@ clear!(0x003, __clear_fcsr);
 /// Reads the CSR
 #[inline]
 pub fn read() -> FCSR {
-    FCSR { bits: unsafe{ _read() as u32 } }
+    FCSR {
+        bits: unsafe { _read() as u32 },
+    }
 }
 
 /// Writes the CSR

src/register/macros.rs

@@ -63,7 +63,9 @@ macro_rules! read_csr_as {
         /// Reads the CSR
         #[inline]
         pub fn read() -> $register {
-            $register { bits: unsafe{ _read() } }
+            $register {
+                bits: unsafe { _read() },
+            }
         }
     };
 }
@@ -75,7 +77,7 @@ macro_rules! read_csr_as_usize {
         /// Reads the CSR
         #[inline]
         pub fn read() -> usize {
-            unsafe{ _read() }
+            unsafe { _read() }
         }
     };
 }
@@ -87,7 +89,7 @@ macro_rules! read_csr_as_usize_rv32 {
         /// Reads the CSR
         #[inline]
         pub fn read() -> usize {
-            unsafe{ _read() }
+            unsafe { _read() }
         }
     };
 }
@@ -151,7 +153,7 @@ macro_rules! write_csr_as_usize {
         /// Writes the CSR
         #[inline]
         pub fn write(bits: usize) {
-            unsafe{ _write(bits) }
+            unsafe { _write(bits) }
         }
     };
 }
@@ -163,7 +165,7 @@ macro_rules! write_csr_as_usize_rv32 {
         /// Writes the CSR
         #[inline]
         pub fn write(bits: usize) {
-            unsafe{ _write(bits) }
+            unsafe { _write(bits) }
         }
     };
 }
@@ -266,5 +268,5 @@ macro_rules! read_composite_csr {
                 () => $lo as u64,
             }
         }
-    }
+    };
 }

src/register/marchid.rs

@@ -20,7 +20,7 @@ read_csr!(0xF11, __read_marchid);
 /// Reads the CSR
 #[inline]
 pub fn read() -> Option<Marchid> {
-    let r = unsafe{ _read() };
+    let r = unsafe { _read() };
     // When marchid is hardwired to zero it means that the marchid
     // csr isn't implemented.
     NonZeroUsize::new(r).map(|bits| Marchid { bits })

src/register/mcause.rs

@@ -65,7 +65,6 @@ impl Interrupt {
     }
 }
 
-
 impl Exception {
     pub fn from(nr: usize) -> Self {
         match nr {

src/register/mhpmeventx.rs

@@ -7,16 +7,16 @@ macro_rules! reg {
             read_csr_as_usize!($addr, $readf);
             write_csr_as_usize!($addr, $writef);
         }
-    }
+    };
 }
 
-reg!(0x323, mhpmevent3,  __read_mhpmevent3,  __write_mhpmevent3);
-reg!(0x324, mhpmevent4,  __read_mhpmevent4,  __write_mhpmevent4);
-reg!(0x325, mhpmevent5,  __read_mhpmevent5,  __write_mhpmevent5);
-reg!(0x326, mhpmevent6,  __read_mhpmevent6,  __write_mhpmevent6);
-reg!(0x327, mhpmevent7,  __read_mhpmevent7,  __write_mhpmevent7);
-reg!(0x328, mhpmevent8,  __read_mhpmevent8,  __write_mhpmevent8);
-reg!(0x329, mhpmevent9,  __read_mhpmevent9,  __write_mhpmevent9);
+reg!(0x323, mhpmevent3, __read_mhpmevent3, __write_mhpmevent3);
+reg!(0x324, mhpmevent4, __read_mhpmevent4, __write_mhpmevent4);
+reg!(0x325, mhpmevent5, __read_mhpmevent5, __write_mhpmevent5);
+reg!(0x326, mhpmevent6, __read_mhpmevent6, __write_mhpmevent6);
+reg!(0x327, mhpmevent7, __read_mhpmevent7, __write_mhpmevent7);
+reg!(0x328, mhpmevent8, __read_mhpmevent8, __write_mhpmevent8);
+reg!(0x329, mhpmevent9, __read_mhpmevent9, __write_mhpmevent9);
 reg!(0x32A, mhpmevent10, __read_mhpmevent10, __write_mhpmevent10);
 reg!(0x32B, mhpmevent11, __read_mhpmevent11, __write_mhpmevent11);
 reg!(0x32C, mhpmevent12, __read_mhpmevent12, __write_mhpmevent12);

src/register/mimpid.rs

@@ -20,7 +20,7 @@ read_csr!(0xF11, __read_mimpid);
 /// Reads the CSR
 #[inline]
 pub fn read() -> Option<Mimpid> {
-    let r = unsafe{ _read() };
+    let r = unsafe { _read() };
     // When mimpid is hardwired to zero it means that the mimpid
     // csr isn't implemented.
     NonZeroUsize::new(r).map(|bits| Mimpid { bits })

src/register/misa.rs

@@ -53,7 +53,7 @@ read_csr!(0x301, __read_misa);
 /// Reads the CSR
 #[inline]
 pub fn read() -> Option<Misa> {
-    let r = unsafe{ _read() };
+    let r = unsafe { _read() };
     // When misa is hardwired to zero it means that the misa csr
     // isn't implemented.
     NonZeroUsize::new(r).map(|bits| Misa { bits })

src/register/mod.rs

@@ -14,74 +14,67 @@
 mod macros;
 
 // User Trap Setup
-pub mod ustatus;
 pub mod uie;
+pub mod ustatus;
 pub mod utvec;
 
 // User Trap Handling
-pub mod uscratch;
-pub mod uepc;
 pub mod ucause;
-pub mod utval;
+pub mod uepc;
 pub mod uip;
+pub mod uscratch;
+pub mod utval;
 
 // User Floating-Point CSRs
 // TODO: frm, fflags
 pub mod fcsr;
 
-
 // User Counter/Timers
 // TODO: cycle[h], instret[h]
 pub mod time;
+#[rustfmt::skip] // long macro use
 mod hpmcounterx;
 pub use self::hpmcounterx::*;
 pub mod timeh;
 
-
 // Supervisor Trap Setup
 // TODO: sedeleg, sideleg
-pub mod sstatus;
 pub mod sie;
+pub mod sstatus;
 pub mod stvec;
 // TODO: scounteren
 
-
 // Supervisor Trap Handling
-pub mod sscratch;
-pub mod sepc;
 pub mod scause;
-pub mod stval;
+pub mod sepc;
 pub mod sip;
-
+pub mod sscratch;
+pub mod stval;
 
 // Supervisor Protection and Translation
 pub mod satp;
 
-
 // Machine Information Registers
-pub mod mvendorid;
 pub mod marchid;
-pub mod mimpid;
 pub mod mhartid;
-
+pub mod mimpid;
+pub mod mvendorid;
 
 // Machine Trap Setup
-pub mod mstatus;
 pub mod misa;
+pub mod mstatus;
 // TODO: medeleg
 pub mod mideleg;
 pub mod mie;
 pub mod mtvec;
 // TODO: mcounteren
 
-
 // Machine Trap Handling
-pub mod mscratch;
-pub mod mepc;
 pub mod mcause;
-pub mod mtval;
+pub mod mepc;
 pub mod mip;
-
+pub mod mscratch;
+pub mod mtval;
 
 // Machine Protection and Translation
 mod pmpcfgx;
@@ -89,26 +82,22 @@ pub use self::pmpcfgx::*;
 mod pmpaddrx;
 pub use self::pmpaddrx::*;
 
-
 // Machine Counter/Timers
 pub mod mcycle;
-pub mod minstret;
+#[rustfmt::skip] // long macro use
 mod mhpmcounterx;
+pub mod minstret;
 pub use self::mhpmcounterx::*;
 pub mod mcycleh;
 pub mod minstreth;
 
-
 // Machine Counter Setup
 mod mhpmeventx;
 pub use self::mhpmeventx::*;
 
-
 // TODO: Debug/Trace Registers (shared with Debug Mode)
 
-
 // TODO: Debug Mode Registers
 
-
 // Vexriscv custom CSRs
 pub mod vexriscv;

src/register/mstatus.rs

@@ -144,7 +144,6 @@ impl Mstatus {
     }
 }
 
-
 read_csr_as!(Mstatus, 0x300, __read_mstatus);
 write_csr!(0x300, __write_mstatus);
 set!(0x300, __set_mstatus);

src/register/mtvec.rs

@@ -30,7 +30,7 @@ impl Mtvec {
         match mode {
             0 => TrapMode::Direct,
             1 => TrapMode::Vectored,
-            _ => unimplemented!()
+            _ => unimplemented!(),
         }
     }
 }

src/register/mvendorid.rs

@@ -25,7 +25,7 @@ read_csr!(0xF11, __read_mvendorid);
 /// Reads the CSR
 #[inline]
 pub fn read() -> Option<Mvendorid> {
-    let r = unsafe{ _read() };
+    let r = unsafe { _read() };
     // When mvendorid is hardwired to zero it means that the mvendorid
     // csr isn't implemented.
     NonZeroUsize::new(r).map(|bits| Mvendorid { bits })

src/register/pmpaddrx.rs

@@ -7,19 +7,19 @@ macro_rules! reg {
             read_csr_as_usize!($addr, $readf);
             write_csr_as_usize!($addr, $writef);
         }
-    }
+    };
 }
 
-reg!(0x3B0, pmpaddr0,  __read_pmpaddr0,  __write_pmpaddr0);
-reg!(0x3B1, pmpaddr1,  __read_pmpaddr1,  __write_pmpaddr1);
-reg!(0x3B2, pmpaddr2,  __read_pmpaddr2,  __write_pmpaddr2);
-reg!(0x3B3, pmpaddr3,  __read_pmpaddr3,  __write_pmpaddr3);
-reg!(0x3B4, pmpaddr4,  __read_pmpaddr4,  __write_pmpaddr4);
-reg!(0x3B5, pmpaddr5,  __read_pmpaddr5,  __write_pmpaddr5);
-reg!(0x3B6, pmpaddr6,  __read_pmpaddr6,  __write_pmpaddr6);
-reg!(0x3B7, pmpaddr7,  __read_pmpaddr7,  __write_pmpaddr7);
-reg!(0x3B8, pmpaddr8,  __read_pmpaddr8,  __write_pmpaddr8);
-reg!(0x3B9, pmpaddr9,  __read_pmpaddr9,  __write_pmpaddr9);
+reg!(0x3B0, pmpaddr0, __read_pmpaddr0, __write_pmpaddr0);
+reg!(0x3B1, pmpaddr1, __read_pmpaddr1, __write_pmpaddr1);
+reg!(0x3B2, pmpaddr2, __read_pmpaddr2, __write_pmpaddr2);
+reg!(0x3B3, pmpaddr3, __read_pmpaddr3, __write_pmpaddr3);
+reg!(0x3B4, pmpaddr4, __read_pmpaddr4, __write_pmpaddr4);
+reg!(0x3B5, pmpaddr5, __read_pmpaddr5, __write_pmpaddr5);
+reg!(0x3B6, pmpaddr6, __read_pmpaddr6, __write_pmpaddr6);
+reg!(0x3B7, pmpaddr7, __read_pmpaddr7, __write_pmpaddr7);
+reg!(0x3B8, pmpaddr8, __read_pmpaddr8, __write_pmpaddr8);
+reg!(0x3B9, pmpaddr9, __read_pmpaddr9, __write_pmpaddr9);
 reg!(0x3BA, pmpaddr10, __read_pmpaddr10, __write_pmpaddr10);
 reg!(0x3BB, pmpaddr11, __read_pmpaddr11, __write_pmpaddr11);
 reg!(0x3BC, pmpaddr12, __read_pmpaddr12, __write_pmpaddr12);

src/register/sstatus.rs

@@ -1,8 +1,8 @@
 //! sstatus register
 
+pub use super::mstatus::FS;
 use bit_field::BitField;
 use core::mem::size_of;
-pub use super::mstatus::FS;
 
 /// Supervisor Status Register
 #[derive(Clone, Copy, Debug)]

src/register/stvec.rs

@@ -25,7 +25,7 @@ impl Stvec {
         match mode {
             0 => TrapMode::Direct,
             1 => TrapMode::Vectored,
-            _ => unimplemented!()
+            _ => unimplemented!(),
         }
     }
 }

src/register/utvec.rs

@@ -25,7 +25,7 @@ impl Utvec {
         match mode {
             0 => TrapMode::Direct,
             1 => TrapMode::Vectored,
-            _ => unimplemented!()
+            _ => unimplemented!(),
         }
     }
 }