Clippy fix

src/register/mcounteren.rs

@@ -30,7 +30,7 @@ impl Mcounteren {
     /// Supervisor "hpm\[x\]" Enable (bits 3-31)
     #[inline]
     pub fn hpm(&self, index: usize) -> bool {
-        assert!(3 <= index && index < 32);
+        assert!((3..32).contains(&index));
         self.bits.get_bit(index)
     }
 }
@@ -54,12 +54,12 @@ set_clear_csr!(
 
 #[inline]
 pub unsafe fn set_hpm(index: usize) {
-    assert!(3 <= index && index < 32);
+    assert!((3..32).contains(&index));
     _set(1 << index);
 }
 
 #[inline]
 pub unsafe fn clear_hpm(index: usize) {
-    assert!(3 <= index && index < 32);
+    assert!((3..32).contains(&index));
     _clear(1 << index);
 }

src/register/mstatus.rs

@@ -8,7 +8,7 @@
 // which would be the best way we implement this using Rust?
 
 use bit_field::BitField;
-use core::mem::size_of;
+
 
 /// mstatus register
 #[derive(Clone, Copy, Debug)]
@@ -205,7 +205,7 @@ impl Mstatus {
     /// signals the presence of some dirty state
     #[inline]
     pub fn sd(&self) -> bool {
-        self.bits.get_bit(size_of::<usize>() * 8 - 1)
+        self.bits.get_bit(usize::BITS as usize - 1)
     }
 }
 

src/register/pmpcfgx.rs

@@ -72,7 +72,7 @@ impl Pmpcsr {
                 3 => Range::NAPOT,
                 _ => unreachable!(),
             },
-            locked: byte.get_bit(7) as bool,
+            locked: byte.get_bit(7),
         }
     }
 }

src/register/scause.rs

@@ -1,7 +1,7 @@
 //! scause register
 
 use bit_field::BitField;
-use core::mem::size_of;
+
 
 /// scause register
 #[derive(Clone, Copy)]
@@ -90,7 +90,7 @@ impl Scause {
     /// Returns the code field
     #[inline]
     pub fn code(&self) -> usize {
-        let bit = 1 << (size_of::<usize>() * 8 - 1);
+        let bit = 1 << (usize::BITS as usize - 1);
         self.bits & !bit
     }
 
@@ -107,7 +107,7 @@ impl Scause {
     /// Is trap cause an interrupt.
     #[inline]
     pub fn is_interrupt(&self) -> bool {
-        self.bits.get_bit(size_of::<usize>() * 8 - 1)
+        self.bits.get_bit(usize::BITS as usize - 1)
     }
 
     /// Is trap cause an exception.
@@ -139,7 +139,7 @@ pub unsafe fn set(cause: Trap) {
                 Interrupt::UserExternal => 8,
                 Interrupt::SupervisorExternal => 9,
                 Interrupt::Unknown => panic!("unknown interrupt"),
-            } | (1 << (size_of::<usize>() * 8 - 1)))
+            } | (1 << (usize::BITS as usize - 1)))
         } // interrupt bit is 1
         Trap::Exception(e) => match e {
             Exception::InstructionMisaligned => 0,

src/register/scounteren.rs

@@ -30,7 +30,7 @@ impl Scounteren {
     /// User "hpm\[x\]" Enable (bits 3-31)
     #[inline]
     pub fn hpm(&self, index: usize) -> bool {
-        assert!(3 <= index && index < 32);
+        assert!((3..32).contains(&index));
         self.bits.get_bit(index)
     }
 }
@@ -54,12 +54,12 @@ set_clear_csr!(
 
 #[inline]
 pub unsafe fn set_hpm(index: usize) {
-    assert!(3 <= index && index < 32);
+    assert!((3..32).contains(&index));
     _set(1 << index);
 }
 
 #[inline]
 pub unsafe fn clear_hpm(index: usize) {
-    assert!(3 <= index && index < 32);
+    assert!((3..32).contains(&index));
     _clear(1 << index);
 }

src/register/sstatus.rs

@@ -2,7 +2,7 @@
 
 pub use super::mstatus::FS;
 use bit_field::BitField;
-use core::mem::size_of;
+
 
 /// Supervisor Status Register
 #[derive(Clone, Copy, Debug)]
@@ -92,7 +92,7 @@ impl Sstatus {
     /// signals the presence of some dirty state
     #[inline]
     pub fn sd(&self) -> bool {
-        self.bits.get_bit(size_of::<usize>() * 8 - 1)
+        self.bits.get_bit(usize::BITS as usize - 1)
     }
 }