Merge #38

38: Release v0.5.6 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

CHANGELOG.md

@@ -7,6 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.5.6] - 2020-03-14
+
+### Added
+
+- Added vexriscv-specific registers
+
 ## [v0.5.5] - 2020-02-28
 
 ### Added
@@ -21,5 +27,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Fixed MSRV by restricting the upper bound of `bare-metal` version
 
-[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.5...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.6...HEAD
+[v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
 [v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv"
-version = "0.5.5"
+version = "0.5.6"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]