Merge #98

98: Convert default_setup_interrupts into a Rust function r=dkhayes117 a=Disasm

First step towards a fully inline-asm `riscv-rt`.

Co-authored-by: Vadim Kaushan <admin@disasm.info>

riscv-rt/Cargo.toml

@@ -8,6 +8,7 @@ categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISC-V CPU's"
 keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
+edition = "2018"
 
 [dependencies]
 r0 = "1.0.0"

riscv-rt/asm.S

@@ -167,16 +167,8 @@ default_start_trap:
     addi sp, sp, 16*REGBYTES
     mret
 
-.section .text
-.global default_setup_interrupts
-
-default_setup_interrupts:
-    // Set trap handler
-    la t0, _start_trap
-    csrw mtvec, t0
-    ret
-
 /* Make sure there is an abort when linking */
+.section .text.abort
 .globl abort
 abort:
     j abort

riscv-rt/src/lib.rs

@@ -330,13 +330,8 @@
 #![no_std]
 #![deny(missing_docs)]
 
-extern crate r0;
-extern crate riscv;
-extern crate riscv_rt_macros as macros;
-
-pub use macros::{entry, pre_init};
-
 use riscv::register::mcause;
+pub use riscv_rt_macros::{entry, pre_init};
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
 #[doc(hidden)]
@@ -549,3 +544,15 @@ pub extern "Rust" fn default_mp_hook() -> bool {
         },
     }
 }
+
+/// Default implementation of `_setup_interrupts` that sets `mtvec` to a trap handler address.
+#[doc(hidden)]
+#[no_mangle]
+#[rustfmt::skip]
+pub unsafe extern "Rust" fn default_setup_interrupts() {
+    use riscv::register::mtvec::{self, TrapMode};
+    extern "C" {
+        fn _start_trap();
+    }
+    mtvec::write(_start_trap as usize, TrapMode::Direct);
+}