SMODE: rename feature sbi to s-mode

riscv-rt/CHANGELOG.md

@@ -9,12 +9,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
-- Optional cargo feature `sbi` for SBI compatibility, including conditional compilation for machine mode instructions.
+- Optional cargo feature `s-mode` for supervisor mode, including conditional compilation for supervisor/machine mode instructions.
 
 ### Changed
 
 - Remove superfluous parentheses from link.x, which caused linker errors with nightly.
-- Changed `mp_hook` signature, hartid as passed as usize parameter by the caller (required for `sbi` feature).
+- Changed `mp_hook` signature, hartid as passed as usize parameter by the caller (required for `s-mode` feature).
 
 ## [v0.9.0] - 2022-07-01
 

riscv-rt/Cargo.toml

@@ -11,7 +11,7 @@ license = "ISC"
 edition = "2018"
 
 [features]
-sbi = []
+s-mode = []
 
 [dependencies]
 r0 = "1.0.0"

riscv-rt/asm.S

@@ -46,7 +46,7 @@ _abs_start:
     .cfi_startproc
     .cfi_undefined ra
 
-    #ifdef SBI
+    #ifdef SMODE
     csrw sie, 0     // interrupt disable 
     csrw sip, 0     // no pending interrupts
     #else
@@ -90,9 +90,9 @@ _abs_start:
     la gp, __global_pointer$
     .option pop
 
-    #ifdef SBI
+    #ifdef SMODE
     // there is no equivalent of mhartid in supervisor mode.
-    // instead, the hartid is passed as paramter by SBI
+    // instead, the hartid is passed as paramter by SMODE
     mv t2, a0   
     #else 
     csrr t2, mhartid
@@ -176,7 +176,7 @@ default_start_trap:
     LOAD a7, 15*REGBYTES(sp)
 
     addi sp, sp, 16*REGBYTES
-    #ifdef SBI
+    #ifdef SMODE
     sret
     #else
     mret

riscv-rt/assemble.sh

@@ -32,12 +32,12 @@ do
     riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
 
-    #sbi
-    riscv64-unknown-elf-gcc -DSBI -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-sbi.a bin/$crate.o
+    #s-mode
+    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-smode.a bin/$crate.o
 
-    riscv64-unknown-elf-gcc -DSBI -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-sbi.a bin/$crate.o
+    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-smode.a bin/$crate.o
 
 done
 

riscv-rt/build.rs

@@ -15,9 +15,9 @@ fn main() {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("imfdc");
         let archive: String;
-        if cfg!(feature = "sbi") {
-            println!("======== compiling riscv-rt for sbi");
-            archive = format!("bin/{}-sbi.a", target.to_string());
+        if cfg!(feature = "s-mode") {
+            println!("======== compiling riscv-rt for s-mode");
+            archive = format!("bin/{}-smode.a", target.to_string());
         } else {
             archive = format!("bin/{}.a", target.to_string());
         }

riscv-rt/examples/multi_core.rs

@@ -6,13 +6,12 @@ extern crate riscv;
 extern crate riscv_rt;
 
 use riscv::asm::wfi;
-use riscv::register::{mhartid, mie, mip};
+use riscv::register::{mie, mip};
 use riscv_rt::entry;
 
 #[export_name = "_mp_hook"]
 #[rustfmt::skip]
 pub extern "Rust" fn user_mp_hook(hartid: usize) -> bool {
-    let hartid = mhartid::read();
     if hartid == 0 {
         true
     } else {

riscv-rt/src/lib.rs

@@ -22,7 +22,7 @@
 //!
 //! - A `_sheap` symbol at whose address you can locate a heap.
 //!
-//! - Support for a runtime in supervisor mode, bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc)
+//! - Support for a runtime in supervisor mode, that can be bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc)
 //!
 //! ``` text
 //! $ cargo new --bin app && cd $_
@@ -325,23 +325,23 @@
 //!
 //! # Features
 //!
-//! ## `sbi`
+//! ## `s-mode`
 //!
-//! The SBI runtime feature (`sbi`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).
+//! The supervisor mode feature (`s-mode`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).
 //!
 //! For example:
 //! ``` text
 //! [dependencies]
-//! riscv-rt = {features=["sbi"]}
+//! riscv-rt = {features=["s-mode"]}
 //! ```
-//! Using the SBI requires riscv-rt to be run in supervisor mode instead of machine code.
 //! Internally, riscv-rt uses different versions of precompiled static libraries
-//! for (i) machine mode and (ii) sbi. If the `sbi` feature was activated,
-//! the build script selects the sbi library. While most registers/instructions have variants for
+//! for (i) machine mode and (ii) supervisor mode. If the `s-mode` feature was activated,
+//! the build script selects the s-mode library. While most registers/instructions have variants for
 //! both `mcause` and `scause`, the `mhartid` hardware thread register is not available in supervisor
-//! mode. Instead, the hartid is passed as parameter by the calling SBI.
+//! mode. Instead, the hartid is passed as parameter by a bootstrapping firmware (i.e., SBI).
 //!
-//! QEMU supports [OpenSBI](https://github.com/riscv-software-src/opensbi) as default firmware.
+//! Use case: QEMU supports [OpenSBI](https://github.com/riscv-software-src/opensbi) as default firmware.
+//! Using the SBI requires riscv-rt to be run in supervisor mode instead of machine mode.
 //! ``` text
 //! APP_BINARY=$(find target -name app)
 //! sudo qemu-system-riscv64 -m 2G -nographic -machine virt -kernel $APP_BINARY
@@ -401,7 +401,7 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
 
     // sbi passes hartid as first parameter (a0)
     let hartid: usize;
-    if cfg!(feature = "sbi") {
+    if cfg!(feature = "s-mode") {
         hartid = a0;
     } else {
         hartid = mhartid::read();
@@ -461,7 +461,7 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
         let code: usize;
         let is_exception: bool;
 
-        if cfg!(feature = "sbi") {
+        if cfg!(feature = "s-mode") {
             let cause = scause::read();
             is_exception = cause.is_exception();
             code = cause.code();
@@ -601,7 +601,7 @@ pub unsafe extern "Rust" fn default_setup_interrupts() {
         fn _start_trap();
     }
 
-    if cfg!(feature = "sbi") {
+    if cfg!(feature = "s-mode") {
         use riscv::register::stvec::{self, TrapMode};
         stvec::write(_start_trap as usize, TrapMode::Direct);
     } else {