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+# Change Log
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+
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+All notable changes to this project will be documented in this file.
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+
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+The format is based on [Keep a Changelog](http://keepachangelog.com/)
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+and this project adheres to [Semantic Versioning](http://semver.org/).
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+
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+## [Unreleased]
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+
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+### Added
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+
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+- Added `riscv32i-unknown-none-elf` target support
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+- Added user trap setup and handling registers
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+- Added write methods for the `mip` and `satp` registers
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+- Added `mideleg` register
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+- Added Changelog
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+
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+### Changed
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+
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+- Fixed MSRV by restricting the upper bound of `bare-metal` version
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+
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+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.4...HEAD
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Vadim Kaushan