1 year ago · 51066b53b9
--- a/riscv-peripheral/.github/workflows/clippy.yml
+++ b/riscv-peripheral/.github/workflows/clippy.yml
--- a/riscv-peripheral/.github/workflows/rust.yml
+++ b/riscv-peripheral/.github/workflows/rust.yml
--- a/riscv-peripheral/.github/workflows/rustfmt.yml
+++ b/riscv-peripheral/.github/workflows/rustfmt.yml
--- a/riscv-peripheral/.gitignore
+++ b/riscv-peripheral/.gitignore
--- a/riscv-peripheral/Cargo.toml
+++ b/riscv-peripheral/Cargo.toml
@@ -7,11 +7,11 @@ edition = "2021"
 
				 
			
 
				 [dependencies]
			
 
				 embedded-hal = "1.0.0-rc.2"
			
 
				-embedded-hal-async = { version = "1.0.0-rc.1", optional =  true }
			
 
				+# embedded-hal-async = { version = "1.0.0-rc.1", optional =  true }
			
 
				 riscv = { git = "https://github.com/rust-embedded/riscv", branch = "master" }
			
 
				 
			
 
				 [features]
			
 
				-hal-async = ["embedded-hal-async"]
			
 
				+# hal-async = ["embedded-hal-async"]
			
 
				 
			
 
				 [package.metadata.docs.rs]
			
 
				 default-target = "riscv64imac-unknown-none-elf"
			
--- a/riscv-peripheral/README.md
+++ b/riscv-peripheral/README.md
--- a/riscv-peripheral/examples/e310x.rs
+++ b/riscv-peripheral/examples/e310x.rs
--- a/riscv-peripheral/src/aclint.rs
+++ b/riscv-peripheral/src/aclint.rs
--- a/riscv-peripheral/src/aclint/mswi.rs
+++ b/riscv-peripheral/src/aclint/mswi.rs
--- a/riscv-peripheral/src/aclint/mtimer.rs
+++ b/riscv-peripheral/src/aclint/mtimer.rs
--- a/riscv-peripheral/src/aclint/sswi.rs
+++ b/riscv-peripheral/src/aclint/sswi.rs
--- a/riscv-peripheral/src/common.rs
+++ b/riscv-peripheral/src/common.rs
--- a/riscv-peripheral/src/hal.rs
+++ b/riscv-peripheral/src/hal.rs
--- a/riscv-peripheral/src/hal/aclint.rs
+++ b/riscv-peripheral/src/hal/aclint.rs
--- a/riscv-peripheral/src/hal_async.rs
+++ b/riscv-peripheral/src/hal_async.rs
--- a/riscv-peripheral/src/hal_async/aclint.rs
+++ b/riscv-peripheral/src/hal_async/aclint.rs
--- a/riscv-peripheral/src/lib.rs
+++ b/riscv-peripheral/src/lib.rs
@@ -7,8 +7,8 @@ pub use riscv; // re-export riscv crate to allow macros to use it
 
				 
			
 
				 pub mod common; // common definitions for all peripherals
			
 
				 pub mod hal; // trait implementations for embedded-hal
			
 
				-#[cfg(feature = "hal-async")]
			
 
				-pub mod hal_async; // async trait implementations for embedded-hal
			
 
				+             // #[cfg(feature = "hal-async")]
			
 
				+             // pub mod hal_async; // async trait implementations for embedded-hal
			
 
				 pub mod macros; // macros for easing the definition of peripherals in PACs
			
 
				 
			
 
				 pub mod aclint; // ACLINT and CLINT peripherals
			
--- a/riscv-peripheral/src/macros.rs
+++ b/riscv-peripheral/src/macros.rs
--- a/riscv-peripheral/src/plic.rs
+++ b/riscv-peripheral/src/plic.rs
--- a/riscv-peripheral/src/plic/claim.rs
+++ b/riscv-peripheral/src/plic/claim.rs
--- a/riscv-peripheral/src/plic/enables.rs
+++ b/riscv-peripheral/src/plic/enables.rs
--- a/riscv-peripheral/src/plic/pendings.rs
+++ b/riscv-peripheral/src/plic/pendings.rs
--- a/riscv-peripheral/src/plic/priorities.rs
+++ b/riscv-peripheral/src/plic/priorities.rs
--- a/riscv-peripheral/src/plic/threshold.rs
+++ b/riscv-peripheral/src/plic/threshold.rs