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@@ -273,3 +273,10 @@ RW(0x7A3, tdata3) // Third Debug/Trace trigger data register
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RW(0x7B0, dcsr) // Debug control and status register
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RW(0x7B1, dpc) // Debug PC
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RW(0x7B2, dscratch) // Debug scratch register
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+
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+// VexRiscv custom registers
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+RW(0xBC0, vmim) // Machine IRQ Mask
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+RO(0xFC0, vmip) // Machine IRQ Pending
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+RW(0x9C0, vsim) // Supervisor IRQ Mask
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+RO(0xDC0, vsip) // Supervisor IRQ Pending
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+RO(0xCC0, vdci) // DCache Info
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