Release v0.9.0

riscv-rt/CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.9.0] - 2022-07-01
+
 ### Added
 
 - Pass `a0..a2` register values to the `#[entry]` function.
@@ -80,7 +82,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1..HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.9.0..HEAD
+[v0.9.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1...v0.9.0
 [v0.8.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...v0.8.1
 [v0.8.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...v0.8.0
 [v0.7.2]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...v0.7.2

riscv-rt/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.8.1"
+version = "0.9.0"
 rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]