Fix: Add separate linkerscripts for rv32 and rv64

riscv-rt/build.rs

@@ -5,9 +5,17 @@ use std::env;
 use std::fs;
 use std::path::PathBuf;
 
+fn add_linker_script(bytes: &[u8]) {
+    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
+
+    // Put the linker script somewhere the linker can find it
+    fs::write(out_dir.join("link.x"), bytes).unwrap();
+    println!("cargo:rustc-link-search={}", out_dir.display());
+    println!("cargo:rerun-if-changed=link.x");
+}
+
 fn main() {
     let target = env::var("TARGET").unwrap();
-    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
     let _name = env::var("CARGO_PKG_NAME").unwrap();
 
     // set configuration flags depending on the target
@@ -17,9 +25,11 @@ fn main() {
         match target.bits {
             32 => {
                 println!("cargo:rustc-cfg=riscv32");
+                add_linker_script(include_bytes!("link-rv32.x"));
             }
             64 => {
                 println!("cargo:rustc-cfg=riscv64");
+                add_linker_script(include_bytes!("link-rv64.x"));
             }
             _ => panic!("Unsupported bit width"),
         }
@@ -27,9 +37,4 @@ fn main() {
             println!("cargo:rustc-cfg=riscvm"); // we can expose extensions this way
         }
     }
-
-    // Put the linker script somewhere the linker can find it
-    fs::write(out_dir.join("link.x"), include_bytes!("link.x")).unwrap();
-    println!("cargo:rustc-link-search={}", out_dir.display());
-    println!("cargo:rerun-if-changed=link.x");
 }

riscv-rt/link.x → riscv-rt/link-rv32.x

@@ -150,10 +150,6 @@ BUG(riscv-rt): .data is not 4-byte aligned");
 ASSERT(_sidata % 4 == 0, "
 BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
 
-/* Make sure that we can safely perform .data initialization on RV64 */ 
-ASSERT(_sidata % 8 == _sdata % 8, "
-BUG(riscv-rt): .data is not similarly 8-byte aligned to the LMA of .data");
-
 ASSERT(_sbss % 4 == 0 && _ebss % 4 == 0, "
 BUG(riscv-rt): .bss is not 4-byte aligned");
 

riscv-rt/link-rv64.x

@@ -0,0 +1,174 @@
+PROVIDE(_stext = ORIGIN(REGION_TEXT));
+PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
+PROVIDE(_max_hart_id = 0);
+PROVIDE(_hart_stack_size = 2K);
+PROVIDE(_heap_size = 0);
+
+PROVIDE(UserSoft = DefaultHandler);
+PROVIDE(SupervisorSoft = DefaultHandler);
+PROVIDE(MachineSoft = DefaultHandler);
+PROVIDE(UserTimer = DefaultHandler);
+PROVIDE(SupervisorTimer = DefaultHandler);
+PROVIDE(MachineTimer = DefaultHandler);
+PROVIDE(UserExternal = DefaultHandler);
+PROVIDE(SupervisorExternal = DefaultHandler);
+PROVIDE(MachineExternal = DefaultHandler);
+
+PROVIDE(DefaultHandler = DefaultInterruptHandler);
+PROVIDE(ExceptionHandler = DefaultExceptionHandler);
+
+/* # Pre-initialization function */
+/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
+   then the function this points to will be called before the RAM is initialized. */
+PROVIDE(__pre_init = default_pre_init);
+
+/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
+PROVIDE(_setup_interrupts = default_setup_interrupts);
+
+/* # Multi-processing hook function
+   fn _mp_hook() -> bool;
+
+   This function is called from all the harts and must return true only for one hart,
+   which will perform memory initialization. For other harts it must return false
+   and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
+*/
+PROVIDE(_mp_hook = default_mp_hook);
+
+/* # Start trap function override
+  By default uses the riscv crates default trap handler
+  but by providing the `_start_trap` symbol external crates can override.
+*/
+PROVIDE(_start_trap = default_start_trap);
+
+SECTIONS
+{
+  .text.dummy (NOLOAD) :
+  {
+    /* This section is intended to make _stext address work */
+    . = ABSOLUTE(_stext);
+  } > REGION_TEXT
+
+  .text _stext :
+  {
+    /* Put reset handler first in .text section so it ends up as the entry */
+    /* point of the program. */
+    KEEP(*(.init));
+    KEEP(*(.init.rust));
+    . = ALIGN(4);
+    *(.trap);
+    *(.trap.rust);
+    *(.text.abort);
+    *(.text .text.*);
+  } > REGION_TEXT
+
+  .rodata : ALIGN(4)
+  {
+    *(.srodata .srodata.*);
+    *(.rodata .rodata.*);
+
+    /* 4-byte align the end (VMA) of this section.
+       This is required by LLD to ensure the LMA of the following .data
+       section will have the correct alignment. */
+    . = ALIGN(4);
+  } > REGION_RODATA
+
+  .data : ALIGN(8)
+  {
+    _sidata = LOADADDR(.data);
+    _sdata = .;
+    /* Must be called __global_pointer$ for linker relaxations to work. */
+    PROVIDE(__global_pointer$ = . + 0x800);
+    *(.sdata .sdata.* .sdata2 .sdata2.*);
+    *(.data .data.*);
+    . = ALIGN(8);
+    _edata = .;
+  } > REGION_DATA AT > REGION_RODATA
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    _sbss = .;
+    *(.sbss .sbss.* .bss .bss.*);
+    . = ALIGN(8);
+    _ebss = .;
+  } > REGION_BSS
+
+  /* fictitious region that represents the memory available for the heap */
+  .heap (NOLOAD) :
+  {
+    _sheap = .;
+    . += _heap_size;
+    . = ALIGN(4);
+    _eheap = .;
+  } > REGION_HEAP
+
+  /* fictitious region that represents the memory available for the stack */
+  .stack (NOLOAD) :
+  {
+    _estack = .;
+    . = ABSOLUTE(_stack_start);
+    _sstack = .;
+  } > REGION_STACK
+
+  /* fake output .got section */
+  /* Dynamic relocations are unsupported. This section is only used to detect
+     relocatable code in the input files and raise an error if relocatable code
+     is found */
+  .got (INFO) :
+  {
+    KEEP(*(.got .got.*));
+  }
+
+  .eh_frame (INFO) : { KEEP(*(.eh_frame)) }
+  .eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
+}
+
+/* Do not exceed this mark in the error messages above                                    | */
+ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_DATA) % 8 == 0, "
+ERROR(riscv-rt): the start of the REGION_DATA must be 8-byte aligned");
+
+ASSERT(ORIGIN(REGION_HEAP) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_HEAP must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
+
+ASSERT(_stext % 4 == 0, "
+ERROR(riscv-rt): `_stext` must be 4-byte aligned");
+
+ASSERT(_sdata % 8 == 0 && _edata % 8 == 0, "
+BUG(riscv-rt): .data is not 8-byte aligned");
+
+ASSERT(_sidata % 8 == 0, "
+BUG(riscv-rt): the LMA of .data is not 8-byte aligned");
+
+ASSERT(_sbss % 8 == 0 && _ebss % 8 == 0, "
+BUG(riscv-rt): .bss is not 8-byte aligned");
+
+ASSERT(_sheap % 4 == 0, "
+BUG(riscv-rt): start of .heap is not 4-byte aligned");
+
+ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
+ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
+Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
+
+ASSERT(SIZEOF(.stack) > (_max_hart_id + 1) * _hart_stack_size, "
+ERROR(riscv-rt): .stack section is too small for allocating stacks for all the harts.
+Consider changing `_max_hart_id` or `_hart_stack_size`.");
+
+ASSERT(SIZEOF(.got) == 0, "
+.got section detected in the input files. Dynamic relocations are not
+supported. If you are linking to C code compiled using the `gcc` crate
+then modify your build script to compile the C code _without_ the
+-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
+details.");
+
+/* Do not exceed this mark in the error messages above                                    | */

riscv-rt/src/lib.rs

@@ -435,6 +435,7 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
 
             2:
                 li      {a},0
+                li      {input},0
 
                 // Zero out .bss
             	la      {start},_sbss
@@ -449,7 +450,6 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
             3:
                 li      {start},0
                 li      {end},0
-                li      {input},0
             ",
             start = out(reg) _,
             end = out(reg) _,
@@ -465,82 +465,31 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
                 la      {end},_edata
                 la      {input},_sidata
 
-                bgeu    {start},{end},3f
-
-                //    If _sdata and _sidata are not 8-byte aligned, we copy one word before the main loop. This way, in
-                //    the main loop, we are sure `start` and `input` are 8-byte aligned. This is needed to safely
-                //    perform load and store double instructions.
-                //
-                //    NOTE: We assert in the `link.x` file that _sdata and _sidata are similarly 8-byte aligned. This is
-                //          needed for the main loop here.
-                andi    {b},{start},4
-                beqz    {b},0f
-                lw      {a},0({input})
-                addi    {input},{input},4
-                sw      {a},0({start})
-                addi    {start},{start},4
-
-            0: // .data Main Loop Initialization
-                //    b = FLOOR_ALIGN(_edata, 4)
-                andi    {b},{end},4
-                sub     {b},{end},{b}
-
-            	bgeu    {start},{b},2f
+                bgeu    {start},{end},2f
+
             1: // .data Main Loop
             	ld      {a},0({input})
             	addi    {input},{input},8
             	sd      {a},0({start})
             	addi    {start},{start},8
-            	bltu    {start},{b},1b
-            
-            2: // .data end align
-                //    If _edata is not 8-byte aligned, we copy one word after the main loop. This way we are sure we
-                //    copied all the data even if _edata is 4-byte aligned.
-                andi    {b},{end},4
-                beqz    {b},3f
-                lw      {a},0({input})
-                addi    {input},{input},4
-                sw      {a},0({start})
-                addi    {start},{start},4
+            	bltu    {start},{end},1b
             
-            3: // .data zero registers
+            2: // .data zero registers
                 li      {a},0
                 li      {input},0
 
-            4: // zero out .bss start
             	la      {start},_sbss
             	la      {end},_ebss
             
-                bgeu    {start},{end},8f
+                bgeu    {start},{end},4f
 
-                //    If _sbss is not 8-byte aligned, we zero one word before the main loop. This way, in the main
-                //    loop, we are sure `start` is 8-byte aligned. This is needed to safely perform store double
-                //    instruction.
-                andi    {b},{start},4
-                beqz    {b},5f
-            	sw      zero,0({start})
-            	addi    {start},{start},4
-
-            5: // .bss main loop initialization
-                //    b = FLOOR_ALIGN(_ebss, 4)
-                andi    {b},{end},4
-                sub     {b},{end},{b}
-
-            	bgeu    {start},{b},7f
-            6: // .bss main loop
+            3: // .bss main loop
             	sd      zero,0({start})
             	addi    {start},{start},8
-            	bltu    {start},{b},6b
-
-            7: // .bss end align
-                //    If _ebss is not 8-byte aligned, we need to zero more one word after the main loop.
-                andi    {b},{end},4
-                beqz    {b},8f
-            	sw      zero,0({start})
+            	bltu    {start},{end},3b
 
-            8: // .bss zero registers
+            4: // .bss zero registers
                 //    Zero out used registers
-                li      {b},0
                 li      {start},0
                 li      {end},0
         ",
@@ -548,7 +497,6 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
             end = out(reg) _,
             input = out(reg) _,
             a = out(reg) _,
-            b = out(reg) _,
         );
 
         compiler_fence(Ordering::SeqCst);