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@@ -1,9 +1,11 @@
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//! misa register
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+use core::num::NonZeroUsize;
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+
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/// misa register
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#[derive(Clone, Copy, Debug)]
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pub struct Misa {
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- bits: usize,
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+ bits: NonZeroUsize,
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}
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/// Machine XLEN
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@@ -16,16 +18,16 @@ pub enum MXL {
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impl Misa {
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/// Returns the contents of the register as raw bits
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pub fn bits(&self) -> usize {
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- self.bits
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+ self.bits.get()
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}
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/// Returns the machine xlen.
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pub fn mxl(&self) -> MXL {
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let value = match () {
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#[cfg(target_pointer_width = "32")]
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- () => (self.bits >> 30) as u8,
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+ () => (self.bits() >> 30) as u8,
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#[cfg(target_pointer_width = "64")]
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- () => (self.bits >> 62) as u8,
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+ () => (self.bits() >> 62) as u8,
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};
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match value {
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1 => MXL::XLEN32,
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@@ -41,7 +43,7 @@ impl Misa {
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if bit > 25 {
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return false;
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}
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- self.bits & (1 >> bit) == (1 >> bit)
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+ self.bits() & (1 >> bit) == (1 >> bit)
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}
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}
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@@ -57,11 +59,7 @@ pub fn read() -> Option<Misa> {
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}
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// When misa is hardwired to zero it means that the misa csr
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// isn't implemented.
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- if r == 0 {
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- None
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- } else {
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- Some(Misa { bits: r })
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- }
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+ NonZeroUsize::new(r).map(|bits| Misa { bits })
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},
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#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
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() => unimplemented!(),
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