Merge #52

52: Add CSR register `medeleg`; small doc fix r=Disasm a=luojia65

mideleg is at 0x303; medeleg is at 0x302.

Co-authored-by: luojia65 <me@luojia.cc>

src/register/medeleg.rs

@@ -0,0 +1,148 @@
+//! medeleg register
+
+use bit_field::BitField;
+
+/// medeleg register
+#[derive(Clone, Copy, Debug)]
+pub struct Medeleg {
+    bits: usize,
+}
+
+impl Medeleg {
+    /// Returns the contents of the register as raw bits
+    #[inline]
+    pub fn bits(&self) -> usize {
+        self.bits
+    }
+
+    /// Instruction Address Misaligned Delegate
+    #[inline]
+    pub fn instruction_misaligned(&self) -> bool {
+        self.bits.get_bit(0)
+    }
+
+    /// Instruction Access Fault Delegate
+    #[inline]
+    pub fn instruction_fault(&self) -> bool {
+        self.bits.get_bit(1)
+    }
+
+    /// Illegal Instruction Delegate
+    #[inline]
+    pub fn illegal_instruction(&self) -> bool {
+        self.bits.get_bit(2)
+    }
+
+    /// Breakpoint Delegate
+    #[inline]
+    pub fn breakpoint(&self) -> bool {
+        self.bits.get_bit(3)
+    }
+
+    /// Load Address Misaligned Delegate
+    #[inline]
+    pub fn load_misaligned(&self) -> bool {
+        self.bits.get_bit(4)
+    }
+
+    /// Load Access Fault Delegate
+    #[inline]
+    pub fn load_fault(&self) -> bool {
+        self.bits.get_bit(5)
+    }
+
+    /// Store/AMO Address Misaligned Delegate
+    #[inline]
+    pub fn store_misaligned(&self) -> bool {
+        self.bits.get_bit(6)
+    }
+
+    /// Store/AMO Access Fault Delegate
+    #[inline]
+    pub fn store_fault(&self) -> bool {
+        self.bits.get_bit(7)
+    }
+
+    /// Environment Call from U-mode Delegate
+    #[inline]
+    pub fn user_env_call(&self) -> bool {
+        self.bits.get_bit(8)
+    }
+
+    /// Environment Call from S-mode Delegate
+    #[inline]
+    pub fn supervisor_env_call(&self) -> bool {
+        self.bits.get_bit(9)
+    }
+
+    /// Environment Call from M-mode Delegate
+    #[inline]
+    pub fn machine_env_call(&self) -> bool {
+        self.bits.get_bit(11)
+    }
+
+    /// Instruction Page Fault Delegate
+    #[inline]
+    pub fn instruction_page_fault(&self) -> bool {
+        self.bits.get_bit(12)
+    }
+
+    /// Load Page Fault Delegate
+    #[inline]
+    pub fn load_page_fault(&self) -> bool {
+        self.bits.get_bit(13)
+    }
+
+    /// Store/AMO Page Fault Delegate
+    #[inline]
+    pub fn store_page_fault(&self) -> bool {
+        self.bits.get_bit(15)
+    }
+}
+
+read_csr_as!(Medeleg, 0x302, __read_medeleg);
+set!(0x302, __set_medeleg);
+clear!(0x302, __clear_medeleg);
+
+set_clear_csr!(
+    /// Instruction Address Misaligned Delegate
+    , set_instruction_misaligned, clear_instruction_misaligned, 1 << 0);
+set_clear_csr!(
+    /// Instruction Access Fault Delegate
+    , set_instruction_fault, clear_instruction_fault, 1 << 1);
+set_clear_csr!(
+    /// Illegal Instruction Delegate
+    , set_illegal_instruction, clear_illegal_instruction, 1 << 2);
+set_clear_csr!(
+    /// Breakpoint Delegate
+    , set_breakpoint, clear_breakpoint, 1 << 3);
+set_clear_csr!(
+    /// Load Address Misaligned Delegate
+    , set_load_misaligned, clear_load_misaligned, 1 << 4);
+set_clear_csr!(
+    /// Load Access Fault Delegate
+    , set_load_fault, clear_load_fault, 1 << 5);
+set_clear_csr!(
+    /// Store/AMO Address Misaligned Delegate
+    , set_store_misaligned, clear_store_misaligned, 1 << 6);
+set_clear_csr!(
+    /// Store/AMO Access fault
+    , set_store_fault, clear_store_fault, 1 << 7);
+set_clear_csr!(
+    /// Environment Call from U-mode Delegate
+    , set_user_env_call, clear_user_env_call, 1 << 8);
+set_clear_csr!(
+    /// Environment Call from S-mode Delegate
+    , set_supervisor_env_call, clear_supervisor_env_call, 1 << 9);
+set_clear_csr!(
+    /// Environment Call from M-mode Delegate
+    , set_machine_env_call, clear_machine_env_call, 1 << 11);
+set_clear_csr!(
+    /// Instruction Page Fault Delegate
+    , set_instruction_page_fault, clear_instruction_page_fault, 1 << 12);
+set_clear_csr!(
+    /// Load Page Fault Delegate
+    , set_load_page_fault, clear_load_page_fault, 1 << 13);
+set_clear_csr!(
+    /// Store/AMO Page Fault Delegate
+    , set_store_page_fault, clear_store_page_fault, 1 << 15);

src/register/mideleg.rs

@@ -15,62 +15,62 @@ impl Mideleg {
         self.bits
     }
 
-    /// User Software Interrupt Enable
+    /// User Software Interrupt Delegate
     #[inline]
     pub fn usoft(&self) -> bool {
         self.bits.get_bit(0)
     }
 
-    /// Supervisor Software Interrupt Enable
+    /// Supervisor Software Interrupt Delegate
     #[inline]
     pub fn ssoft(&self) -> bool {
         self.bits.get_bit(1)
     }
 
-    /// User Timer Interrupt Enable
+    /// User Timer Interrupt Delegate
     #[inline]
     pub fn utimer(&self) -> bool {
         self.bits.get_bit(4)
     }
 
-    /// Supervisor Timer Interrupt Enable
+    /// Supervisor Timer Interrupt Delegate
     #[inline]
     pub fn stimer(&self) -> bool {
         self.bits.get_bit(5)
     }
 
-    /// User External Interrupt Enable
+    /// User External Interrupt Delegate
     #[inline]
     pub fn uext(&self) -> bool {
         self.bits.get_bit(8)
     }
 
-    /// Supervisor External Interrupt Enable
+    /// Supervisor External Interrupt Delegate
     #[inline]
     pub fn sext(&self) -> bool {
         self.bits.get_bit(9)
     }
 }
 
-read_csr_as!(Mideleg, 0x304, __read_mideleg);
+read_csr_as!(Mideleg, 0x303, __read_mideleg);
 set!(0x303, __set_mideleg);
 clear!(0x303, __clear_mideleg);
 
 set_clear_csr!(
-    /// User Software Interrupt Pending
+    /// User Software Interrupt Delegate
     , set_usoft, clear_usoft, 1 << 0);
 set_clear_csr!(
-    /// Supervisor Software Interrupt Pending
+    /// Supervisor Software Interrupt Delegate
     , set_ssoft, clear_ssoft, 1 << 1);
 set_clear_csr!(
-    /// User Timer Interrupt Pending
+    /// User Timer Interrupt Delegate
     , set_utimer, clear_utimer, 1 << 4);
 set_clear_csr!(
-    /// Supervisor Timer Interrupt Pending
+    /// Supervisor Timer Interrupt Delegate
     , set_stimer, clear_stimer, 1 << 5);
 set_clear_csr!(
-    /// User External Interrupt Pending
+    /// User External Interrupt Delegate
     , set_uext, clear_uext, 1 << 8);
 set_clear_csr!(
-    /// Supervisor External Interrupt Pending
+    /// Supervisor External Interrupt Delegate
     , set_sext, clear_sext, 1 << 9);

src/register/mod.rs

@@ -61,11 +61,11 @@ pub mod mimpid;
 pub mod mvendorid;
 
 // Machine Trap Setup
-pub mod misa;
-pub mod mstatus;
-// TODO: medeleg
+pub mod medeleg;
 pub mod mideleg;
 pub mod mie;
+pub mod misa;
+pub mod mstatus;
 pub mod mtvec;
 // TODO: mcounteren