Remove vexriscv support.

CHANGELOG.md

@@ -12,6 +12,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Updated Minimum Supported Rust Version to 1.31.0
 - Use `llvm_asm!` instead of `asm!`
 
+### Removed
+
+- vexriscv-specific registers were moved to the `vexriscv` crate
+
 ## [v0.5.6] - 2020-03-14
 
 ### Added

asm.S

@@ -273,10 +273,3 @@ RW(0x7A3, tdata3)   // Third Debug/Trace trigger data register
 RW(0x7B0, dcsr)     // Debug control and status register
 RW(0x7B1, dpc)      // Debug PC
 RW(0x7B2, dscratch) // Debug scratch register
-
-// VexRiscv custom registers
-RW(0xBC0, vmim)     // Machine IRQ Mask
-RO(0xFC0, vmip)     // Machine IRQ Pending
-RW(0x9C0, vsim)     // Supervisor IRQ Mask
-RO(0xDC0, vsip)     // Supervisor IRQ Pending
-RO(0xCC0, vdci)     // DCache Info

src/register/mod.rs

@@ -98,6 +98,3 @@ pub use self::mhpmeventx::*;
 // TODO: Debug/Trace Registers (shared with Debug Mode)
 
 // TODO: Debug Mode Registers
-
-// Vexriscv custom CSRs
-pub mod vexriscv;

src/register/vexriscv/dci.rs

@@ -1,10 +0,0 @@
-//! vexriscv dci register -- dcache info
-//!
-//! This register is only available if the core was built with
-//! `DBusCachedPlugin` enabled and `csrInfo` set to `true`.
-//!
-//! See
-//! [DBusCachedPlugin.scala](https://github.com/SpinalHDL/VexRiscv/blob/95237b23ea2d658cb3e0aa77680ca2851ef5d882/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala#L358)
-//! for more information.
-
-read_csr_as_usize!(0xCC0, __read_vdci);

src/register/vexriscv/mim.rs

@@ -1,4 +0,0 @@
-//! vexriscv mim register -- machine irq mask
-
-read_csr_as_usize!(0xBC0, __read_vmim);
-write_csr_as_usize!(0xBC0, __write_vmim);

src/register/vexriscv/mip.rs

@@ -1,3 +0,0 @@
-//! vexriscv mip register -- machine irq pending
-
-read_csr_as_usize!(0xFC0, __read_vmip);

src/register/vexriscv/mod.rs

@@ -1,13 +0,0 @@
-//! VexRiscv CSRs
-//!
-//! [VexRiscv](https://github.com/SpinalHDL/VexRiscv) is a RISC-V softcore
-//! written in Scala.  It is highly configurable, and can be built with features
-//! such as a dcache and an external interrupt controller.
-//!
-//! These features use vendor-specific CSRs, which are available using this
-//! module.
-pub mod dci;
-pub mod mim;
-pub mod mip;
-pub mod sim;
-pub mod sip;

src/register/vexriscv/sim.rs

@@ -1,4 +0,0 @@
-//! vexriscv sim register -- supervisor irq mask
-
-read_csr_as_usize!(0x9C0, __read_vsim);
-write_csr_as_usize!(0x9C0, __write_vsim);

src/register/vexriscv/sip.rs

@@ -1,3 +0,0 @@
-//! vexriscv sip register -- supervisor irq pending
-
-read_csr_as_usize!(0xDC0, __read_vsip);