@@ -1,4 +1,5 @@
//! cycle register
+//!
//! Shadow of mcycle register
//! must have `scounteren::cy` or `mcounteren::cy` bit enabled depending on whether
//! S-mode is implemented or not
//! cycleh register
//! Shadow of mcycleh register (rv32)
//! instret register
//! Shadow of minstret register
//! must have `scounteren::ir` or `mcounteren::ir` bit enabled depending on whether
//! instreth register
//! Shadow of minstreth register (rv32)