`riscv`: add tp register

* `riscv`: add tp register

riscv/src/register.rs

@@ -109,3 +109,6 @@ pub use self::mhpmeventx::*;
 // TODO: Debug/Trace Registers (shared with Debug Mode)
 
 // TODO: Debug Mode Registers
+
+// Others
+pub mod tp;

riscv/src/register/scause.rs

@@ -1,11 +1,19 @@
 //! scause register
 
+use core::fmt::Debug;
+
 /// scause register
 #[derive(Clone, Copy)]
 pub struct Scause {
     bits: usize,
 }
 
+impl Debug for Scause {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("Scause").field("bits", &self.bits).finish()
+    }
+}
+
 /// Trap Cause
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
 pub enum Trap {

riscv/src/register/tp.rs

@@ -0,0 +1,17 @@
+/// Write the value into the tp register
+#[inline(always)]
+pub fn write(bits: usize) {
+    unsafe {
+        core::arch::asm!("mv tp, {0}", in(reg) bits);
+    }
+}
+
+/// Read the value of the tp register
+#[inline(always)]
+pub fn read() -> usize {
+    let r: usize;
+    unsafe {
+        core::arch::asm!("mv {0}, tp", out(reg) r);
+    }
+    r
+}