Run cargo format

riscv-rt/build.rs

@@ -46,18 +46,25 @@ fn parse_target(target: &str, cargo_flags: &str) -> (u32, HashSet<char>) {
     let cargo_flags = cargo_flags
         .split(0x1fu8 as char)
         .filter(|arg| !arg.is_empty());
-     
+
     cargo_flags
-        .filter(|k| k.starts_with("target-feature=")).flat_map(|str| {
+        .filter(|k| k.starts_with("target-feature="))
+        .flat_map(|str| {
             let flags = str.split('=').collect::<Vec<&str>>()[1];
             flags.split(',')
         })
         .for_each(|feature| {
             let chars = feature.chars().collect::<Vec<char>>();
             match chars[0] {
-                '+' => { extensions.insert(chars[1]); }
-                '-' => { extensions.remove(&chars[1]); }
-                _ => { panic!("Unsupported target feature operation"); }
+                '+' => {
+                    extensions.insert(chars[1]);
+                }
+                '-' => {
+                    extensions.remove(&chars[1]);
+                }
+                _ => {
+                    panic!("Unsupported target feature operation");
+                }
             }
         });
 
@@ -73,7 +80,7 @@ fn main() {
     if target.starts_with("riscv") {
         println!("cargo:rustc-cfg=riscv");
 
-        // This is required until target_arch & target_feature risc-v work is 
+        // This is required until target_arch & target_feature risc-v work is
         // stable and in-use (rust 1.75.0)
         let (bits, extensions) = parse_target(&target, &cargo_flags);
 

riscv-rt/macros/src/lib.rs

@@ -9,7 +9,11 @@ extern crate proc_macro2;
 extern crate syn;
 
 use proc_macro2::Span;
-use syn::{parse::{self, Parse}, spanned::Spanned, FnArg, ItemFn, PathArguments, ReturnType, Type, Visibility, LitStr, LitInt};
+use syn::{
+    parse::{self, Parse},
+    spanned::Spanned,
+    FnArg, ItemFn, LitInt, LitStr, PathArguments, ReturnType, Type, Visibility,
+};
 
 use proc_macro::TokenStream;
 
@@ -230,9 +234,9 @@ impl Parse for AsmLoopArgs {
 /// See [the formatting syntax documentation in `std::fmt`](../std/fmt/index.html)
 /// for details.
 ///
-/// Argument 1 is an assembly expression, all "{}" in this assembly expression will be replaced with the 
+/// Argument 1 is an assembly expression, all "{}" in this assembly expression will be replaced with the
 /// current loop index.
-/// 
+///
 /// Argument 2 is the number of loops to do with the provided expression.
 ///
 /// # Examples
@@ -247,10 +251,13 @@ impl Parse for AsmLoopArgs {
 pub fn loop_asm(input: TokenStream) -> TokenStream {
     let args = parse_macro_input!(input as AsmLoopArgs);
 
-    let tokens = (0..args.count).map(|i| {
-        let i = i.to_string();
-        let asm = args.asm_template.replace("{}", &i);
-        format!("core::arch::asm!(\"{}\");", asm)
-    }).collect::<Vec<String>>().join("\n");
+    let tokens = (0..args.count)
+        .map(|i| {
+            let i = i.to_string();
+            let asm = args.asm_template.replace("{}", &i);
+            format!("core::arch::asm!(\"{}\");", asm)
+        })
+        .collect::<Vec<String>>()
+        .join("\n");
     tokens.parse().unwrap()
 }

riscv-rt/src/lib.rs

@@ -525,8 +525,8 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
 
         // Zero out floating point registers
         if cfg!(all(target_arch = "riscv32", riscvd)) {
-            // rv32 targets with double precision floating point can use fmvp.d.x 
-            // to combine 2 32 bit registers to fill the 64 bit floating point 
+            // rv32 targets with double precision floating point can use fmvp.d.x
+            // to combine 2 32 bit registers to fill the 64 bit floating point
             // register
             riscv_rt_macros::loop_asm!("fmvp.d.x f{}, x0, x0", 32);
         } else if cfg!(riscvd) {