Added new functions

src/aclint.rs

@@ -65,45 +65,77 @@ impl<C: Clint> CLINT<C> {
 
     const MTIME_OFFSET: usize = 0xBFF8;
 
+    /// Returns `true` if any CLINT-related interrupt is pending.
+    #[inline]
+    pub fn is_interrupting() -> bool {
+        Self::mswi_is_interrupting() || Self::mtimer_is_interrupting()
+    }
+
+    /// Returns `true` if a machine software interrupt is pending.
+    #[inline]
+    pub fn mswi_is_interrupting() -> bool {
+        mswi::MSWI::is_interrupting()
+    }
+
+    /// Returns `true` if Machine Software Interrupts are enabled.
+    /// This bit must be set for the `MSWI` to trigger machine software interrupts.
+    #[inline]
+    pub fn mswi_is_enabled() -> bool {
+        mswi::MSWI::is_enabled()
+    }
+
     /// Enables machine software interrupts to let the `MSWI` peripheral trigger interrupts.
     ///
     /// # Safety
     ///
     /// Enabling the `MSWI` may break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable_mswi() {
+    pub unsafe fn mswi_enable() {
         mswi::MSWI::enable();
     }
 
     /// Disables machine software interrupts to prevent the `MSWI` peripheral from triggering interrupts.
     #[inline]
-    pub fn disable_mswi() {
+    pub fn mswi_disable() {
         mswi::MSWI::disable();
     }
 
+    /// Returns the `MSWI` peripheral.
+    #[inline]
+    pub const fn mswi() -> mswi::MSWI {
+        // SAFETY: valid base address
+        unsafe { mswi::MSWI::new(C::BASE) }
+    }
+
+    /// Returns `true` if a machine timer interrupt is pending.
+    #[inline]
+    pub fn mtimer_is_interrupting() -> bool {
+        mtimer::MTIMER::is_interrupting()
+    }
+
+    /// Returns `true` if Machine Timer Interrupts are enabled.
+    /// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
+    #[inline]
+    pub fn mtimer_is_enabled() -> bool {
+        mtimer::MTIMER::is_enabled()
+    }
+
     /// Enables machine timer interrupts to let the `MTIMER` peripheral trigger interrupts.
     ///
     /// # Safety
     ///
     /// Enabling the `MTIMER` may break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable_mtimer() {
+    pub unsafe fn mtimer_enable() {
         mtimer::MTIMER::enable();
     }
 
     /// Disables machine timer interrupts to prevent the `MTIMER` peripheral from triggering interrupts.
     #[inline]
-    pub fn disable_mtimer() {
+    pub fn mtimer_disable() {
         mtimer::MTIMER::disable();
     }
 
-    /// Returns the `MSWI` peripheral.
-    #[inline]
-    pub const fn mswi() -> mswi::MSWI {
-        // SAFETY: valid base address
-        unsafe { mswi::MSWI::new(C::BASE) }
-    }
-
     /// Returns the `MTIMER` peripheral.
     #[inline]
     pub const fn mtimer() -> mtimer::MTIMER {

src/aclint/mswi.rs

@@ -25,6 +25,18 @@ impl MSWI {
         }
     }
 
+    /// Returns `true` if a machine software interrupt is pending.
+    #[inline]
+    pub fn is_interrupting() -> bool {
+        riscv::register::mip::read().msoft()
+    }
+
+    /// Returns `true` if Machine Software Interrupts are enabled.
+    #[inline]
+    pub fn is_enabled() -> bool {
+        riscv::register::mie::read().msoft()
+    }
+
     /// Sets the Machine Software Interrupt bit of the `mie` CSR.
     /// This bit must be set for the `MSWI` to trigger machine software interrupts.
     ///

src/aclint/mtimer.rs

@@ -27,6 +27,18 @@ impl MTIMER {
         }
     }
 
+    /// Returns `true` if a machine timer interrupt is pending.
+    #[inline]
+    pub fn is_interrupting() -> bool {
+        riscv::register::mip::read().mtimer()
+    }
+
+    /// Returns `true` if Machine Timer Interrupts are enabled.
+    #[inline]
+    pub fn is_enabled() -> bool {
+        riscv::register::mie::read().mtimer()
+    }
+
     /// Sets the Machine Timer Interrupt bit of the `mie` CSR.
     /// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
     ///
@@ -46,7 +58,7 @@ impl MTIMER {
         unsafe { riscv::register::mie::clear_mtimer() };
     }
 
-    /// Returns the `MTIME` register for the HART which ID is `hart_id`.
+    /// Returns the `MTIMECMP` register for the HART which ID is `hart_id`.
     ///
     /// # Note
     ///

src/aclint/sswi.rs

@@ -25,6 +25,18 @@ impl SSWI {
         }
     }
 
+    /// Returns `true` if a supervisor software interrupt is pending.
+    #[inline]
+    pub fn is_interrupting() -> bool {
+        riscv::register::sip::read().ssoft()
+    }
+
+    /// Returns `true` if Supervisor Software Interrupts are enabled.
+    #[inline]
+    pub fn is_enabled() -> bool {
+        riscv::register::mie::read().ssoft()
+    }
+
     /// Sets the Supervisor Software Interrupt bit of the `mie` CSR.
     /// This bit must be set for the `SSWI` to trigger supervisor software interrupts.
     ///

src/macros.rs

@@ -81,14 +81,14 @@ macro_rules! clint_codegen {
             ///
             /// Enabling the `MSWI` may break mask-based critical sections.
             #[inline]
-            pub unsafe fn enable_mswi() {
-                $crate::aclint::CLINT::<CLINT>::enable_mswi();
+            pub unsafe fn mswi_enable() {
+                $crate::aclint::CLINT::<CLINT>::mswi_enable();
             }
 
             /// Disables the `MSWI` peripheral.
             #[inline]
-            pub fn disable_mswi() {
-                $crate::aclint::CLINT::<CLINT>::disable_mswi();
+            pub fn mswi_disable() {
+                $crate::aclint::CLINT::<CLINT>::mswi_disable();
             }
 
             /// Enables the `MTIMER` peripheral.
@@ -97,14 +97,14 @@ macro_rules! clint_codegen {
             ///
             /// Enabling the `MTIMER` may break mask-based critical sections.
             #[inline]
-            pub unsafe fn enable_mtimer() {
-                $crate::aclint::CLINT::<CLINT>::enable_mtimer();
+            pub unsafe fn mtimer_enable() {
+                $crate::aclint::CLINT::<CLINT>::mtimer_enable();
             }
 
             /// Disables the `MTIMER` peripheral.
             #[inline]
             pub fn disable_mtimer() {
-                $crate::aclint::CLINT::<CLINT>::disable_mtimer();
+                $crate::aclint::CLINT::<CLINT>::mtimer_disable();
             }
 
             /// Returns the `MSWI` peripheral.

src/plic.rs

@@ -127,6 +127,18 @@ impl<P: Plic> PLIC<P> {
 
     const PENDINGS_OFFSET: usize = 0x1000;
 
+    /// Returns `true` if a machine external interrupt is pending.
+    #[inline]
+    pub fn is_interrupting() -> bool {
+        riscv::register::mip::read().mext()
+    }
+
+    /// Returns true if Machine External Interrupts are enabled.
+    #[inline]
+    pub fn is_enabled() -> bool {
+        riscv::register::mie::read().mext()
+    }
+
     /// Sets the Machine External Interrupt bit of the `mie` CSR.
     /// This bit must be set for the PLIC to trigger machine external interrupts.
     ///
@@ -156,16 +168,14 @@ impl<P: Plic> PLIC<P> {
     }
 
     /// Returns the pendings register of the PLIC.
-    /// This register allows to check if an interrupt source is pending.
-    /// This register is shared among all the contexts.
+    /// This register allows to check if a particular interrupt source is pending.
     #[inline]
     pub fn pendings() -> pendings::PENDINGS {
         // SAFETY: valid address
         unsafe { pendings::PENDINGS::new(P::BASE + Self::PENDINGS_OFFSET) }
     }
 
-    /// Returns the context proxy of a given context.
-    /// This proxy provides access to the PLIC registers of the given context.
+    /// Returns a proxy to access to all the PLIC registers of a given context.
     #[inline]
     pub fn ctx<C: ContextNumber>(context: C) -> CTX<P> {
         // SAFETY: valid context number