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@@ -7,13 +7,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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-## [v0.8.1] - 2022-10-06
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+## [v0.9.0] - 2022-10-06
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### Fixed
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- Fix `asm::delay()` to ensure count register is always reloaded
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- Fix reading marchid and mimpid (#107)
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+### Removed
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+- `set_msoft`, `clear_msoft`, `set_mtimer` and `clear_mtimer` removed as part of fixing issue #62
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+
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## [v0.8.0] - 2022-04-20
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### Added
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@@ -92,8 +95,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Fixed MSRV by restricting the upper bound of `bare-metal` version
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-[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.8.1...HEAD
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-[v0.8.1]: https://github.com/rust-embedded/riscv/compare/v0.8.1...v0.8.0
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+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.9.0...HEAD
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+[v0.9.0]: https://github.com/rust-embedded/riscv/compare/v0.8.0...v0.9.0
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[v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.8.0
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[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.0...v0.7.0
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[v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
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