Ready for PR

riscv-rt/.github/workflows/build.yaml

@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, global_asm ]
+    branches: [ master ]
   pull_request:
   merge_group:
 

riscv-rt/CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Use inline assembly instead of pre-compiled blobs
 - Removed bors in favor of GitHub Merge Queue
 
 ## [v0.11.0] - 2023-01-18

riscv-rt/asm/original_asm.S

@@ -1,189 +0,0 @@
-#if __riscv_xlen == 64
-# define STORE    sd
-# define LOAD     ld
-# define LOG_REGBYTES 3
-#else
-# define STORE    sw
-# define LOAD     lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-/*
-    Entry point of all programs (_start).
-
-    It initializes DWARF call frame information, the stack pointer, the
-    frame pointer (needed for closures to work in start_rust) and the global
-    pointer. Then it calls _start_rust.
-*/
-
-.section .init, "ax"
-.global _start
-
-_start:
-    /* Jump to the absolute address defined by the linker script. */
-    // for 32bit
-    .if __riscv_xlen == 32
-    lui ra, %hi(_abs_start)
-    jr %lo(_abs_start)(ra)
-    .endif
-
-    // for 64bit
-    .if __riscv_xlen == 64
-.option push
-.option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
-1:
-    auipc ra, %pcrel_hi(1f)
-    ld ra, %pcrel_lo(1b)(ra)
-    jr ra
-    .align  3
-1:
-    .dword _abs_start
-.option pop
-    .endif
-
-_abs_start:
-    .cfi_startproc
-    .cfi_undefined ra
-
-    #ifdef SMODE
-    csrw sie, 0     // interrupt disable 
-    csrw sip, 0     // no pending interrupts
-    #else
-    csrw mie, 0
-    csrw mip, 0
-    #endif
-    
-
-    li  x1, 0
-    li  x2, 0
-    li  x3, 0
-    li  x4, 0
-    li  x5, 0
-    li  x6, 0
-    li  x7, 0
-    li  x8, 0
-    li  x9, 0
-    // a0..a2 (x10..x12) skipped
-    li  x13,0
-    li  x14,0
-    li  x15,0
-    li  x16,0
-    li  x17,0
-    li  x18,0
-    li  x19,0
-    li  x20,0
-    li  x21,0
-    li  x22,0
-    li  x23,0
-    li  x24,0
-    li  x25,0
-    li  x26,0
-    li  x27,0
-    li  x28,0
-    li  x29,0
-    li  x30,0
-    li  x31,0
-
-    .option push
-    .option norelax
-    la gp, __global_pointer$
-    .option pop
-
-    #ifdef SMODE
-    // there is no equivalent of mhartid in supervisor mode.
-    // instead, the hartid is passed as paramter by SMODE
-    mv t2, a0   
-    #else 
-    csrr t2, mhartid
-    #endif
-    lui t0, %hi(_max_hart_id)
-    add t0, t0, %lo(_max_hart_id)
-    bgtu t2, t0, abort
-
-    // Allocate stacks
-    la sp, _stack_start
-    lui t0, %hi(_hart_stack_size)
-    add t0, t0, %lo(_hart_stack_size)
-#ifdef __riscv_mul
-    mul t0, t2, t0
-#else
-    beqz t2, 2f  // Jump if single-hart
-    mv t1, t2
-    mv t3, t0
-1:
-    add t0, t0, t3
-    addi t1, t1, -1
-    bnez t1, 1b
-2:
-#endif
-    sub sp, sp, t0
-
-    // Set frame pointer
-    add s0, sp, zero
-
-    jal zero, _start_rust
-
-    .cfi_endproc
-
-/*
-    Trap entry point (_start_trap)
-
-    Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
-    restores caller saved registers and then returns.
-*/
-.section .trap, "ax"
-.global default_start_trap
-
-default_start_trap:
-    addi sp, sp, -16*REGBYTES
-
-    STORE ra, 0*REGBYTES(sp)
-    STORE t0, 1*REGBYTES(sp)
-    STORE t1, 2*REGBYTES(sp)
-    STORE t2, 3*REGBYTES(sp)
-    STORE t3, 4*REGBYTES(sp)
-    STORE t4, 5*REGBYTES(sp)
-    STORE t5, 6*REGBYTES(sp)
-    STORE t6, 7*REGBYTES(sp)
-    STORE a0, 8*REGBYTES(sp)
-    STORE a1, 9*REGBYTES(sp)
-    STORE a2, 10*REGBYTES(sp)
-    STORE a3, 11*REGBYTES(sp)
-    STORE a4, 12*REGBYTES(sp)
-    STORE a5, 13*REGBYTES(sp)
-    STORE a6, 14*REGBYTES(sp)
-    STORE a7, 15*REGBYTES(sp)
-
-    add a0, sp, zero
-    jal ra, _start_trap_rust
-
-    LOAD ra, 0*REGBYTES(sp)
-    LOAD t0, 1*REGBYTES(sp)
-    LOAD t1, 2*REGBYTES(sp)
-    LOAD t2, 3*REGBYTES(sp)
-    LOAD t3, 4*REGBYTES(sp)
-    LOAD t4, 5*REGBYTES(sp)
-    LOAD t5, 6*REGBYTES(sp)
-    LOAD t6, 7*REGBYTES(sp)
-    LOAD a0, 8*REGBYTES(sp)
-    LOAD a1, 9*REGBYTES(sp)
-    LOAD a2, 10*REGBYTES(sp)
-    LOAD a3, 11*REGBYTES(sp)
-    LOAD a4, 12*REGBYTES(sp)
-    LOAD a5, 13*REGBYTES(sp)
-    LOAD a6, 14*REGBYTES(sp)
-    LOAD a7, 15*REGBYTES(sp)
-
-    addi sp, sp, 16*REGBYTES
-    #ifdef SMODE
-    sret
-    #else
-    mret
-    #endif
-
-/* Make sure there is an abort when linking */
-.section .text.abort
-.globl abort
-abort:
-    j abort

riscv-rt/asm/riscv32i-unknown-none-elf-m.s

@@ -1,123 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0"
-	.file	"zk0t2u2b1an050m"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	mie, 0
-	csrwi	mip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	csrr	t2, mhartid
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	beqz	t2, .Ltmp0
-	mv	t1, t2
-	mv	t3, t0
-.Ltmp1:
-	add	t0, t0, t3
-	addi	t1, t1, -1
-	bnez	t1, .Ltmp1
-.Ltmp0:
-	sub	sp, sp, t0
-	add	s0, sp, zero
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	mret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort

riscv-rt/asm/riscv32i-unknown-none-elf-s.s

@@ -1,123 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0"
-	.file	"eaqpawb8fun9h0d"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	sie, 0
-	csrwi	sip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	mv	t2, a0
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	beqz	t2, .Ltmp0
-	mv	t1, t2
-	mv	t3, t0
-.Ltmp1:
-	add	t0, t0, t3
-	addi	t1, t1, -1
-	bnez	t1, .Ltmp1
-.Ltmp0:
-	sub	sp, sp, t0
-	add	s0, sp, zero
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	sret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort

riscv-rt/asm/riscv32imac-unknown-none-elf-m.s

@@ -1,116 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
-	.file	"3wdx7lxc78dgym21"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	mie, 0
-	csrwi	mip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	csrr	t2, mhartid
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	mret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort

riscv-rt/asm/riscv32imac-unknown-none-elf-s.s

@@ -1,116 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
-	.file	"2mpkjzuft8hmeuib"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	sie, 0
-	csrwi	sip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	mv	t2, a0
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	sret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort

riscv-rt/asm/riscv64imac-unknown-none-elf-m.s

@@ -1,126 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
-	.file	"1ruuache5c4x1fns"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	.option	push
-
-	.option	norelax
-.Ltmp0:
-	auipc	ra, %pcrel_hi(.Ltmp1)
-	ld	ra, %pcrel_lo(.Ltmp0)(ra)
-	ret
-	.p2align	3
-.Ltmp1:
-	.quad	_abs_start
-	.option	pop
-
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	mie, 0
-	csrwi	mip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	csrr	t2, mhartid
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -128
-	sd	ra, 0(sp)
-	sd	t0, 8(sp)
-	sd	t1, 16(sp)
-	sd	t2, 24(sp)
-	sd	t3, 32(sp)
-	sd	t4, 40(sp)
-	sd	t5, 48(sp)
-	sd	t6, 56(sp)
-	sd	a0, 64(sp)
-	sd	a1, 72(sp)
-	sd	a2, 80(sp)
-	sd	a3, 88(sp)
-	sd	a4, 96(sp)
-	sd	a5, 104(sp)
-	sd	a6, 112(sp)
-	sd	a7, 120(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	ld	ra, 0(sp)
-	ld	t0, 8(sp)
-	ld	t1, 16(sp)
-	ld	t2, 24(sp)
-	ld	t3, 32(sp)
-	ld	t4, 40(sp)
-	ld	t5, 48(sp)
-	ld	t6, 56(sp)
-	ld	a0, 64(sp)
-	ld	a1, 72(sp)
-	ld	a2, 80(sp)
-	ld	a3, 88(sp)
-	ld	a4, 96(sp)
-	ld	a5, 104(sp)
-	ld	a6, 112(sp)
-	ld	a7, 120(sp)
-	addi	sp, sp, 128
-	mret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort

riscv-rt/asm/riscv64imac-unknown-none-elf-s.s

@@ -1,126 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
-	.file	"5194e8m2dkkkh98p"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	.option	push
-
-	.option	norelax
-.Ltmp0:
-	auipc	ra, %pcrel_hi(.Ltmp1)
-	ld	ra, %pcrel_lo(.Ltmp0)(ra)
-	ret
-	.p2align	3
-.Ltmp1:
-	.quad	_abs_start
-	.option	pop
-
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	sie, 0
-	csrwi	sip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	mv	t2, a0
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -128
-	sd	ra, 0(sp)
-	sd	t0, 8(sp)
-	sd	t1, 16(sp)
-	sd	t2, 24(sp)
-	sd	t3, 32(sp)
-	sd	t4, 40(sp)
-	sd	t5, 48(sp)
-	sd	t6, 56(sp)
-	sd	a0, 64(sp)
-	sd	a1, 72(sp)
-	sd	a2, 80(sp)
-	sd	a3, 88(sp)
-	sd	a4, 96(sp)
-	sd	a5, 104(sp)
-	sd	a6, 112(sp)
-	sd	a7, 120(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	ld	ra, 0(sp)
-	ld	t0, 8(sp)
-	ld	t1, 16(sp)
-	ld	t2, 24(sp)
-	ld	t3, 32(sp)
-	ld	t4, 40(sp)
-	ld	t5, 48(sp)
-	ld	t6, 56(sp)
-	ld	a0, 64(sp)
-	ld	a1, 72(sp)
-	ld	a2, 80(sp)
-	ld	a3, 88(sp)
-	ld	a4, 96(sp)
-	ld	a5, 104(sp)
-	ld	a6, 112(sp)
-	ld	a7, 120(sp)
-	addi	sp, sp, 128
-	sret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort