Merge #45

45: Add support for the riscv32i target r=almindor a=Disasm

Ported from [fomu-rt](https://github.com/im-tomu/fomu-rt)

Closes: https://github.com/rust-embedded/riscv-rt/pull/34

Co-authored-by: Vadim Kaushan <admin@disasm.info>

riscv-rt/.travis.yml

@@ -3,23 +3,16 @@ language: rust
 rust:
 - nightly
 - stable
-- 1.31.0 # MSRV
+- 1.38.0 # MSRV
 
 env:
 - TARGET=x86_64-unknown-linux-gnu
+- TARGET=riscv32i-unknown-none-elf
 - TARGET=riscv32imac-unknown-none-elf
 - TARGET=riscv64imac-unknown-none-elf
 
 if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
-matrix:
-  exclude:
-    - rust: stable
-      env: TARGET=riscv64imac-unknown-none-elf
-    - rust: 1.31.0 # MSRV
-      env: TARGET=riscv64imac-unknown-none-elf
-
-
 before_install: set -e
 
 install:
@@ -32,9 +25,6 @@ script:
 after_script: set +e
 
 cache: cargo
-before_cache:
-  # Travis can't cache files that are not readable by "others"
-  - chmod -R a+r $HOME/.cargo
 
 branches:
   only:

riscv-rt/Cargo.toml

@@ -9,13 +9,12 @@ keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 
 [dependencies]
-r0 = "0.2.2"
-riscv = "0.5.3"
+r0 = "1.0.0"
+riscv = "0.5.5"
 riscv-rt-macros = { path = "macros", version = "0.1.6" }
 
 [features]
 inline-asm = ["riscv/inline-asm"]
 
 [dev-dependencies]
-riscv = "0.5.3"
 panic-halt = "0.2.0"

riscv-rt/asm.S

@@ -1,4 +1,13 @@
-#include "asm.h"
+#if __riscv_xlen == 64
+# define STORE    sd
+# define LOAD     ld
+# define LOG_REGBYTES 3
+#else
+# define STORE    sw
+# define LOAD     lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
 
 /*
     Entry point of all programs (_start).
@@ -84,7 +93,18 @@ _abs_start:
     la sp, _stack_start
     lui t0, %hi(_hart_stack_size)
     add t0, t0, %lo(_hart_stack_size)
+#ifdef __riscv_mul
     mul t0, a2, t0
+#else
+    beqz a2, 2f  // Jump if single-hart
+    mv t1, a2
+    mv t2, t0
+1:
+    add t0, t0, t2
+    addi t1, t1, -1
+    bnez t1, 1b
+2:
+#endif
     sub sp, sp, t0
 
     // Set frame pointer

riscv-rt/asm.h

@@ -1,15 +0,0 @@
-#ifndef _RISCV_RT_ASM_H
-#define _RISCV_RT_ASM_H
-
-#if __riscv_xlen == 64
-# define STORE    sd
-# define LOAD     ld
-# define LOG_REGBYTES 3
-#else
-# define STORE    sw
-# define LOAD     lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-#endif

riscv-rt/assemble.ps1

@@ -0,0 +1,17 @@
+# remove existing blobs because otherwise this will append object files to the old blobs
+Remove-Item -Force bin/*.a
+
+$crate = "riscv-rt"
+
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+
+Remove-Item bin/$crate.o

riscv-rt/assemble.sh

@@ -7,12 +7,15 @@ crate=riscv-rt
 # remove existing blobs because otherwise this will append object files to the old blobs
 rm -f bin/*.a
 
-riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
 
-riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
 
 rm bin/$crate.o

riscv-rt/src/lib.rs

@@ -2,10 +2,8 @@
 //!
 //! # Minimum Supported Rust Version (MSRV)
 //!
-//! This crate is guaranteed to compile on stable Rust 1.31 and up. It *might*
+//! This crate is guaranteed to compile on stable Rust 1.38 and up. It *might*
 //! compile with older versions but that may change in any new patch release.
-//! Note that `riscv64imac-unknown-none-elf` and `riscv64gc-unknown-none-elf` targets
-//! are not supported on stable yet.
 //!
 //! # Features
 //!