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@@ -1,88 +1,18 @@
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+[](https://crates.io/crates/riscv)
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+[](https://crates.io/crates/riscv)
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+[](https://travis-ci.org/rust-embedded/riscv)
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+
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# `riscv`
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> Low level access to RISCV processors
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-## Implemented Peripherals
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-- [ ] plic
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-- [ ] clint
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-
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-## Implemented privileged ASM instructions
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-- [x] ecall
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-- [x] ebreak
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-- [x] uret
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-- [x] sret
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-- [x] mret
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-- [x] wfi
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-- [ ] sfence.vma
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-
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-## Implemented CSR's
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-
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-### User mode
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-- [ ] ustatus
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-- [ ] uie
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-- [ ] utvec
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-- [ ] uscratch
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-- [ ] uepc
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-- [ ] ucause
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-- [ ] utval
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-- [ ] uip
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-- [ ] fflags
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-- [ ] frm
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-- [ ] fcsr
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-- [ ] cycle
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-- [ ] time
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-- [ ] instret
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-- [ ] hpmcounter[3-31]
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-- [ ] cycleh
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-- [ ] timeh
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-- [ ] instreth
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-- [ ] hpmcounter[3-31]h
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+This project is developed and maintained by the [RISCV team][team].
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-### Supervisor mode
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-- [ ] sstatus
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-- [ ] sedeleg
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-- [ ] sideleg
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-- [ ] sie
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-- [ ] stvec
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-- [ ] scounteren
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-- [ ] sscratch
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-- [ ] sepc
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-- [ ] scause
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-- [ ] stval
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-- [ ] sip
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-- [ ] satp
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+## [Documentation](https://docs.rs/crate/riscv)
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-### Machine mode
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-- [x] mvendorid
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-- [ ] marchid
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-- [ ] mimpid
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-- [ ] mhartid
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-- [x] mstatus
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-- [x] misa
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-- [ ] medeleg
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-- [ ] mideleg
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-- [x] mie
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-- [x] mtvec
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-- [ ] mcounteren
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-- [ ] mscratch
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-- [x] mepc
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-- [x] mcause
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-- [ ] mtval
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-- [x] mip
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-- [ ] pmpcfg[0-3]
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-- [ ] pmpaddr[0-15]
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-- [x] mcycle
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-- [x] minstret
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-- [ ] mhpmcounter[3-31]
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-- [x] mcycleh
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-- [x] minstreth
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-- [ ] mhpmcounter[3-31]h
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-- [ ] mhpmevent[3-31]
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-- [ ] tselect
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-- [ ] tdata[1-3]
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+## License
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-# License
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-Copyright 2017 David Craven
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+Copyright 2018 [RISCV team][team]
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Permission to use, copy, modify, and/or distribute this software for any purpose
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with or without fee is hereby granted, provided that the above copyright notice
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@@ -95,3 +25,12 @@ INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
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OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
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THIS SOFTWARE.
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+
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+## Code of Conduct
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+
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+Contribution to this crate is organized under the terms of the [Rust Code of
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+Conduct][CoC], the maintainer of this crate, the [RISCV team][team], promises
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+to intervene to uphold that code of conduct.
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+
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+[CoC]: CODE_OF_CONDUCT.md
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+[team]: https://github.com/rust-embedded/wg#the-riscv-team
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David Craven