Merge #99

99: Remove uses of unstable features and always use inline assembly r=Disasm a=taiki-e

Currently, the `inline-asm` feature uses unstable features, but by replacing the uses of asm_const with `concat!`+`stringify`, the uses of unstable features can be removed.

https://github.com/rust-embedded/riscv/blob/cd31989ba11d5d64e1addd8aab98bfb00dd927d5/src/lib.rs#L17-L18

Co-authored-by: Taiki Endo <te316e89@gmail.com>

.github/bors.toml

@@ -3,7 +3,7 @@ delete_merged_branches = true
 required_approvals = 1
 status = [
     "ci-linux (stable)",
-    "ci-linux (1.42.0)",
+    "ci-linux (1.59.0)",
     "build-other (macOS-latest)",
     "build-other (windows-latest)",
     "Rustfmt"

.github/workflows/ci.yaml

@@ -11,8 +11,8 @@ jobs:
     continue-on-error: ${{ matrix.experimental || false }}
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.42.0
-        rust: [nightly, stable, 1.42.0]
+        # All generated code should be running on stable now, MRSV is 1.59.0
+        rust: [nightly, stable, 1.59.0]
 
         include:
           # Nightly is only for reference and allowed to fail
@@ -34,17 +34,10 @@ jobs:
         run: cargo check --target x86_64-unknown-linux-gnu
       - name: Run CI script for riscv32imac-unknown-none-elf under ${{ matrix.rust }}
         run: cargo check --target riscv32imac-unknown-none-elf
-      - name: Run CI script for riscv32imac-unknown-none-elf (inline-asm) under ${{ matrix.rust }}
-        run: |
-          if [ "${{ matrix.rust }}" == "nightly" ]; then
-            cargo check --target riscv32imac-unknown-none-elf --features inline-asm
-          fi
       - name: Run CI script for riscv64imac-unknown-none-elf under ${{ matrix.rust }}
         run: cargo check --target riscv64imac-unknown-none-elf
       - name: Run CI script for riscv64gc-unknown-none-elf under ${{ matrix.rust }}
         run: cargo check --target riscv64gc-unknown-none-elf
-      - name: Check blobs
-        run: ./check-blobs.sh
 
   # On macOS and Windows, we at least make sure that the crate builds and links.
   build-other:
@@ -63,4 +56,4 @@ jobs:
           toolchain: stable
           override: true
       - name: Build crate for host OS
-        run: cargo build
+        run: cargo build

.gitignore

@@ -1,5 +1,2 @@
 Cargo.lock
 target/
-bin/*.after
-bin/*.before
-bin/*.o

CHANGELOG.md

@@ -19,7 +19,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - Use new `asm!` instead of `llvm_asm!`
-- Change `pmpcfgx::read()` macro to `read_csr_as!()` from `read_csr_as_usize!()` 
+- Change `pmpcfgx::read()` macro to `read_csr_as!()` from `read_csr_as_usize!()`
+- Inline assembly is now always used
+- Update Minimum Supported Rust Version to 1.59
+
+### Removed
+
+- Remove `inline-asm` feature which is now always enabled
 
 ## [v0.7.0] - 2020-07-29
 

Cargo.toml

@@ -1,6 +1,7 @@
 [package]
 name = "riscv"
 version = "0.7.0"
+rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]
@@ -19,9 +20,3 @@ targets = [
 bare-metal = "1.0.0"
 bit_field = "0.10.0"
 embedded-hal = "0.2.6"
-
-[build-dependencies]
-riscv-target = "0.1.2"
-
-[features]
-inline-asm = []

README.md

@@ -12,7 +12,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.42.0 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
 compile with older versions but that may change in any new patch release.
 
 ## License

asm.S

@@ -1,289 +0,0 @@
-#include "asm.h"
-
-.section .text.__nop
-.global __nop
-__nop:
-    nop
-    ret
-
-.section .text.__ebreak
-.global __ebreak
-__ebreak:
-    ebreak
-    ret
-
-.section .text.__wfi
-.global __wfi
-__wfi:
-    wfi
-    ret
-
-.section .text.__sfence_vma_all
-.global __sfence_vma_all
-__sfence_vma_all:
-    sfence.vma
-    ret
-
-.section .text.__sfence_vma
-.global __sfence_vma
-__sfence_vma:
-    sfence.vma a0, a1
-    ret
-
-.section .text.__delay
-.global __delay
-__delay:
-    1:
-    addi a0, a0, -1
-    bne a0, zero, 1b
-    ret
-
-// User Trap Setup
-RW(0x000, ustatus)  // User status register
-RW(0x004, uie)      // User interrupt-enable register
-RW(0x005, utvec)    // User trap handler base address
-
-// User Trap Handling
-RW(0x040, uscratch) // Scratch register for user trap handlers
-RW(0x041, uepc)     // User exception program counter
-RW(0x042, ucause)   // User trap cause
-RW(0x043, utval)    // User bad address or instruction
-RW(0x044, uip)      // User interrupt pending
-
-// User Floating-Point CSRs
-RW(0x001, fflags)   // Floating-Point Accrued Exceptions
-RW(0x002, frm)      // Floating-Point Dynamic Rounding Mode
-RW(0x003, fcsr)     // Floating-Point Control and Status Register (frm + fflags)
-
-// User Counter/Timers
-RO(  0xC00, cycle)          // Cycle counter for RDCYCLE instruction
-RO(  0xC01, time)           // Timer for RDTIME instruction
-RO(  0xC02, instret)        // Instructions-retired counter for RDINSTRET instruction
-RO(  0xC03, hpmcounter3)    // Performance-monitoring counter
-RO(  0xC04, hpmcounter4)    // Performance-monitoring counter
-RO(  0xC05, hpmcounter5)    // Performance-monitoring counter
-RO(  0xC06, hpmcounter6)    // Performance-monitoring counter
-RO(  0xC07, hpmcounter7)    // Performance-monitoring counter
-RO(  0xC08, hpmcounter8)    // Performance-monitoring counter
-RO(  0xC09, hpmcounter9)    // Performance-monitoring counter
-RO(  0xC0A, hpmcounter10)   // Performance-monitoring counter
-RO(  0xC0B, hpmcounter11)   // Performance-monitoring counter
-RO(  0xC0C, hpmcounter12)   // Performance-monitoring counter
-RO(  0xC0D, hpmcounter13)   // Performance-monitoring counter
-RO(  0xC0E, hpmcounter14)   // Performance-monitoring counter
-RO(  0xC0F, hpmcounter15)   // Performance-monitoring counter
-RO(  0xC10, hpmcounter16)   // Performance-monitoring counter
-RO(  0xC11, hpmcounter17)   // Performance-monitoring counter
-RO(  0xC12, hpmcounter18)   // Performance-monitoring counter
-RO(  0xC13, hpmcounter19)   // Performance-monitoring counter
-RO(  0xC14, hpmcounter20)   // Performance-monitoring counter
-RO(  0xC15, hpmcounter21)   // Performance-monitoring counter
-RO(  0xC16, hpmcounter22)   // Performance-monitoring counter
-RO(  0xC17, hpmcounter23)   // Performance-monitoring counter
-RO(  0xC18, hpmcounter24)   // Performance-monitoring counter
-RO(  0xC19, hpmcounter25)   // Performance-monitoring counter
-RO(  0xC1A, hpmcounter26)   // Performance-monitoring counter
-RO(  0xC1B, hpmcounter27)   // Performance-monitoring counter
-RO(  0xC1C, hpmcounter28)   // Performance-monitoring counter
-RO(  0xC1D, hpmcounter29)   // Performance-monitoring counter
-RO(  0xC1E, hpmcounter30)   // Performance-monitoring counter
-RO(  0xC1F, hpmcounter31)   // Performance-monitoring counter
-RO32(0xC80, cycleh)         // Upper 32 bits of cycle, RV32I only
-RO32(0xC81, timeh)          // Upper 32 bits of time, RV32I only
-RO32(0xC82, instreth)       // Upper 32 bits of instret, RV32I only
-RO32(0xC83, hpmcounter3h)   // Upper 32 bits of hpmcounter3, RV32I only
-RO32(0xC84, hpmcounter4h)
-RO32(0xC85, hpmcounter5h)
-RO32(0xC86, hpmcounter6h)
-RO32(0xC87, hpmcounter7h)
-RO32(0xC88, hpmcounter8h)
-RO32(0xC89, hpmcounter9h)
-RO32(0xC8A, hpmcounter10h)
-RO32(0xC8B, hpmcounter11h)
-RO32(0xC8C, hpmcounter12h)
-RO32(0xC8D, hpmcounter13h)
-RO32(0xC8E, hpmcounter14h)
-RO32(0xC8F, hpmcounter15h)
-RO32(0xC90, hpmcounter16h)
-RO32(0xC91, hpmcounter17h)
-RO32(0xC92, hpmcounter18h)
-RO32(0xC93, hpmcounter19h)
-RO32(0xC94, hpmcounter20h)
-RO32(0xC95, hpmcounter21h)
-RO32(0xC96, hpmcounter22h)
-RO32(0xC97, hpmcounter23h)
-RO32(0xC98, hpmcounter24h)
-RO32(0xC99, hpmcounter25h)
-RO32(0xC9A, hpmcounter26h)
-RO32(0xC9B, hpmcounter27h)
-RO32(0xC9C, hpmcounter28h)
-RO32(0xC9D, hpmcounter29h)
-RO32(0xC9E, hpmcounter30h)
-RO32(0xC9F, hpmcounter31h)
-
-// Supervisor Trap Setup
-RW(0x100, sstatus)      // Supervisor status register
-RW(0x102, sedeleg)      // Supervisor exception delegation register
-RW(0x103, sideleg)      // Supervisor interrupt delegation register
-RW(0x104, sie)          // Supervisor interrupt-enable register
-RW(0x105, stvec)        // Supervisor trap handler base address
-RW(0x106, scounteren)   // Supervisor counter enable
-
-// Supervisor Trap Handling
-RW(0x140, sscratch)     // Scratch register for supervisor trap handlers
-RW(0x141, sepc)         // Supervisor exception program counter
-RW(0x142, scause)       // Supervisor trap cause
-RW(0x143, stval)        // Supervisor bad address or instruction
-RW(0x144, sip)          // Supervisor interrupt pending
-
-// Supervisor Protection and Translation
-RW(0x180, satp)         // Supervisor address translation and protection
-
-// Machine Information Registers
-RO(0xF11, mvendorid)    // Vendor ID
-RO(0xF12, marchid)      // Architecture ID
-RO(0xF13, mimpid)       // Implementation ID
-RO(0xF14, mhartid)      // Hardware thread ID
-
-// Machine Trap Setup
-RW(0x300, mstatus)      // Machine status register
-RW(0x301, misa)         // ISA and extensions
-RW(0x302, medeleg)      // Machine exception delegation register
-RW(0x303, mideleg)      // Machine interrupt delegation register
-RW(0x304, mie)          // Machine interrupt-enable register
-RW(0x305, mtvec)        // Machine trap handler base address
-RW(0x306, mcounteren)   // Machine counter enable
-
-// Machine Trap Handling
-RW(0x340, mscratch)     // Scratch register for machine trap handlers
-RW(0x341, mepc)         // Machine exception program counter
-RW(0x342, mcause)       // Machine trap cause
-RW(0x343, mtval)        // Machine bad address or instruction
-RW(0x344, mip)          // Machine interrupt pending
-
-// Machine Protection and Translation
-RW(  0x3A0, pmpcfg0)    // Physical memory protection configuration
-RW32(0x3A1, pmpcfg1)    // Physical memory protection configuration, RV32 only
-RW(  0x3A2, pmpcfg2)    // Physical memory protection configuration
-RW32(0x3A3, pmpcfg3)    // Physical memory protection configuration, RV32 only
-RW(  0x3B0, pmpaddr0)   // Physical memory protection address register
-RW(  0x3B1, pmpaddr1)   // Physical memory protection address register
-RW(  0x3B2, pmpaddr2)   // Physical memory protection address register
-RW(  0x3B3, pmpaddr3)   // Physical memory protection address register
-RW(  0x3B4, pmpaddr4)   // Physical memory protection address register
-RW(  0x3B5, pmpaddr5)   // Physical memory protection address register
-RW(  0x3B6, pmpaddr6)   // Physical memory protection address register
-RW(  0x3B7, pmpaddr7)   // Physical memory protection address register
-RW(  0x3B8, pmpaddr8)   // Physical memory protection address register
-RW(  0x3B9, pmpaddr9)   // Physical memory protection address register
-RW(  0x3BA, pmpaddr10)  // Physical memory protection address register
-RW(  0x3BB, pmpaddr11)  // Physical memory protection address register
-RW(  0x3BC, pmpaddr12)  // Physical memory protection address register
-RW(  0x3BD, pmpaddr13)  // Physical memory protection address register
-RW(  0x3BE, pmpaddr14)  // Physical memory protection address register
-RW(  0x3BF, pmpaddr15)  // Physical memory protection address register
-
-// Machine Counter/Timers
-RO(  0xB00, mcycle)          // Machine cycle counter
-RO(  0xB02, minstret)        // Machine instructions-retired counter
-RO(  0xB03, mhpmcounter3)    // Machine performance-monitoring counter
-RO(  0xB04, mhpmcounter4)    // Machine performance-monitoring counter
-RO(  0xB05, mhpmcounter5)    // Machine performance-monitoring counter
-RO(  0xB06, mhpmcounter6)    // Machine performance-monitoring counter
-RO(  0xB07, mhpmcounter7)    // Machine performance-monitoring counter
-RO(  0xB08, mhpmcounter8)    // Machine performance-monitoring counter
-RO(  0xB09, mhpmcounter9)    // Machine performance-monitoring counter
-RO(  0xB0A, mhpmcounter10)   // Machine performance-monitoring counter
-RO(  0xB0B, mhpmcounter11)   // Machine performance-monitoring counter
-RO(  0xB0C, mhpmcounter12)   // Machine performance-monitoring counter
-RO(  0xB0D, mhpmcounter13)   // Machine performance-monitoring counter
-RO(  0xB0E, mhpmcounter14)   // Machine performance-monitoring counter
-RO(  0xB0F, mhpmcounter15)   // Machine performance-monitoring counter
-RO(  0xB10, mhpmcounter16)   // Machine performance-monitoring counter
-RO(  0xB11, mhpmcounter17)   // Machine performance-monitoring counter
-RO(  0xB12, mhpmcounter18)   // Machine performance-monitoring counter
-RO(  0xB13, mhpmcounter19)   // Machine performance-monitoring counter
-RO(  0xB14, mhpmcounter20)   // Machine performance-monitoring counter
-RO(  0xB15, mhpmcounter21)   // Machine performance-monitoring counter
-RO(  0xB16, mhpmcounter22)   // Machine performance-monitoring counter
-RO(  0xB17, mhpmcounter23)   // Machine performance-monitoring counter
-RO(  0xB18, mhpmcounter24)   // Machine performance-monitoring counter
-RO(  0xB19, mhpmcounter25)   // Machine performance-monitoring counter
-RO(  0xB1A, mhpmcounter26)   // Machine performance-monitoring counter
-RO(  0xB1B, mhpmcounter27)   // Machine performance-monitoring counter
-RO(  0xB1C, mhpmcounter28)   // Machine performance-monitoring counter
-RO(  0xB1D, mhpmcounter29)   // Machine performance-monitoring counter
-RO(  0xB1E, mhpmcounter30)   // Machine performance-monitoring counter
-RO(  0xB1F, mhpmcounter31)   // Machine performance-monitoring counter
-RO32(0xB80, mcycleh)         // Upper 32 bits of mcycle, RV32I only
-RO32(0xB82, minstreth)       // Upper 32 bits of minstret, RV32I only
-RO32(0xB83, mhpmcounter3h)   // Upper 32 bits of mhpmcounter3, RV32I only
-RO32(0xB84, mhpmcounter4h)
-RO32(0xB85, mhpmcounter5h)
-RO32(0xB86, mhpmcounter6h)
-RO32(0xB87, mhpmcounter7h)
-RO32(0xB88, mhpmcounter8h)
-RO32(0xB89, mhpmcounter9h)
-RO32(0xB8A, mhpmcounter10h)
-RO32(0xB8B, mhpmcounter11h)
-RO32(0xB8C, mhpmcounter12h)
-RO32(0xB8D, mhpmcounter13h)
-RO32(0xB8E, mhpmcounter14h)
-RO32(0xB8F, mhpmcounter15h)
-RO32(0xB90, mhpmcounter16h)
-RO32(0xB91, mhpmcounter17h)
-RO32(0xB92, mhpmcounter18h)
-RO32(0xB93, mhpmcounter19h)
-RO32(0xB94, mhpmcounter20h)
-RO32(0xB95, mhpmcounter21h)
-RO32(0xB96, mhpmcounter22h)
-RO32(0xB97, mhpmcounter23h)
-RO32(0xB98, mhpmcounter24h)
-RO32(0xB99, mhpmcounter25h)
-RO32(0xB9A, mhpmcounter26h)
-RO32(0xB9B, mhpmcounter27h)
-RO32(0xB9C, mhpmcounter28h)
-RO32(0xB9D, mhpmcounter29h)
-RO32(0xB9E, mhpmcounter30h)
-RO32(0xB9F, mhpmcounter31h)
-
-RW(0x323, mhpmevent3)   // Machine performance-monitoring event selector
-RW(0x324, mhpmevent4)   // Machine performance-monitoring event selector
-RW(0x325, mhpmevent5)   // Machine performance-monitoring event selector
-RW(0x326, mhpmevent6)   // Machine performance-monitoring event selector
-RW(0x327, mhpmevent7)   // Machine performance-monitoring event selector
-RW(0x328, mhpmevent8)   // Machine performance-monitoring event selector
-RW(0x329, mhpmevent9)   // Machine performance-monitoring event selector
-RW(0x32A, mhpmevent10)  // Machine performance-monitoring event selector
-RW(0x32B, mhpmevent11)  // Machine performance-monitoring event selector
-RW(0x32C, mhpmevent12)  // Machine performance-monitoring event selector
-RW(0x32D, mhpmevent13)  // Machine performance-monitoring event selector
-RW(0x32E, mhpmevent14)  // Machine performance-monitoring event selector
-RW(0x32F, mhpmevent15)  // Machine performance-monitoring event selector
-RW(0x330, mhpmevent16)  // Machine performance-monitoring event selector
-RW(0x331, mhpmevent17)  // Machine performance-monitoring event selector
-RW(0x332, mhpmevent18)  // Machine performance-monitoring event selector
-RW(0x333, mhpmevent19)  // Machine performance-monitoring event selector
-RW(0x334, mhpmevent20)  // Machine performance-monitoring event selector
-RW(0x335, mhpmevent21)  // Machine performance-monitoring event selector
-RW(0x336, mhpmevent22)  // Machine performance-monitoring event selector
-RW(0x337, mhpmevent23)  // Machine performance-monitoring event selector
-RW(0x338, mhpmevent24)  // Machine performance-monitoring event selector
-RW(0x339, mhpmevent25)  // Machine performance-monitoring event selector
-RW(0x33A, mhpmevent26)  // Machine performance-monitoring event selector
-RW(0x33B, mhpmevent27)  // Machine performance-monitoring event selector
-RW(0x33C, mhpmevent28)  // Machine performance-monitoring event selector
-RW(0x33D, mhpmevent29)  // Machine performance-monitoring event selector
-RW(0x33E, mhpmevent30)  // Machine performance-monitoring event selector
-RW(0x33F, mhpmevent31)  // Machine performance-monitoring event selector
-
-// Debug/Trace Registers (shared with Debug Mode)
-RW(0x7A0, tselect)  // Debug/Trace trigger register select
-RW(0x7A1, tdata1)   // First Debug/Trace trigger data register
-RW(0x7A2, tdata2)   // Second Debug/Trace trigger data register
-RW(0x7A3, tdata3)   // Third Debug/Trace trigger data register
-
-// Debug Mode Registers
-RW(0x7B0, dcsr)     // Debug control and status register
-RW(0x7B1, dpc)      // Debug PC
-RW(0x7B2, dscratch) // Debug scratch register

asm.h

@@ -1,48 +0,0 @@
-#ifndef __ASM_H
-#define __ASM_H
-
-#define REG_READ(name, offset) \
-.section .text.__read_ ## name; \
-.global __read_ ## name; \
-__read_ ## name: \
-    csrrs a0, offset, x0; \
-    ret
-
-#define REG_WRITE(name, offset) \
-.section .text.__write_ ## name; \
-.global __write_ ## name; \
-__write_ ## name: \
-    csrrw x0, offset, a0; \
-    ret
-
-#define REG_SET(name, offset) \
-.section .text.__set_ ## name; \
-.global __set_ ## name; \
-__set_ ## name: \
-    csrrs x0, offset, a0; \
-    ret
-
-#define REG_CLEAR(name, offset) \
-.section .text.__clear_ ## name; \
-.global __clear_ ## name; \
-__clear_ ## name: \
-    csrrc x0, offset, a0; \
-    ret
-
-
-#define REG_READ_WRITE(name, offset) REG_READ(name, offset); REG_WRITE(name, offset)
-#define REG_SET_CLEAR(name, offset) REG_SET(name, offset); REG_CLEAR(name, offset)
-
-#define RW(offset, name) REG_READ_WRITE(name, offset); REG_SET_CLEAR(name, offset)
-#define RO(offset, name) REG_READ(name, offset)
-
-#if __riscv_xlen == 32
-#define RW32(offset, name) RW(offset, name)
-#define RO32(offset, name) RO(offset, name)
-#else
-#define RW32(offset, name)
-#define RO32(offset, name)
-#endif
-
-#endif /* __ASM_H */
-

assemble.ps1

@@ -1,44 +0,0 @@
-New-Item -Force -Name bin -Type Directory
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-Remove-Item -Force bin/*.a
-
-$crate = "riscv"
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32i.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32ic.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64i asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64i.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64ic asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64ic.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32if asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32if.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32ifc asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32ifc.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64if asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64if.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64ifc asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64ifc.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifd asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32ifd.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifdc asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32ifdc.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifd asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64ifd.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifdc asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64ifdc.a bin/$crate.o
-
-Remove-Item bin/$crate.o

assemble.sh

@@ -1,46 +0,0 @@
-#!/bin/bash
-
-set -euxo pipefail
-
-crate=riscv
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-rm -f bin/*.a
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
-ar crs bin/riscv32i.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32ic asm.S -o bin/$crate.o
-ar crs bin/riscv32ic.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64i asm.S -o bin/$crate.o
-ar crs bin/riscv64i.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64ic asm.S -o bin/$crate.o
-ar crs bin/riscv64ic.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32if asm.S -o bin/$crate.o
-ar crs bin/riscv32if.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32ifc asm.S -o bin/$crate.o
-ar crs bin/riscv32ifc.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64if asm.S -o bin/$crate.o
-ar crs bin/riscv64if.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64ifc asm.S -o bin/$crate.o
-ar crs bin/riscv64ifc.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifd asm.S -o bin/$crate.o
-ar crs bin/riscv32ifd.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifdc asm.S -o bin/$crate.o
-ar crs bin/riscv32ifdc.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifd asm.S -o bin/$crate.o
-ar crs bin/riscv64ifd.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifdc asm.S -o bin/$crate.o
-ar crs bin/riscv64ifdc.a bin/$crate.o
-
-rm bin/$crate.o

build.rs

@@ -1,31 +1,7 @@
-extern crate riscv_target;
-
-use riscv_target::Target;
-use std::path::PathBuf;
-use std::{env, fs};
+use std::env;
 
 fn main() {
     let target = env::var("TARGET").unwrap();
-    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
-    let name = env::var("CARGO_PKG_NAME").unwrap();
-
-    if target.starts_with("riscv") && env::var_os("CARGO_FEATURE_INLINE_ASM").is_none() {
-        let mut target = Target::from_target_str(&target);
-        target.retain_extensions("ifdc");
-
-        let target = target.to_string();
-        // capture riscvNNxxxxx only
-        let target = target.split("-").next().unwrap();
-
-        fs::copy(
-            format!("bin/{}.a", target),
-            out_dir.join(format!("lib{}.a", name)),
-        )
-        .unwrap();
-
-        println!("cargo:rustc-link-lib=static={}", name);
-        println!("cargo:rustc-link-search={}", out_dir.display());
-    }
 
     if target.starts_with("riscv32") {
         println!("cargo:rustc-cfg=riscv");

check-blobs.sh

@@ -1,21 +0,0 @@
-#!/bin/bash
-
-# Checks that the blobs are up to date with the committed assembly files
-
-set -euxo pipefail
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.before
-done
-
-./assemble.sh
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.after
-done
-
-for cksum in $(ls bin/*.after); do
-    diff -u $cksum ${cksum%.after}.before
-done

src/asm.rs

@@ -1,23 +1,14 @@
 //! Assembly instructions
 
 macro_rules! instruction {
-    ($(#[$attr:meta])*, $fnname:ident, $asm:expr, $asm_fn:ident) => (
+    ($(#[$attr:meta])*, $fnname:ident, $asm:expr) => (
         $(#[$attr])*
         #[inline]
         pub unsafe fn $fnname() {
             match () {
-                #[cfg(all(riscv, feature = "inline-asm"))]
+                #[cfg(riscv)]
                 () => core::arch::asm!($asm),
 
-                #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => {
-                    extern "C" {
-                        fn $asm_fn();
-                    }
-
-                    $asm_fn();
-                }
-
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
             }
@@ -29,18 +20,18 @@ instruction!(
     /// `nop` instruction wrapper
     ///
     /// Generates a no-operation.  Useful to prevent delay loops from being optimized away.
-    , nop, "nop", __nop);
+    , nop, "nop");
 instruction!(
     /// `EBREAK` instruction wrapper
     ///
     /// Generates a breakpoint exception.
-    , ebreak, "ebreak", __ebreak);
+    , ebreak, "ebreak");
 instruction!(
     /// `WFI` instruction wrapper
     ///
     /// Provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing.
     /// The WFI instruction is just a hint, and a legal implementation is to implement WFI as a NOP.
-    , wfi, "wfi", __wfi);
+    , wfi, "wfi");
 instruction!(
     /// `SFENCE.VMA` instruction wrapper (all address spaces and page table levels)
     ///
@@ -49,7 +40,7 @@ instruction!(
     /// are ordinarily not ordered with respect to loads and stores in the instruction stream.
     /// Executing an `SFENCE.VMA` instruction guarantees that any stores in the instruction stream prior to the
     /// `SFENCE.VMA` are ordered before all implicit references subsequent to the `SFENCE.VMA`.
-    , sfence_vma_all, "sfence.vma", __sfence_vma_all);
+    , sfence_vma_all, "sfence.vma");
 
 /// `SFENCE.VMA` instruction wrapper
 ///
@@ -62,18 +53,9 @@ instruction!(
 #[allow(unused_variables)]
 pub unsafe fn sfence_vma(asid: usize, addr: usize) {
     match () {
-        #[cfg(all(riscv, feature = "inline-asm"))]
+        #[cfg(riscv)]
         () => core::arch::asm!("sfence.vma {0}, {1}", in(reg) addr, in(reg) asid),
 
-        #[cfg(all(riscv, not(feature = "inline-asm")))]
-        () => {
-            extern "C" {
-                fn __sfence_vma(addr: usize, asid: usize);
-            }
-
-            __sfence_vma(addr, asid);
-        }
-
         #[cfg(not(riscv))]
         () => unimplemented!(),
     }
@@ -92,7 +74,7 @@ pub unsafe fn sfence_vma(asid: usize, addr: usize) {
 #[allow(unused_variables)]
 pub unsafe fn delay(cycles: u32) {
     match () {
-        #[cfg(all(riscv, feature = "inline-asm"))]
+        #[cfg(riscv)]
         () => {
             let real_cyc = 1 + cycles / 2;
             core::arch::asm!(
@@ -103,15 +85,6 @@ pub unsafe fn delay(cycles: u32) {
             )
         }
 
-        #[cfg(all(riscv, not(feature = "inline-asm")))]
-        () => {
-            extern "C" {
-                fn __delay(cycles: u32);
-            }
-
-            __delay(cycles);
-        }
-
         #[cfg(not(riscv))]
         () => unimplemented!(),
     }

src/lib.rs

@@ -2,7 +2,7 @@
 //!
 //! # Minimum Supported Rust Version (MSRV)
 //!
-//! This crate is guaranteed to compile on stable Rust 1.42 and up. It *might*
+//! This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
 //! compile with older versions but that may change in any new patch release.
 //!
 //! # Features
@@ -14,8 +14,6 @@
 //! - Wrappers around assembly instructions like `WFI`.
 
 #![no_std]
-#![cfg_attr(feature = "inline-asm", feature(asm))]
-#![cfg_attr(feature = "inline-asm", feature(asm_const))]
 
 extern crate bare_metal;
 extern crate bit_field;

src/register/cycle.rs

@@ -4,5 +4,5 @@
 //! must have `scounteren::cy` or `mcounteren::cy` bit enabled depending on whether
 //! S-mode is implemented or not
 
-read_csr_as_usize!(0xC00, __read_cycle);
+read_csr_as_usize!(0xC00);
 read_composite_csr!(super::cycleh::read(), read());

src/register/cycleh.rs

@@ -4,4 +4,4 @@
 //! must have `scounteren::cy` or `mcounteren::cy` bit enabled depending on whether
 //! S-mode is implemented or not
 
-read_csr_as_usize_rv32!(0xC80, __read_cycleh);
+read_csr_as_usize_rv32!(0xC80);

src/register/fcsr.rs

@@ -101,9 +101,9 @@ impl FCSR {
     }
 }
 
-read_csr!(0x003, __read_fcsr);
-write_csr!(0x003, __write_fcsr);
-clear!(0x003, __clear_fcsr);
+read_csr!(0x003);
+write_csr!(0x003);
+clear!(0x003);
 
 /// Reads the CSR
 #[inline]

src/register/hpmcounterx.rs

@@ -1,10 +1,10 @@
 macro_rules! reg {
     (
-        $addr:expr, $csrl:ident, $csrh:ident, $readf:ident, $writef:ident
+        $addr:expr, $csrl:ident, $csrh:ident
     ) => {
         /// Performance-monitoring counter
         pub mod $csrl {
-            read_csr_as_usize!($addr, $readf);
+            read_csr_as_usize!($addr);
             read_composite_csr!(super::$csrh::read(), read());
         }
     };
@@ -12,390 +12,71 @@ macro_rules! reg {
 
 macro_rules! regh {
     (
-        $addr:expr, $csrh:ident, $readf:ident, $writef:ident
+        $addr:expr, $csrh:ident
     ) => {
         /// Upper 32 bits of performance-monitoring counter (RV32I only)
         pub mod $csrh {
-            read_csr_as_usize_rv32!($addr, $readf);
+            read_csr_as_usize_rv32!($addr);
         }
     };
 }
 
-reg!(
-    0xC03,
-    hpmcounter3,
-    hpmcounter3h,
-    __read_hpmcounter3,
-    __write_hpmcounter3
-);
-reg!(
-    0xC04,
-    hpmcounter4,
-    hpmcounter4h,
-    __read_hpmcounter4,
-    __write_hpmcounter4
-);
-reg!(
-    0xC05,
-    hpmcounter5,
-    hpmcounter5h,
-    __read_hpmcounter5,
-    __write_hpmcounter5
-);
-reg!(
-    0xC06,
-    hpmcounter6,
-    hpmcounter6h,
-    __read_hpmcounter6,
-    __write_hpmcounter6
-);
-reg!(
-    0xC07,
-    hpmcounter7,
-    hpmcounter7h,
-    __read_hpmcounter7,
-    __write_hpmcounter7
-);
-reg!(
-    0xC08,
-    hpmcounter8,
-    hpmcounter8h,
-    __read_hpmcounter8,
-    __write_hpmcounter8
-);
-reg!(
-    0xC09,
-    hpmcounter9,
-    hpmcounter9h,
-    __read_hpmcounter9,
-    __write_hpmcounter9
-);
-reg!(
-    0xC0A,
-    hpmcounter10,
-    hpmcounter10h,
-    __read_hpmcounter10,
-    __write_hpmcounter10
-);
-reg!(
-    0xC0B,
-    hpmcounter11,
-    hpmcounter11h,
-    __read_hpmcounter11,
-    __write_hpmcounter11
-);
-reg!(
-    0xC0C,
-    hpmcounter12,
-    hpmcounter12h,
-    __read_hpmcounter12,
-    __write_hpmcounter12
-);
-reg!(
-    0xC0D,
-    hpmcounter13,
-    hpmcounter13h,
-    __read_hpmcounter13,
-    __write_hpmcounter13
-);
-reg!(
-    0xC0E,
-    hpmcounter14,
-    hpmcounter14h,
-    __read_hpmcounter14,
-    __write_hpmcounter14
-);
-reg!(
-    0xC0F,
-    hpmcounter15,
-    hpmcounter15h,
-    __read_hpmcounter15,
-    __write_hpmcounter15
-);
-reg!(
-    0xC10,
-    hpmcounter16,
-    hpmcounter16h,
-    __read_hpmcounter16,
-    __write_hpmcounter16
-);
-reg!(
-    0xC11,
-    hpmcounter17,
-    hpmcounter17h,
-    __read_hpmcounter17,
-    __write_hpmcounter17
-);
-reg!(
-    0xC12,
-    hpmcounter18,
-    hpmcounter18h,
-    __read_hpmcounter18,
-    __write_hpmcounter18
-);
-reg!(
-    0xC13,
-    hpmcounter19,
-    hpmcounter19h,
-    __read_hpmcounter19,
-    __write_hpmcounter19
-);
-reg!(
-    0xC14,
-    hpmcounter20,
-    hpmcounter20h,
-    __read_hpmcounter20,
-    __write_hpmcounter20
-);
-reg!(
-    0xC15,
-    hpmcounter21,
-    hpmcounter21h,
-    __read_hpmcounter21,
-    __write_hpmcounter21
-);
-reg!(
-    0xC16,
-    hpmcounter22,
-    hpmcounter22h,
-    __read_hpmcounter22,
-    __write_hpmcounter22
-);
-reg!(
-    0xC17,
-    hpmcounter23,
-    hpmcounter23h,
-    __read_hpmcounter23,
-    __write_hpmcounter23
-);
-reg!(
-    0xC18,
-    hpmcounter24,
-    hpmcounter24h,
-    __read_hpmcounter24,
-    __write_hpmcounter24
-);
-reg!(
-    0xC19,
-    hpmcounter25,
-    hpmcounter25h,
-    __read_hpmcounter25,
-    __write_hpmcounter25
-);
-reg!(
-    0xC1A,
-    hpmcounter26,
-    hpmcounter26h,
-    __read_hpmcounter26,
-    __write_hpmcounter26
-);
-reg!(
-    0xC1B,
-    hpmcounter27,
-    hpmcounter27h,
-    __read_hpmcounter27,
-    __write_hpmcounter27
-);
-reg!(
-    0xC1C,
-    hpmcounter28,
-    hpmcounter28h,
-    __read_hpmcounter28,
-    __write_hpmcounter28
-);
-reg!(
-    0xC1D,
-    hpmcounter29,
-    hpmcounter29h,
-    __read_hpmcounter29,
-    __write_hpmcounter29
-);
-reg!(
-    0xC1E,
-    hpmcounter30,
-    hpmcounter30h,
-    __read_hpmcounter30,
-    __write_hpmcounter30
-);
-reg!(
-    0xC1F,
-    hpmcounter31,
-    hpmcounter31h,
-    __read_hpmcounter31,
-    __write_hpmcounter31
-);
+reg!(0xC03, hpmcounter3, hpmcounter3h);
+reg!(0xC04, hpmcounter4, hpmcounter4h);
+reg!(0xC05, hpmcounter5, hpmcounter5h);
+reg!(0xC06, hpmcounter6, hpmcounter6h);
+reg!(0xC07, hpmcounter7, hpmcounter7h);
+reg!(0xC08, hpmcounter8, hpmcounter8h);
+reg!(0xC09, hpmcounter9, hpmcounter9h);
+reg!(0xC0A, hpmcounter10, hpmcounter10h);
+reg!(0xC0B, hpmcounter11, hpmcounter11h);
+reg!(0xC0C, hpmcounter12, hpmcounter12h);
+reg!(0xC0D, hpmcounter13, hpmcounter13h);
+reg!(0xC0E, hpmcounter14, hpmcounter14h);
+reg!(0xC0F, hpmcounter15, hpmcounter15h);
+reg!(0xC10, hpmcounter16, hpmcounter16h);
+reg!(0xC11, hpmcounter17, hpmcounter17h);
+reg!(0xC12, hpmcounter18, hpmcounter18h);
+reg!(0xC13, hpmcounter19, hpmcounter19h);
+reg!(0xC14, hpmcounter20, hpmcounter20h);
+reg!(0xC15, hpmcounter21, hpmcounter21h);
+reg!(0xC16, hpmcounter22, hpmcounter22h);
+reg!(0xC17, hpmcounter23, hpmcounter23h);
+reg!(0xC18, hpmcounter24, hpmcounter24h);
+reg!(0xC19, hpmcounter25, hpmcounter25h);
+reg!(0xC1A, hpmcounter26, hpmcounter26h);
+reg!(0xC1B, hpmcounter27, hpmcounter27h);
+reg!(0xC1C, hpmcounter28, hpmcounter28h);
+reg!(0xC1D, hpmcounter29, hpmcounter29h);
+reg!(0xC1E, hpmcounter30, hpmcounter30h);
+reg!(0xC1F, hpmcounter31, hpmcounter31h);
 
-regh!(
-    0xC83,
-    hpmcounter3h,
-    __read_hpmcounter3h,
-    __write_hpmcounter3h
-);
-regh!(
-    0xC84,
-    hpmcounter4h,
-    __read_hpmcounter4h,
-    __write_hpmcounter4h
-);
-regh!(
-    0xC85,
-    hpmcounter5h,
-    __read_hpmcounter5h,
-    __write_hpmcounter5h
-);
-regh!(
-    0xC86,
-    hpmcounter6h,
-    __read_hpmcounter6h,
-    __write_hpmcounter6h
-);
-regh!(
-    0xC87,
-    hpmcounter7h,
-    __read_hpmcounter7h,
-    __write_hpmcounter7h
-);
-regh!(
-    0xC88,
-    hpmcounter8h,
-    __read_hpmcounter8h,
-    __write_hpmcounter8h
-);
-regh!(
-    0xC89,
-    hpmcounter9h,
-    __read_hpmcounter9h,
-    __write_hpmcounter9h
-);
-regh!(
-    0xC8A,
-    hpmcounter10h,
-    __read_hpmcounter10h,
-    __write_hpmcounter10h
-);
-regh!(
-    0xC8B,
-    hpmcounter11h,
-    __read_hpmcounter11h,
-    __write_hpmcounter11h
-);
-regh!(
-    0xC8C,
-    hpmcounter12h,
-    __read_hpmcounter12h,
-    __write_hpmcounter12h
-);
-regh!(
-    0xC8D,
-    hpmcounter13h,
-    __read_hpmcounter13h,
-    __write_hpmcounter13h
-);
-regh!(
-    0xC8E,
-    hpmcounter14h,
-    __read_hpmcounter14h,
-    __write_hpmcounter14h
-);
-regh!(
-    0xC8F,
-    hpmcounter15h,
-    __read_hpmcounter15h,
-    __write_hpmcounter15h
-);
-regh!(
-    0xC90,
-    hpmcounter16h,
-    __read_hpmcounter16h,
-    __write_hpmcounter16h
-);
-regh!(
-    0xC91,
-    hpmcounter17h,
-    __read_hpmcounter17h,
-    __write_hpmcounter17h
-);
-regh!(
-    0xC92,
-    hpmcounter18h,
-    __read_hpmcounter18h,
-    __write_hpmcounter18h
-);
-regh!(
-    0xC93,
-    hpmcounter19h,
-    __read_hpmcounter19h,
-    __write_hpmcounter19h
-);
-regh!(
-    0xC94,
-    hpmcounter20h,
-    __read_hpmcounter20h,
-    __write_hpmcounter20h
-);
-regh!(
-    0xC95,
-    hpmcounter21h,
-    __read_hpmcounter21h,
-    __write_hpmcounter21h
-);
-regh!(
-    0xC96,
-    hpmcounter22h,
-    __read_hpmcounter22h,
-    __write_hpmcounter22h
-);
-regh!(
-    0xC97,
-    hpmcounter23h,
-    __read_hpmcounter23h,
-    __write_hpmcounter23h
-);
-regh!(
-    0xC98,
-    hpmcounter24h,
-    __read_hpmcounter24h,
-    __write_hpmcounter24h
-);
-regh!(
-    0xC99,
-    hpmcounter25h,
-    __read_hpmcounter25h,
-    __write_hpmcounter25h
-);
-regh!(
-    0xC9A,
-    hpmcounter26h,
-    __read_hpmcounter26h,
-    __write_hpmcounter26h
-);
-regh!(
-    0xC9B,
-    hpmcounter27h,
-    __read_hpmcounter27h,
-    __write_hpmcounter27h
-);
-regh!(
-    0xC9C,
-    hpmcounter28h,
-    __read_hpmcounter28h,
-    __write_hpmcounter28h
-);
-regh!(
-    0xC9D,
-    hpmcounter29h,
-    __read_hpmcounter29h,
-    __write_hpmcounter29h
-);
-regh!(
-    0xC9E,
-    hpmcounter30h,
-    __read_hpmcounter30h,
-    __write_hpmcounter30h
-);
-regh!(
-    0xC9F,
-    hpmcounter31h,
-    __read_hpmcounter31h,
-    __write_hpmcounter31h
-);
+regh!(0xC83, hpmcounter3h);
+regh!(0xC84, hpmcounter4h);
+regh!(0xC85, hpmcounter5h);
+regh!(0xC86, hpmcounter6h);
+regh!(0xC87, hpmcounter7h);
+regh!(0xC88, hpmcounter8h);
+regh!(0xC89, hpmcounter9h);
+regh!(0xC8A, hpmcounter10h);
+regh!(0xC8B, hpmcounter11h);
+regh!(0xC8C, hpmcounter12h);
+regh!(0xC8D, hpmcounter13h);
+regh!(0xC8E, hpmcounter14h);
+regh!(0xC8F, hpmcounter15h);
+regh!(0xC90, hpmcounter16h);
+regh!(0xC91, hpmcounter17h);
+regh!(0xC92, hpmcounter18h);
+regh!(0xC93, hpmcounter19h);
+regh!(0xC94, hpmcounter20h);
+regh!(0xC95, hpmcounter21h);
+regh!(0xC96, hpmcounter22h);
+regh!(0xC97, hpmcounter23h);
+regh!(0xC98, hpmcounter24h);
+regh!(0xC99, hpmcounter25h);
+regh!(0xC9A, hpmcounter26h);
+regh!(0xC9B, hpmcounter27h);
+regh!(0xC9C, hpmcounter28h);
+regh!(0xC9D, hpmcounter29h);
+regh!(0xC9E, hpmcounter30h);
+regh!(0xC9F, hpmcounter31h);

src/register/instret.rs

@@ -4,5 +4,5 @@
 //! must have `scounteren::ir` or `mcounteren::ir` bit enabled depending on whether
 //! S-mode is implemented or not
 
-read_csr_as_usize!(0xC02, __read_instret);
+read_csr_as_usize!(0xC02);
 read_composite_csr!(super::instreth::read(), read());

src/register/instreth.rs

@@ -4,4 +4,4 @@
 //! must have `scounteren::ir` or `mcounteren::ir` bit enabled depending on whether
 //! S-mode is implemented or not
 
-read_csr_as_usize!(0xC82, __read_instreth);
+read_csr_as_usize!(0xC82);

src/register/macros.rs

@@ -1,25 +1,16 @@
 macro_rules! read_csr {
-    ($csr_number:expr, $asm_fn: ident) => {
+    ($csr_number:literal) => {
         /// Reads the CSR
         #[inline]
         unsafe fn _read() -> usize {
             match () {
-                #[cfg(all(riscv, feature = "inline-asm"))]
+                #[cfg(riscv)]
                 () => {
                     let r: usize;
-                    core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
+                    core::arch::asm!(concat!("csrrs {0}, ", stringify!($csr_number), ", x0"), out(reg) r);
                     r
                 }
 
-                #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => {
-                    extern "C" {
-                        fn $asm_fn() -> usize;
-                    }
-
-                    $asm_fn()
-                }
-
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
             }
@@ -28,27 +19,18 @@ macro_rules! read_csr {
 }
 
 macro_rules! read_csr_rv32 {
-    ($csr_number:expr, $asm_fn: ident) => {
+    ($csr_number:literal) => {
         /// Reads the CSR
         #[inline]
         unsafe fn _read() -> usize {
             match () {
-                #[cfg(all(riscv32, feature = "inline-asm"))]
+                #[cfg(riscv32)]
                 () => {
                     let r: usize;
-                    core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
+                    core::arch::asm!(concat!("csrrs {0}, ", stringify!($csr_number), ", x0"), out(reg) r);
                     r
                 }
 
-                #[cfg(all(riscv32, not(feature = "inline-asm")))]
-                () => {
-                    extern "C" {
-                        fn $asm_fn() -> usize;
-                    }
-
-                    $asm_fn()
-                }
-
                 #[cfg(not(riscv32))]
                 () => unimplemented!(),
             }
@@ -57,8 +39,8 @@ macro_rules! read_csr_rv32 {
 }
 
 macro_rules! read_csr_as {
-    ($register:ident, $csr_number:expr, $asm_fn: ident) => {
-        read_csr!($csr_number, $asm_fn);
+    ($register:ident, $csr_number:literal) => {
+        read_csr!($csr_number);
 
         /// Reads the CSR
         #[inline]
@@ -71,8 +53,8 @@ macro_rules! read_csr_as {
 }
 
 macro_rules! read_csr_as_usize {
-    ($csr_number:expr, $asm_fn: ident) => {
-        read_csr!($csr_number, $asm_fn);
+    ($csr_number:literal) => {
+        read_csr!($csr_number);
 
         /// Reads the CSR
         #[inline]
@@ -83,8 +65,8 @@ macro_rules! read_csr_as_usize {
 }
 
 macro_rules! read_csr_as_usize_rv32 {
-    ($csr_number:expr, $asm_fn: ident) => {
-        read_csr_rv32!($csr_number, $asm_fn);
+    ($csr_number:literal) => {
+        read_csr_rv32!($csr_number);
 
         /// Reads the CSR
         #[inline]
@@ -95,23 +77,14 @@ macro_rules! read_csr_as_usize_rv32 {
 }
 
 macro_rules! write_csr {
-    ($csr_number:expr, $asm_fn: ident) => {
+    ($csr_number:literal) => {
         /// Writes the CSR
         #[inline]
         #[allow(unused_variables)]
         unsafe fn _write(bits: usize) {
             match () {
-                #[cfg(all(riscv, feature = "inline-asm"))]
-                () => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
-
-                #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => {
-                    extern "C" {
-                        fn $asm_fn(bits: usize);
-                    }
-
-                    $asm_fn(bits);
-                }
+                #[cfg(riscv)]
+                () => core::arch::asm!(concat!("csrrw x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
@@ -121,23 +94,14 @@ macro_rules! write_csr {
 }
 
 macro_rules! write_csr_rv32 {
-    ($csr_number:expr, $asm_fn: ident) => {
+    ($csr_number:literal) => {
         /// Writes the CSR
         #[inline]
         #[allow(unused_variables)]
         unsafe fn _write(bits: usize) {
             match () {
-                #[cfg(all(riscv32, feature = "inline-asm"))]
-                () => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
-
-                #[cfg(all(riscv32, not(feature = "inline-asm")))]
-                () => {
-                    extern "C" {
-                        fn $asm_fn(bits: usize);
-                    }
-
-                    $asm_fn(bits);
-                }
+                #[cfg(riscv32)]
+                () => core::arch::asm!(concat!("csrrw x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
                 #[cfg(not(riscv32))]
                 () => unimplemented!(),
@@ -147,8 +111,8 @@ macro_rules! write_csr_rv32 {
 }
 
 macro_rules! write_csr_as_usize {
-    ($csr_number:expr, $asm_fn: ident) => {
-        write_csr!($csr_number, $asm_fn);
+    ($csr_number:literal) => {
+        write_csr!($csr_number);
 
         /// Writes the CSR
         #[inline]
@@ -159,8 +123,8 @@ macro_rules! write_csr_as_usize {
 }
 
 macro_rules! write_csr_as_usize_rv32 {
-    ($csr_number:expr, $asm_fn: ident) => {
-        write_csr_rv32!($csr_number, $asm_fn);
+    ($csr_number:literal) => {
+        write_csr_rv32!($csr_number);
 
         /// Writes the CSR
         #[inline]
@@ -171,23 +135,14 @@ macro_rules! write_csr_as_usize_rv32 {
 }
 
 macro_rules! set {
-    ($csr_number:expr, $asm_fn: ident) => {
+    ($csr_number:literal) => {
         /// Set the CSR
         #[inline]
         #[allow(unused_variables)]
         unsafe fn _set(bits: usize) {
             match () {
-                #[cfg(all(riscv, feature = "inline-asm"))]
-                () => core::arch::asm!("csrrs x0, {1}, {0}", in(reg) bits, const $csr_number),
-
-                #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => {
-                    extern "C" {
-                        fn $asm_fn(bits: usize);
-                    }
-
-                    $asm_fn(bits);
-                }
+                #[cfg(riscv)]
+                () => core::arch::asm!(concat!("csrrs x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),
@@ -197,23 +152,14 @@ macro_rules! set {
 }
 
 macro_rules! clear {
-    ($csr_number:expr, $asm_fn: ident) => {
+    ($csr_number:literal) => {
         /// Clear the CSR
         #[inline]
         #[allow(unused_variables)]
         unsafe fn _clear(bits: usize) {
             match () {
-                #[cfg(all(riscv, feature = "inline-asm"))]
-                () => core::arch::asm!("csrrc x0, {1}, {0}", in(reg) bits, const $csr_number),
-
-                #[cfg(all(riscv, not(feature = "inline-asm")))]
-                () => {
-                    extern "C" {
-                        fn $asm_fn(bits: usize);
-                    }
-
-                    $asm_fn(bits);
-                }
+                #[cfg(riscv)]
+                () => core::arch::asm!(concat!("csrrc x0, ", stringify!($csr_number), ", {0}"), in(reg) bits),
 
                 #[cfg(not(riscv))]
                 () => unimplemented!(),

src/register/marchid.rs

@@ -16,7 +16,7 @@ impl Marchid {
     }
 }
 
-read_csr!(0xF11, __read_marchid);
+read_csr!(0xF11);
 
 /// Reads the CSR
 #[inline]

src/register/mcause.rs

@@ -138,4 +138,4 @@ impl Mcause {
     }
 }
 
-read_csr_as!(Mcause, 0x342, __read_mcause);
+read_csr_as!(Mcause, 0x342);

src/register/mcounteren.rs

@@ -35,10 +35,10 @@ impl Mcounteren {
     }
 }
 
-read_csr_as!(Mcounteren, 0x306, __read_mcounteren);
-write_csr!(0x306, __write_mcounteren);
-set!(0x306, __set_mcounteren);
-clear!(0x306, __clear_mcounteren);
+read_csr_as!(Mcounteren, 0x306);
+write_csr!(0x306);
+set!(0x306);
+clear!(0x306);
 
 set_clear_csr!(
 /// Supervisor cycle Enable

src/register/mcycle.rs

@@ -1,4 +1,4 @@
 //! mcycle register
 
-read_csr_as_usize!(0xB00, __read_mcycle);
+read_csr_as_usize!(0xB00);
 read_composite_csr!(super::mcycleh::read(), read());

src/register/mcycleh.rs

@@ -1,3 +1,3 @@
 //! mcycleh register
 
-read_csr_as_usize_rv32!(0xB80, __read_mcycleh);
+read_csr_as_usize_rv32!(0xB80);

src/register/medeleg.rs

@@ -100,9 +100,9 @@ impl Medeleg {
     }
 }
 
-read_csr_as!(Medeleg, 0x302, __read_medeleg);
-set!(0x302, __set_medeleg);
-clear!(0x302, __clear_medeleg);
+read_csr_as!(Medeleg, 0x302);
+set!(0x302);
+clear!(0x302);
 
 set_clear_csr!(
     /// Instruction Address Misaligned Delegate

src/register/mepc.rs

@@ -1,4 +1,4 @@
 //! mepc register
 
-read_csr_as_usize!(0x341, __read_mepc);
-write_csr_as_usize!(0x341, __write_mepc);
+read_csr_as_usize!(0x341);
+write_csr_as_usize!(0x341);

src/register/mhartid.rs

@@ -1,3 +1,3 @@
 //! mhartid register
 
-read_csr_as_usize!(0xf14, __read_mhartid);
+read_csr_as_usize!(0xf14);

src/register/mhpmcounterx.rs

@@ -1,11 +1,11 @@
 macro_rules! reg {
     (
-        $addr:expr, $csrl:ident, $csrh:ident, $readf:ident, $writef:ident
+        $addr:expr, $csrl:ident, $csrh:ident
     ) => {
         /// Machine performance-monitoring counter
         pub mod $csrl {
-            read_csr_as_usize!($addr, $readf);
-            write_csr_as_usize!($addr, $writef);
+            read_csr_as_usize!($addr);
+            write_csr_as_usize!($addr);
             read_composite_csr!(super::$csrh::read(), read());
         }
     };
@@ -13,391 +13,72 @@ macro_rules! reg {
 
 macro_rules! regh {
     (
-        $addr:expr, $csrh:ident, $readf:ident, $writef:ident
+        $addr:expr, $csrh:ident
     ) => {
         /// Upper 32 bits of machine performance-monitoring counter (RV32I only)
         pub mod $csrh {
-            read_csr_as_usize_rv32!($addr, $readf);
-            write_csr_as_usize_rv32!($addr, $writef);
+            read_csr_as_usize_rv32!($addr);
+            write_csr_as_usize_rv32!($addr);
         }
     };
 }
 
-reg!(
-    0xB03,
-    mhpmcounter3,
-    mhpmcounter3h,
-    __read_mhpmcounter3,
-    __write_mhpmcounter3
-);
-reg!(
-    0xB04,
-    mhpmcounter4,
-    mhpmcounter4h,
-    __read_mhpmcounter4,
-    __write_mhpmcounter4
-);
-reg!(
-    0xB05,
-    mhpmcounter5,
-    mhpmcounter5h,
-    __read_mhpmcounter5,
-    __write_mhpmcounter5
-);
-reg!(
-    0xB06,
-    mhpmcounter6,
-    mhpmcounter6h,
-    __read_mhpmcounter6,
-    __write_mhpmcounter6
-);
-reg!(
-    0xB07,
-    mhpmcounter7,
-    mhpmcounter7h,
-    __read_mhpmcounter7,
-    __write_mhpmcounter7
-);
-reg!(
-    0xB08,
-    mhpmcounter8,
-    mhpmcounter8h,
-    __read_mhpmcounter8,
-    __write_mhpmcounter8
-);
-reg!(
-    0xB09,
-    mhpmcounter9,
-    mhpmcounter9h,
-    __read_mhpmcounter9,
-    __write_mhpmcounter9
-);
-reg!(
-    0xB0A,
-    mhpmcounter10,
-    mhpmcounter10h,
-    __read_mhpmcounter10,
-    __write_mhpmcounter10
-);
-reg!(
-    0xB0B,
-    mhpmcounter11,
-    mhpmcounter11h,
-    __read_mhpmcounter11,
-    __write_mhpmcounter11
-);
-reg!(
-    0xB0C,
-    mhpmcounter12,
-    mhpmcounter12h,
-    __read_mhpmcounter12,
-    __write_mhpmcounter12
-);
-reg!(
-    0xB0D,
-    mhpmcounter13,
-    mhpmcounter13h,
-    __read_mhpmcounter13,
-    __write_mhpmcounter13
-);
-reg!(
-    0xB0E,
-    mhpmcounter14,
-    mhpmcounter14h,
-    __read_mhpmcounter14,
-    __write_mhpmcounter14
-);
-reg!(
-    0xB0F,
-    mhpmcounter15,
-    mhpmcounter15h,
-    __read_mhpmcounter15,
-    __write_mhpmcounter15
-);
-reg!(
-    0xB10,
-    mhpmcounter16,
-    mhpmcounter16h,
-    __read_mhpmcounter16,
-    __write_mhpmcounter16
-);
-reg!(
-    0xB11,
-    mhpmcounter17,
-    mhpmcounter17h,
-    __read_mhpmcounter17,
-    __write_mhpmcounter17
-);
-reg!(
-    0xB12,
-    mhpmcounter18,
-    mhpmcounter18h,
-    __read_mhpmcounter18,
-    __write_mhpmcounter18
-);
-reg!(
-    0xB13,
-    mhpmcounter19,
-    mhpmcounter19h,
-    __read_mhpmcounter19,
-    __write_mhpmcounter19
-);
-reg!(
-    0xB14,
-    mhpmcounter20,
-    mhpmcounter20h,
-    __read_mhpmcounter20,
-    __write_mhpmcounter20
-);
-reg!(
-    0xB15,
-    mhpmcounter21,
-    mhpmcounter21h,
-    __read_mhpmcounter21,
-    __write_mhpmcounter21
-);
-reg!(
-    0xB16,
-    mhpmcounter22,
-    mhpmcounter22h,
-    __read_mhpmcounter22,
-    __write_mhpmcounter22
-);
-reg!(
-    0xB17,
-    mhpmcounter23,
-    mhpmcounter23h,
-    __read_mhpmcounter23,
-    __write_mhpmcounter23
-);
-reg!(
-    0xB18,
-    mhpmcounter24,
-    mhpmcounter24h,
-    __read_mhpmcounter24,
-    __write_mhpmcounter24
-);
-reg!(
-    0xB19,
-    mhpmcounter25,
-    mhpmcounter25h,
-    __read_mhpmcounter25,
-    __write_mhpmcounter25
-);
-reg!(
-    0xB1A,
-    mhpmcounter26,
-    mhpmcounter26h,
-    __read_mhpmcounter26,
-    __write_mhpmcounter26
-);
-reg!(
-    0xB1B,
-    mhpmcounter27,
-    mhpmcounter27h,
-    __read_mhpmcounter27,
-    __write_mhpmcounter27
-);
-reg!(
-    0xB1C,
-    mhpmcounter28,
-    mhpmcounter28h,
-    __read_mhpmcounter28,
-    __write_mhpmcounter28
-);
-reg!(
-    0xB1D,
-    mhpmcounter29,
-    mhpmcounter29h,
-    __read_mhpmcounter29,
-    __write_mhpmcounter29
-);
-reg!(
-    0xB1E,
-    mhpmcounter30,
-    mhpmcounter30h,
-    __read_mhpmcounter30,
-    __write_mhpmcounter30
-);
-reg!(
-    0xB1F,
-    mhpmcounter31,
-    mhpmcounter31h,
-    __read_mhpmcounter31,
-    __write_mhpmcounter31
-);
+reg!(0xB03, mhpmcounter3, mhpmcounter3h);
+reg!(0xB04, mhpmcounter4, mhpmcounter4h);
+reg!(0xB05, mhpmcounter5, mhpmcounter5h);
+reg!(0xB06, mhpmcounter6, mhpmcounter6h);
+reg!(0xB07, mhpmcounter7, mhpmcounter7h);
+reg!(0xB08, mhpmcounter8, mhpmcounter8h);
+reg!(0xB09, mhpmcounter9, mhpmcounter9h);
+reg!(0xB0A, mhpmcounter10, mhpmcounter10h);
+reg!(0xB0B, mhpmcounter11, mhpmcounter11h);
+reg!(0xB0C, mhpmcounter12, mhpmcounter12h);
+reg!(0xB0D, mhpmcounter13, mhpmcounter13h);
+reg!(0xB0E, mhpmcounter14, mhpmcounter14h);
+reg!(0xB0F, mhpmcounter15, mhpmcounter15h);
+reg!(0xB10, mhpmcounter16, mhpmcounter16h);
+reg!(0xB11, mhpmcounter17, mhpmcounter17h);
+reg!(0xB12, mhpmcounter18, mhpmcounter18h);
+reg!(0xB13, mhpmcounter19, mhpmcounter19h);
+reg!(0xB14, mhpmcounter20, mhpmcounter20h);
+reg!(0xB15, mhpmcounter21, mhpmcounter21h);
+reg!(0xB16, mhpmcounter22, mhpmcounter22h);
+reg!(0xB17, mhpmcounter23, mhpmcounter23h);
+reg!(0xB18, mhpmcounter24, mhpmcounter24h);
+reg!(0xB19, mhpmcounter25, mhpmcounter25h);
+reg!(0xB1A, mhpmcounter26, mhpmcounter26h);
+reg!(0xB1B, mhpmcounter27, mhpmcounter27h);
+reg!(0xB1C, mhpmcounter28, mhpmcounter28h);
+reg!(0xB1D, mhpmcounter29, mhpmcounter29h);
+reg!(0xB1E, mhpmcounter30, mhpmcounter30h);
+reg!(0xB1F, mhpmcounter31, mhpmcounter31h);
 
-regh!(
-    0xB83,
-    mhpmcounter3h,
-    __read_mhpmcounter3h,
-    __write_mhpmcounter3h
-);
-regh!(
-    0xB84,
-    mhpmcounter4h,
-    __read_mhpmcounter4h,
-    __write_mhpmcounter4h
-);
-regh!(
-    0xB85,
-    mhpmcounter5h,
-    __read_mhpmcounter5h,
-    __write_mhpmcounter5h
-);
-regh!(
-    0xB86,
-    mhpmcounter6h,
-    __read_mhpmcounter6h,
-    __write_mhpmcounter6h
-);
-regh!(
-    0xB87,
-    mhpmcounter7h,
-    __read_mhpmcounter7h,
-    __write_mhpmcounter7h
-);
-regh!(
-    0xB88,
-    mhpmcounter8h,
-    __read_mhpmcounter8h,
-    __write_mhpmcounter8h
-);
-regh!(
-    0xB89,
-    mhpmcounter9h,
-    __read_mhpmcounter9h,
-    __write_mhpmcounter9h
-);
-regh!(
-    0xB8A,
-    mhpmcounter10h,
-    __read_mhpmcounter10h,
-    __write_mhpmcounter10h
-);
-regh!(
-    0xB8B,
-    mhpmcounter11h,
-    __read_mhpmcounter11h,
-    __write_mhpmcounter11h
-);
-regh!(
-    0xB8C,
-    mhpmcounter12h,
-    __read_mhpmcounter12h,
-    __write_mhpmcounter12h
-);
-regh!(
-    0xB8D,
-    mhpmcounter13h,
-    __read_mhpmcounter13h,
-    __write_mhpmcounter13h
-);
-regh!(
-    0xB8E,
-    mhpmcounter14h,
-    __read_mhpmcounter14h,
-    __write_mhpmcounter14h
-);
-regh!(
-    0xB8F,
-    mhpmcounter15h,
-    __read_mhpmcounter15h,
-    __write_mhpmcounter15h
-);
-regh!(
-    0xB90,
-    mhpmcounter16h,
-    __read_mhpmcounter16h,
-    __write_mhpmcounter16h
-);
-regh!(
-    0xB91,
-    mhpmcounter17h,
-    __read_mhpmcounter17h,
-    __write_mhpmcounter17h
-);
-regh!(
-    0xB92,
-    mhpmcounter18h,
-    __read_mhpmcounter18h,
-    __write_mhpmcounter18h
-);
-regh!(
-    0xB93,
-    mhpmcounter19h,
-    __read_mhpmcounter19h,
-    __write_mhpmcounter19h
-);
-regh!(
-    0xB94,
-    mhpmcounter20h,
-    __read_mhpmcounter20h,
-    __write_mhpmcounter20h
-);
-regh!(
-    0xB95,
-    mhpmcounter21h,
-    __read_mhpmcounter21h,
-    __write_mhpmcounter21h
-);
-regh!(
-    0xB96,
-    mhpmcounter22h,
-    __read_mhpmcounter22h,
-    __write_mhpmcounter22h
-);
-regh!(
-    0xB97,
-    mhpmcounter23h,
-    __read_mhpmcounter23h,
-    __write_mhpmcounter23h
-);
-regh!(
-    0xB98,
-    mhpmcounter24h,
-    __read_mhpmcounter24h,
-    __write_mhpmcounter24h
-);
-regh!(
-    0xB99,
-    mhpmcounter25h,
-    __read_mhpmcounter25h,
-    __write_mhpmcounter25h
-);
-regh!(
-    0xB9A,
-    mhpmcounter26h,
-    __read_mhpmcounter26h,
-    __write_mhpmcounter26h
-);
-regh!(
-    0xB9B,
-    mhpmcounter27h,
-    __read_mhpmcounter27h,
-    __write_mhpmcounter27h
-);
-regh!(
-    0xB9C,
-    mhpmcounter28h,
-    __read_mhpmcounter28h,
-    __write_mhpmcounter28h
-);
-regh!(
-    0xB9D,
-    mhpmcounter29h,
-    __read_mhpmcounter29h,
-    __write_mhpmcounter29h
-);
-regh!(
-    0xB9E,
-    mhpmcounter30h,
-    __read_mhpmcounter30h,
-    __write_mhpmcounter30h
-);
-regh!(
-    0xB9F,
-    mhpmcounter31h,
-    __read_mhpmcounter31h,
-    __write_mhpmcounter31h
-);
+regh!(0xB83, mhpmcounter3h);
+regh!(0xB84, mhpmcounter4h);
+regh!(0xB85, mhpmcounter5h);
+regh!(0xB86, mhpmcounter6h);
+regh!(0xB87, mhpmcounter7h);
+regh!(0xB88, mhpmcounter8h);
+regh!(0xB89, mhpmcounter9h);
+regh!(0xB8A, mhpmcounter10h);
+regh!(0xB8B, mhpmcounter11h);
+regh!(0xB8C, mhpmcounter12h);
+regh!(0xB8D, mhpmcounter13h);
+regh!(0xB8E, mhpmcounter14h);
+regh!(0xB8F, mhpmcounter15h);
+regh!(0xB90, mhpmcounter16h);
+regh!(0xB91, mhpmcounter17h);
+regh!(0xB92, mhpmcounter18h);
+regh!(0xB93, mhpmcounter19h);
+regh!(0xB94, mhpmcounter20h);
+regh!(0xB95, mhpmcounter21h);
+regh!(0xB96, mhpmcounter22h);
+regh!(0xB97, mhpmcounter23h);
+regh!(0xB98, mhpmcounter24h);
+regh!(0xB99, mhpmcounter25h);
+regh!(0xB9A, mhpmcounter26h);
+regh!(0xB9B, mhpmcounter27h);
+regh!(0xB9C, mhpmcounter28h);
+regh!(0xB9D, mhpmcounter29h);
+regh!(0xB9E, mhpmcounter30h);
+regh!(0xB9F, mhpmcounter31h);

src/register/mhpmeventx.rs

@@ -1,41 +1,41 @@
 macro_rules! reg {
     (
-        $addr:expr, $csr:ident, $readf:ident, $writef:ident
+        $addr:expr, $csr:ident
     ) => {
         /// Machine performance-monitoring event selector
         pub mod $csr {
-            read_csr_as_usize!($addr, $readf);
-            write_csr_as_usize!($addr, $writef);
+            read_csr_as_usize!($addr);
+            write_csr_as_usize!($addr);
         }
     };
 }
 
-reg!(0x323, mhpmevent3, __read_mhpmevent3, __write_mhpmevent3);
-reg!(0x324, mhpmevent4, __read_mhpmevent4, __write_mhpmevent4);
-reg!(0x325, mhpmevent5, __read_mhpmevent5, __write_mhpmevent5);
-reg!(0x326, mhpmevent6, __read_mhpmevent6, __write_mhpmevent6);
-reg!(0x327, mhpmevent7, __read_mhpmevent7, __write_mhpmevent7);
-reg!(0x328, mhpmevent8, __read_mhpmevent8, __write_mhpmevent8);
-reg!(0x329, mhpmevent9, __read_mhpmevent9, __write_mhpmevent9);
-reg!(0x32A, mhpmevent10, __read_mhpmevent10, __write_mhpmevent10);
-reg!(0x32B, mhpmevent11, __read_mhpmevent11, __write_mhpmevent11);
-reg!(0x32C, mhpmevent12, __read_mhpmevent12, __write_mhpmevent12);
-reg!(0x32D, mhpmevent13, __read_mhpmevent13, __write_mhpmevent13);
-reg!(0x32E, mhpmevent14, __read_mhpmevent14, __write_mhpmevent14);
-reg!(0x32F, mhpmevent15, __read_mhpmevent15, __write_mhpmevent15);
-reg!(0x330, mhpmevent16, __read_mhpmevent16, __write_mhpmevent16);
-reg!(0x331, mhpmevent17, __read_mhpmevent17, __write_mhpmevent17);
-reg!(0x332, mhpmevent18, __read_mhpmevent18, __write_mhpmevent18);
-reg!(0x333, mhpmevent19, __read_mhpmevent19, __write_mhpmevent19);
-reg!(0x334, mhpmevent20, __read_mhpmevent20, __write_mhpmevent20);
-reg!(0x335, mhpmevent21, __read_mhpmevent21, __write_mhpmevent21);
-reg!(0x336, mhpmevent22, __read_mhpmevent22, __write_mhpmevent22);
-reg!(0x337, mhpmevent23, __read_mhpmevent23, __write_mhpmevent23);
-reg!(0x338, mhpmevent24, __read_mhpmevent24, __write_mhpmevent24);
-reg!(0x339, mhpmevent25, __read_mhpmevent25, __write_mhpmevent25);
-reg!(0x33A, mhpmevent26, __read_mhpmevent26, __write_mhpmevent26);
-reg!(0x33B, mhpmevent27, __read_mhpmevent27, __write_mhpmevent27);
-reg!(0x33C, mhpmevent28, __read_mhpmevent28, __write_mhpmevent28);
-reg!(0x33D, mhpmevent29, __read_mhpmevent29, __write_mhpmevent29);
-reg!(0x33E, mhpmevent30, __read_mhpmevent30, __write_mhpmevent30);
-reg!(0x33F, mhpmevent31, __read_mhpmevent31, __write_mhpmevent31);
+reg!(0x323, mhpmevent3);
+reg!(0x324, mhpmevent4);
+reg!(0x325, mhpmevent5);
+reg!(0x326, mhpmevent6);
+reg!(0x327, mhpmevent7);
+reg!(0x328, mhpmevent8);
+reg!(0x329, mhpmevent9);
+reg!(0x32A, mhpmevent10);
+reg!(0x32B, mhpmevent11);
+reg!(0x32C, mhpmevent12);
+reg!(0x32D, mhpmevent13);
+reg!(0x32E, mhpmevent14);
+reg!(0x32F, mhpmevent15);
+reg!(0x330, mhpmevent16);
+reg!(0x331, mhpmevent17);
+reg!(0x332, mhpmevent18);
+reg!(0x333, mhpmevent19);
+reg!(0x334, mhpmevent20);
+reg!(0x335, mhpmevent21);
+reg!(0x336, mhpmevent22);
+reg!(0x337, mhpmevent23);
+reg!(0x338, mhpmevent24);
+reg!(0x339, mhpmevent25);
+reg!(0x33A, mhpmevent26);
+reg!(0x33B, mhpmevent27);
+reg!(0x33C, mhpmevent28);
+reg!(0x33D, mhpmevent29);
+reg!(0x33E, mhpmevent30);
+reg!(0x33F, mhpmevent31);

src/register/mideleg.rs

@@ -52,9 +52,9 @@ impl Mideleg {
     }
 }
 
-read_csr_as!(Mideleg, 0x303, __read_mideleg);
-set!(0x303, __set_mideleg);
-clear!(0x303, __clear_mideleg);
+read_csr_as!(Mideleg, 0x303);
+set!(0x303);
+clear!(0x303);
 
 set_clear_csr!(
     /// User Software Interrupt Delegate

src/register/mie.rs

@@ -70,9 +70,9 @@ impl Mie {
     }
 }
 
-read_csr_as!(Mie, 0x304, __read_mie);
-set!(0x304, __set_mie);
-clear!(0x304, __clear_mie);
+read_csr_as!(Mie, 0x304);
+set!(0x304);
+clear!(0x304);
 
 set_clear_csr!(
     /// User Software Interrupt Enable

src/register/mimpid.rs

@@ -16,7 +16,7 @@ impl Mimpid {
     }
 }
 
-read_csr!(0xF11, __read_mimpid);
+read_csr!(0xF11);
 
 /// Reads the CSR
 #[inline]

src/register/minstret.rs

@@ -1,4 +1,4 @@
 //! minstret register
 
-read_csr_as_usize!(0xB02, __read_minstret);
+read_csr_as_usize!(0xB02);
 read_composite_csr!(super::minstreth::read(), read());

src/register/minstreth.rs

@@ -1,3 +1,3 @@
 //! minstreth register
 
-read_csr_as_usize_rv32!(0xB82, __read_minstreth);
+read_csr_as_usize_rv32!(0xB82);

src/register/mip.rs

@@ -70,9 +70,9 @@ impl Mip {
     }
 }
 
-read_csr_as!(Mip, 0x344, __read_mip);
-set!(0x344, __set_mip);
-clear!(0x344, __clear_mip);
+read_csr_as!(Mip, 0x344);
+set!(0x344);
+clear!(0x344);
 
 set_clear_csr!(
     /// User Software Interrupt Pending

src/register/misa.rs

@@ -51,7 +51,7 @@ impl Misa {
     }
 }
 
-read_csr!(0x301, __read_misa);
+read_csr!(0x301);
 
 /// Reads the CSR
 #[inline]

src/register/mscratch.rs

@@ -1,4 +1,4 @@
 //! mscratch register
 
-read_csr_as_usize!(0x340, __read_mscratch);
-write_csr_as_usize!(0x340, __write_mscratch);
+read_csr_as_usize!(0x340);
+write_csr_as_usize!(0x340);

src/register/mstatus.rs

@@ -209,10 +209,10 @@ impl Mstatus {
     }
 }
 
-read_csr_as!(Mstatus, 0x300, __read_mstatus);
-write_csr!(0x300, __write_mstatus);
-set!(0x300, __set_mstatus);
-clear!(0x300, __clear_mstatus);
+read_csr_as!(Mstatus, 0x300);
+write_csr!(0x300);
+set!(0x300);
+clear!(0x300);
 
 set_clear_csr!(
     /// User Interrupt Enable

src/register/mtval.rs

@@ -1,3 +1,3 @@
 //! mtval register
 
-read_csr_as_usize!(0x343, __read_mtval);
+read_csr_as_usize!(0x343);

src/register/mtvec.rs

@@ -38,9 +38,9 @@ impl Mtvec {
     }
 }
 
-read_csr_as!(Mtvec, 0x305, __read_mtvec);
+read_csr_as!(Mtvec, 0x305);
 
-write_csr!(0x305, __write_mtvec);
+write_csr!(0x305);
 
 /// Writes the CSR
 #[inline]

src/register/mvendorid.rs

@@ -22,7 +22,7 @@ impl Mvendorid {
     }
 }
 
-read_csr!(0xF11, __read_mvendorid);
+read_csr!(0xF11);
 
 /// Reads the CSR
 #[inline]

src/register/pmpaddrx.rs

@@ -1,28 +1,28 @@
 macro_rules! reg {
     (
-        $addr:expr, $csr:ident, $readf:ident, $writef:ident
+        $addr:expr, $csr:ident
     ) => {
         /// Physical memory protection address register
         pub mod $csr {
-            read_csr_as_usize!($addr, $readf);
-            write_csr_as_usize!($addr, $writef);
+            read_csr_as_usize!($addr);
+            write_csr_as_usize!($addr);
         }
     };
 }
 
-reg!(0x3B0, pmpaddr0, __read_pmpaddr0, __write_pmpaddr0);
-reg!(0x3B1, pmpaddr1, __read_pmpaddr1, __write_pmpaddr1);
-reg!(0x3B2, pmpaddr2, __read_pmpaddr2, __write_pmpaddr2);
-reg!(0x3B3, pmpaddr3, __read_pmpaddr3, __write_pmpaddr3);
-reg!(0x3B4, pmpaddr4, __read_pmpaddr4, __write_pmpaddr4);
-reg!(0x3B5, pmpaddr5, __read_pmpaddr5, __write_pmpaddr5);
-reg!(0x3B6, pmpaddr6, __read_pmpaddr6, __write_pmpaddr6);
-reg!(0x3B7, pmpaddr7, __read_pmpaddr7, __write_pmpaddr7);
-reg!(0x3B8, pmpaddr8, __read_pmpaddr8, __write_pmpaddr8);
-reg!(0x3B9, pmpaddr9, __read_pmpaddr9, __write_pmpaddr9);
-reg!(0x3BA, pmpaddr10, __read_pmpaddr10, __write_pmpaddr10);
-reg!(0x3BB, pmpaddr11, __read_pmpaddr11, __write_pmpaddr11);
-reg!(0x3BC, pmpaddr12, __read_pmpaddr12, __write_pmpaddr12);
-reg!(0x3BD, pmpaddr13, __read_pmpaddr13, __write_pmpaddr13);
-reg!(0x3BE, pmpaddr14, __read_pmpaddr14, __write_pmpaddr14);
-reg!(0x3BF, pmpaddr15, __read_pmpaddr15, __write_pmpaddr15);
+reg!(0x3B0, pmpaddr0);
+reg!(0x3B1, pmpaddr1);
+reg!(0x3B2, pmpaddr2);
+reg!(0x3B3, pmpaddr3);
+reg!(0x3B4, pmpaddr4);
+reg!(0x3B5, pmpaddr5);
+reg!(0x3B6, pmpaddr6);
+reg!(0x3B7, pmpaddr7);
+reg!(0x3B8, pmpaddr8);
+reg!(0x3B9, pmpaddr9);
+reg!(0x3BA, pmpaddr10);
+reg!(0x3BB, pmpaddr11);
+reg!(0x3BC, pmpaddr12);
+reg!(0x3BD, pmpaddr13);
+reg!(0x3BE, pmpaddr14);
+reg!(0x3BF, pmpaddr15);

src/register/pmpcfgx.rs

@@ -83,8 +83,8 @@ pub mod pmpcfg0 {
     use super::{Permission, Pmpcsr, Range};
     use bit_field::BitField;
 
-    read_csr_as!(Pmpcsr, 0x3A0, __read_pmpcfg0);
-    write_csr_as_usize!(0x3A0, __write_pmpcfg0);
+    read_csr_as!(Pmpcsr, 0x3A0);
+    write_csr_as_usize!(0x3A0);
 
     set_pmp!();
     clear_pmp!();
@@ -97,8 +97,8 @@ pub mod pmpcfg1 {
     use super::{Permission, Pmpcsr, Range};
     use bit_field::BitField;
 
-    read_csr_as!(Pmpcsr, 0x3A1, __read_pmpcfg1);
-    write_csr_as_usize_rv32!(0x3A1, __write_pmpcfg1);
+    read_csr_as!(Pmpcsr, 0x3A1);
+    write_csr_as_usize_rv32!(0x3A1);
 
     set_pmp!();
     clear_pmp!();
@@ -110,8 +110,8 @@ pub mod pmpcfg2 {
     use super::{Permission, Pmpcsr, Range};
     use bit_field::BitField;
 
-    read_csr_as!(Pmpcsr, 0x3A2, __read_pmpcfg2);
-    write_csr_as_usize!(0x3A2, __write_pmpcfg2);
+    read_csr_as!(Pmpcsr, 0x3A2);
+    write_csr_as_usize!(0x3A2);
 
     set_pmp!();
     clear_pmp!();
@@ -124,8 +124,8 @@ pub mod pmpcfg3 {
     use super::{Permission, Pmpcsr, Range};
     use bit_field::BitField;
 
-    read_csr_as!(Pmpcsr, 0x3A3, __read_pmpcfg3);
-    write_csr_as_usize_rv32!(0x3A3, __write_pmpcfg3);
+    read_csr_as!(Pmpcsr, 0x3A3);
+    write_csr_as_usize_rv32!(0x3A3);
 
     set_pmp!();
     clear_pmp!();

src/register/satp.rs

@@ -94,8 +94,8 @@ pub enum Mode {
     Sv64 = 11,
 }
 
-read_csr_as!(Satp, 0x180, __read_satp);
-write_csr_as_usize!(0x180, __write_satp);
+read_csr_as!(Satp, 0x180);
+write_csr_as_usize!(0x180);
 
 /// Sets the register to corresponding page table mode, physical page number and address space id.
 #[inline]

src/register/scause.rs

@@ -117,8 +117,8 @@ impl Scause {
     }
 }
 
-read_csr_as!(Scause, 0x142, __read_scause);
-write_csr!(0x142, __write_scause);
+read_csr_as!(Scause, 0x142);
+write_csr!(0x142);
 
 /// Writes the CSR
 #[inline]

src/register/scounteren.rs

@@ -35,10 +35,10 @@ impl Scounteren {
     }
 }
 
-read_csr_as!(Scounteren, 0x106, __read_scounteren);
-write_csr!(0x106, __write_scounteren);
-set!(0x106, __set_scounteren);
-clear!(0x106, __clear_scounteren);
+read_csr_as!(Scounteren, 0x106);
+write_csr!(0x106);
+set!(0x106);
+clear!(0x106);
 
 set_clear_csr!(
 /// User cycle Enable

src/register/sepc.rs

@@ -1,4 +1,4 @@
 //! sepc register
 
-read_csr_as_usize!(0x141, __read_sepc);
-write_csr_as_usize!(0x141, __write_sepc);
+read_csr_as_usize!(0x141);
+write_csr_as_usize!(0x141);

src/register/sie.rs

@@ -52,9 +52,9 @@ impl Sie {
     }
 }
 
-read_csr_as!(Sie, 0x104, __read_sie);
-set!(0x104, __set_sie);
-clear!(0x104, __clear_sie);
+read_csr_as!(Sie, 0x104);
+set!(0x104);
+clear!(0x104);
 
 set_clear_csr!(
     /// User Software Interrupt Enable

src/register/sip.rs

@@ -52,4 +52,4 @@ impl Sip {
     }
 }
 
-read_csr_as!(Sip, 0x144, __read_sip);
+read_csr_as!(Sip, 0x144);

src/register/sscratch.rs

@@ -1,4 +1,4 @@
 //! sscratch register
 
-read_csr_as_usize!(0x140, __read_sscratch);
-write_csr_as_usize!(0x140, __write_sscratch);
+read_csr_as_usize!(0x140);
+write_csr_as_usize!(0x140);

src/register/sstatus.rs

@@ -96,10 +96,10 @@ impl Sstatus {
     }
 }
 
-read_csr_as!(Sstatus, 0x100, __read_sstatus);
-write_csr!(0x100, __write_sstatus);
-set!(0x100, __set_sstatus);
-clear!(0x100, __clear_sstatus);
+read_csr_as!(Sstatus, 0x100);
+write_csr!(0x100);
+set!(0x100);
+clear!(0x100);
 
 set_clear_csr!(
     /// User Interrupt Enable

src/register/stval.rs

@@ -1,7 +1,7 @@
 //! stval register
 
-read_csr_as_usize!(0x143, __read_stval);
-write_csr!(0x143, __write_stval);
+read_csr_as_usize!(0x143);
+write_csr!(0x143);
 
 /// Writes the CSR
 #[inline]

src/register/stvec.rs

@@ -33,8 +33,8 @@ impl Stvec {
     }
 }
 
-read_csr_as!(Stvec, 0x105, __read_stvec);
-write_csr!(0x105, __write_stvec);
+read_csr_as!(Stvec, 0x105);
+write_csr!(0x105);
 
 /// Writes the CSR
 #[inline]

src/register/time.rs

@@ -1,4 +1,4 @@
 //! time register
 
-read_csr_as_usize!(0xC01, __read_time);
+read_csr_as_usize!(0xC01);
 read_composite_csr!(super::timeh::read(), read());

src/register/timeh.rs

@@ -1,3 +1,3 @@
 //! timeh register
 
-read_csr_as_usize_rv32!(0xC81, __read_timeh);
+read_csr_as_usize_rv32!(0xC81);

src/register/ucause.rs

@@ -14,8 +14,8 @@ impl Ucause {
     }
 }
 
-read_csr_as!(Ucause, 0x042, __read_ucause);
-write_csr!(0x042, __write_ucause);
+read_csr_as!(Ucause, 0x042);
+write_csr!(0x042);
 
 /// Writes the CSR
 #[inline]

src/register/uepc.rs

@@ -1,4 +1,4 @@
 //! uepc register
 
-read_csr_as_usize!(0x041, __read_uepc);
-write_csr_as_usize!(0x041, __write_uepc);
+read_csr_as_usize!(0x041);
+write_csr_as_usize!(0x041);

src/register/uie.rs

@@ -34,9 +34,9 @@ impl Uie {
     }
 }
 
-read_csr_as!(Uie, 0x004, __read_uie);
-set!(0x004, __set_uie);
-clear!(0x004, __clear_uie);
+read_csr_as!(Uie, 0x004);
+set!(0x004);
+clear!(0x004);
 
 set_clear_csr!(
     /// User Software Interrupt Enable

src/register/uip.rs

@@ -34,4 +34,4 @@ impl Uip {
     }
 }
 
-read_csr_as!(Uip, 0x044, __read_uip);
+read_csr_as!(Uip, 0x044);

src/register/uscratch.rs

@@ -1,4 +1,4 @@
 //! uscratch register
 
-read_csr_as_usize!(0x040, __read_uscratch);
-write_csr_as_usize!(0x040, __write_uscratch);
+read_csr_as_usize!(0x040);
+write_csr_as_usize!(0x040);

src/register/ustatus.rs

@@ -23,10 +23,10 @@ impl Ustatus {
     }
 }
 
-read_csr_as!(Ustatus, 0x000, __read_ustatus);
-write_csr!(0x000, __write_ustatus);
-set!(0x000, __set_ustatus);
-clear!(0x000, __clear_ustatus);
+read_csr_as!(Ustatus, 0x000);
+write_csr!(0x000);
+set!(0x000);
+clear!(0x000);
 
 set_clear_csr!(
     /// User Interrupt Enable

src/register/utval.rs

@@ -1,7 +1,7 @@
 //! utval register
 
-read_csr_as_usize!(0x043, __read_utval);
-write_csr!(0x043, __write_utval);
+read_csr_as_usize!(0x043);
+write_csr!(0x043);
 
 /// Writes the CSR
 #[inline]

src/register/utvec.rs

@@ -33,8 +33,8 @@ impl Utvec {
     }
 }
 
-read_csr_as!(Utvec, 0x005, __read_utvec);
-write_csr!(0x005, __write_utvec);
+read_csr_as!(Utvec, 0x005);
+write_csr!(0x005);
 
 /// Writes the CSR
 #[inline]