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@@ -1,26 +1,5 @@
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-[package]
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-name = "riscv"
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-version = "0.10.1"
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-edition = "2021"
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-rust-version = "1.59"
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-repository = "https://github.com/rust-embedded/riscv"
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-authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
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-categories = ["embedded", "hardware-support", "no-std"]
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-description = "Low level access to RISC-V processors"
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-keywords = ["riscv", "register", "peripheral"]
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-license = "ISC"
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-
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-[package.metadata.docs.rs]
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-all-features = true
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-default-target = "riscv64imac-unknown-none-elf"
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-targets = [
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- "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
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- "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
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+[workspace]
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+resolver = "2"
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+members = [
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+ "riscv",
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]
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-
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-[features]
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-critical-section-single-hart = ["critical-section/restore-state-bool"]
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-
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-[dependencies]
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-critical-section = "1.1.2"
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-embedded-hal = "1.0.0-rc.1"
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