csr: inline register reads and type conversations

apply clippy suggestions

Signed-off-by: luojia65 <me@luojia.cc>

CHANGELOG.md

@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add delay structure and methods using embedded-hal traits and `mcycle` register
 - Add `asm::delay()` function for assembly-based busy-loops
 - Add `asm::nop()`, a wrapper for implementing a `nop` instruction
+- Add missing `#[inline]` attribute to register reads, type conversations and `interrupt::free`
 
 ### Changed
 

src/delay.rs

@@ -9,12 +9,14 @@ pub struct McycleDelay {
 
 impl McycleDelay {
     /// Constructs the delay provider
+    #[inline(always)]
     pub fn new(ticks_second: u32) -> Self {
         Self { ticks_second }
     }
 }
 
 impl DelayUs<u64> for McycleDelay {
+    #[inline(always)]
     fn delay_us(&mut self, us: u64) {
         let t0 = mcycle::read64();
         let clock = (us * (self.ticks_second as u64)) / 1_000_000;
@@ -53,6 +55,7 @@ impl DelayUs<u8> for McycleDelay {
 }
 
 impl DelayMs<u32> for McycleDelay {
+    #[inline(always)]
     fn delay_ms(&mut self, ms: u32) {
         self.delay_us((ms as u64) * 1000)
     }

src/interrupt.rs

@@ -33,6 +33,7 @@ pub unsafe fn enable() {
 /// Execute closure `f` in an interrupt-free context.
 ///
 /// This as also known as a "critical section".
+#[inline]
 pub fn free<F, R>(f: F) -> R
 where
     F: FnOnce(&CriticalSection) -> R,

src/register/fcsr.rs

@@ -76,6 +76,7 @@ pub enum RoundingMode {
 
 impl FCSR {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> u32 {
         self.bits
     }

src/register/marchid.rs

@@ -10,6 +10,7 @@ pub struct Marchid {
 
 impl Marchid {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> usize {
         self.bits.get()
     }

src/register/mcause.rs

@@ -49,6 +49,7 @@ pub enum Exception {
 }
 
 impl Interrupt {
+    #[inline]
     pub fn from(nr: usize) -> Self {
         match nr {
             0 => Interrupt::UserSoft,
@@ -66,6 +67,7 @@ impl Interrupt {
 }
 
 impl Exception {
+    #[inline]
     pub fn from(nr: usize) -> Self {
         match nr {
             0 => Exception::InstructionMisaligned,
@@ -94,6 +96,7 @@ impl Mcause {
     }
 
     /// Returns the code field
+    #[inline]
     pub fn code(&self) -> usize {
         match () {
             #[cfg(target_pointer_width = "32")]

src/register/mimpid.rs

@@ -10,6 +10,7 @@ pub struct Mimpid {
 
 impl Mimpid {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> usize {
         self.bits.get()
     }

src/register/misa.rs

@@ -18,11 +18,13 @@ pub enum MXL {
 
 impl Misa {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> usize {
         self.bits.get()
     }
 
     /// Returns the machine xlen.
+    #[inline]
     pub fn mxl(&self) -> MXL {
         let value = match () {
             #[cfg(target_pointer_width = "32")]
@@ -39,6 +41,7 @@ impl Misa {
     }
 
     /// Returns true when the atomic extension is implemented.
+    #[inline]
     pub fn has_extension(&self, extension: char) -> bool {
         let bit = extension as u8 - 65;
         if bit > 25 {

src/register/mtvec.rs

@@ -15,16 +15,19 @@ pub enum TrapMode {
 
 impl Mtvec {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> usize {
         self.bits
     }
 
     /// Returns the trap-vector base-address
+    #[inline]
     pub fn address(&self) -> usize {
         self.bits - (self.bits & 0b11)
     }
 
     /// Returns the trap-vector mode
+    #[inline]
     pub fn trap_mode(&self) -> Option<TrapMode> {
         let mode = self.bits & 0b11;
         match mode {

src/register/mvendorid.rs

@@ -10,11 +10,13 @@ pub struct Mvendorid {
 
 impl Mvendorid {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> usize {
         self.bits.get()
     }
 
     /// Returns the JEDEC manufacturer ID
+    #[inline]
     pub fn jedec_manufacturer(&self) -> usize {
         self.bits() >> 7
     }

src/register/scause.rs

@@ -46,6 +46,7 @@ pub enum Exception {
 }
 
 impl Interrupt {
+    #[inline]
     pub fn from(nr: usize) -> Self {
         match nr {
             0 => Interrupt::UserSoft,
@@ -60,6 +61,7 @@ impl Interrupt {
 }
 
 impl Exception {
+    #[inline]
     pub fn from(nr: usize) -> Self {
         match nr {
             0 => Exception::InstructionMisaligned,
@@ -86,6 +88,7 @@ impl Scause {
     }
 
     /// Returns the code field
+    #[inline]
     pub fn code(&self) -> usize {
         let bit = 1 << (size_of::<usize>() * 8 - 1);
         self.bits & !bit

src/register/stvec.rs

@@ -10,16 +10,19 @@ pub struct Stvec {
 
 impl Stvec {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> usize {
         self.bits
     }
 
     /// Returns the trap-vector base-address
+    #[inline]
     pub fn address(&self) -> usize {
         self.bits - (self.bits & 0b11)
     }
 
     /// Returns the trap-vector mode
+    #[inline]
     pub fn trap_mode(&self) -> Option<TrapMode> {
         let mode = self.bits & 0b11;
         match mode {

src/register/utvec.rs

@@ -10,16 +10,19 @@ pub struct Utvec {
 
 impl Utvec {
     /// Returns the contents of the register as raw bits
+    #[inline]
     pub fn bits(&self) -> usize {
         self.bits
     }
 
     /// Returns the trap-vector base-address
+    #[inline]
     pub fn address(&self) -> usize {
         self.bits - (self.bits & 0b11)
     }
 
     /// Returns the trap-vector mode
+    #[inline]
     pub fn trap_mode(&self) -> Option<TrapMode> {
         let mode = self.bits & 0b11;
         match mode {