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@@ -0,0 +1,76 @@
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+//! mideleg register
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+
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+use bit_field::BitField;
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+
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+/// mideleg register
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+#[derive(Clone, Copy, Debug)]
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+pub struct Mideleg {
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+ bits: usize,
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+}
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+
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+impl Mideleg {
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+ /// Returns the contents of the register as raw bits
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+ #[inline]
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+ pub fn bits(&self) -> usize {
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+ self.bits
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+ }
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+
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+ /// User Software Interrupt Enable
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+ #[inline]
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+ pub fn usoft(&self) -> bool {
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+ self.bits.get_bit(0)
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+ }
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+
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+ /// Supervisor Software Interrupt Enable
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+ #[inline]
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+ pub fn ssoft(&self) -> bool {
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+ self.bits.get_bit(1)
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+ }
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+
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+ /// User Timer Interrupt Enable
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+ #[inline]
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+ pub fn utimer(&self) -> bool {
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+ self.bits.get_bit(4)
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+ }
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+
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+ /// Supervisor Timer Interrupt Enable
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+ #[inline]
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+ pub fn stimer(&self) -> bool {
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+ self.bits.get_bit(5)
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+ }
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+
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+ /// User External Interrupt Enable
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+ #[inline]
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+ pub fn uext(&self) -> bool {
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+ self.bits.get_bit(8)
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+ }
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+
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+ /// Supervisor External Interrupt Enable
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+ #[inline]
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+ pub fn sext(&self) -> bool {
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+ self.bits.get_bit(9)
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+ }
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+}
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+
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+read_csr_as!(Mideleg, 0x304, __read_mideleg);
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+set!(0x303, __set_mideleg);
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+clear!(0x303, __clear_mideleg);
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+
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+set_clear_csr!(
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+ /// User Software Interrupt Pending
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+ , set_usoft, clear_usoft, 1 << 0);
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+set_clear_csr!(
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+ /// Supervisor Software Interrupt Pending
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+ , set_ssoft, clear_ssoft, 1 << 1);
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+set_clear_csr!(
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+ /// User Timer Interrupt Pending
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+ , set_utimer, clear_utimer, 1 << 4);
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+set_clear_csr!(
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+ /// Supervisor Timer Interrupt Pending
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+ , set_stimer, clear_stimer, 1 << 5);
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+set_clear_csr!(
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+ /// User External Interrupt Pending
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+ , set_uext, clear_uext, 1 << 8);
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+set_clear_csr!(
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+ /// Supervisor External Interrupt Pending
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+ , set_sext, clear_sext, 1 << 9);
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