adjust the workspace

.github/workflows/changelog.yaml

@@ -19,10 +19,12 @@ jobs:
           filters: |
             riscv:
               - 'riscv/**'
-            riscv-rt:
-              - 'riscv-rt/**'
             riscv-pac:
               - 'riscv-pac/**'
+            riscv-rt:
+              - 'riscv-rt/**'
+            riscv-semihosting:
+              - 'riscv-semihosting/**'
 
       - name: Check for CHANGELOG.md (riscv)
         if: steps.changes.outputs.riscv == 'true'
@@ -32,6 +34,14 @@ jobs:
           skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'
 
+      - name: Check for CHANGELOG.md (riscv-pac)
+        if: steps.changes.outputs.riscv-pac == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: ./riscv-pac/CHANGELOG.md
+          skipLabels: 'skip changelog'
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-pac/CHANGELOG.md file.'
+      
       - name: Check for CHANGELOG.md (riscv-rt)
         if: steps.changes.outputs.riscv-rt == 'true'
         uses: dangoslen/changelog-enforcer@v3
@@ -40,10 +50,10 @@ jobs:
           skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-rt/CHANGELOG.md file.'
       
-      - name: Check for CHANGELOG.md (riscv-pac)
-        if: steps.changes.outputs.riscv-pac == 'true'
+      - name: Check for CHANGELOG.md (riscv-semihosting)
+        if: steps.changes.outputs.riscv-semihosting == 'true'
         uses: dangoslen/changelog-enforcer@v3
         with:
-          changeLogPath: ./riscv-pac/CHANGELOG.md
+          changeLogPath: ./riscv-semihosting/CHANGELOG.md
           skipLabels: 'skip changelog'
-          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-pac/CHANGELOG.md file.'
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-semihosting/CHANGELOG.md file.'

.github/workflows/riscv-semihosting.yaml

@@ -0,0 +1,46 @@
+on:
+  push:
+    branches: [ master, semihosting ]
+  pull_request:
+  merge_group:
+
+name: Build check (riscv-semihosting)
+
+jobs:
+  # We check that the crate builds and links for all the toolchains and targets.
+  build-riscv:
+    strategy:
+      matrix:
+        # All generated code should be running on stable now, MRSV is 1.60.0
+        toolchain: [ stable, nightly, 1.60.0 ]
+        target:
+          - riscv32i-unknown-none-elf
+          - riscv32imc-unknown-none-elf
+          - riscv32imac-unknown-none-elf
+          - riscv64imac-unknown-none-elf
+          - riscv64gc-unknown-none-elf
+        include:
+          # Nightly is only for reference and allowed to fail
+          - toolchain: nightly
+            experimental: true
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental || false }}
+    steps:
+    - uses: actions/checkout@v4
+    - uses: dtolnay/rust-toolchain@master
+      with:
+        toolchain: ${{ matrix.toolchain }}
+        targets: ${{ matrix.target }}
+    - name: Build (M-mode)
+      run: cargo build --package riscv-semihosting --target ${{ matrix.target }} --features machine-mode 
+    - name: Build (U-mode)
+      run: cargo build --package riscv-semihosting --target ${{ matrix.target }} --features=user-mode
+
+  # Job to check that all the builds succeeded
+  build-check:
+    needs:
+    - build-riscv
+    runs-on: ubuntu-latest
+    if: always()
+    steps:
+      - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'

Cargo.toml

@@ -4,4 +4,5 @@ members = [
     "riscv",
     "riscv-pac",
     "riscv-rt",
+    "riscv-semihosting",
 ]

README.md

@@ -5,7 +5,7 @@ This repository contains various crates useful for writing Rust programs on RISC
 * [`riscv`]: CPU registers access and intrinsics
 * [`riscv-pac`]: Common traits to be implemented by RISC-V PACs
 * [`riscv-rt`]: Startup code and interrupt handling
-
+* [`riscv-semihosting`]: Semihosting for RISC-V processors
 
 This project is developed and maintained by the [RISC-V team][team].
 
@@ -22,6 +22,8 @@ Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
 to intervene to uphold that code of conduct.
 
 [`riscv`]: https://crates.io/crates/riscv
+[`riscv-pac`]: https://crates.io/crates/riscv-pac
 [`riscv-rt`]: https://crates.io/crates/riscv-rt
+[`riscv-semihosting`]: https://crates.io/crates/riscv-semihosting
 [team]: https://github.com/rust-embedded/wg#the-risc-v-team
 [CoC]: CODE_OF_CONDUCT.md

riscv-semihosting/.github/workflows/check.yml

@@ -1,31 +0,0 @@
-name: check
-on: [push, pull_request]
-
-jobs:
-  check:
-    runs-on: ubuntu-latest
-    strategy:
-      matrix:
-        # All generated code should be running on stable now, MRSV is 1.59.0
-        toolchain: [nightly, stable, 1.59.0]
-        target: [riscv32i-unknown-none-elf, riscv32imc-unknown-none-elf, riscv32imac-unknown-none-elf, riscv64imac-unknown-none-elf, riscv64gc-unknown-none-elf]
-        privilege: [machine, user]
-
-        include:
-          # Nightly is only for reference and allowed to fail
-          - rust: nightly
-            experimental: true
-
-    steps:
-      - uses: actions/checkout@v2
-      - uses: actions-rs/toolchain@v1
-        with:
-          profile: minimal
-          toolchain: ${{ matrix.toolchain }}
-          target: ${{ matrix.target }}
-          override: true
-      - uses: actions-rs/cargo@v1
-        with:
-          use-cross: true
-          command: check
-          args: --verbose --target ${{ matrix.target }} --features=${{matrix.privilege}}-mode

riscv-semihosting/.github/workflows/doc.yml

@@ -1,21 +0,0 @@
-name: doc
-on: [push, pull_request]
-
-
-jobs:
-  doc:
-    runs-on: ubuntu-latest
-    strategy:
-      matrix:
-        privilege: [machine, user]
-    steps:
-      - uses: actions/checkout@v2
-      - uses: actions-rs/toolchain@v1
-        with:
-          profile: minimal
-          toolchain: stable
-          override: true
-      - uses: actions-rs/cargo@v1
-        with:
-          command: doc
-          args: --features=${{matrix.privilege}}-mode

riscv-semihosting/.github/workflows/fmt.yml

@@ -1,18 +0,0 @@
-name: fmt
-on: [push, pull_request]
-
-jobs:
-  fmt:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v2
-      - uses: actions-rs/toolchain@v1
-        with:
-          profile: minimal
-          toolchain: stable
-          override: true
-          components: rustfmt
-      - uses: actions-rs/cargo@v1
-        with:
-          command: fmt
-          args: --all -- --check

riscv-semihosting/.gitignore

@@ -1,2 +0,0 @@
-target
-Cargo.lock

riscv-semihosting/CHANGELOG.md

@@ -5,6 +5,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Moved to the `riscv` Cargo workspace
 - Bring in API changes from
   [cortex-m-semihosting](https://github.com/rust-embedded/cortex-m/tree/master/cortex-m-semihosting),
   including:

riscv-semihosting/Cargo.toml

@@ -11,10 +11,10 @@ categories = ["no-std", "embedded"]
 license = "MIT OR Apache-2.0"
 name = "riscv-semihosting"
 readme = "README.md"
-repository = "https://github.com/riscv-rust/riscv-semihosting"
+repository = "https://github.com/riscv-rust/riscv"
 version = "0.0.1"
 edition = "2021"
-rust-version = "1.59.0"
+rust-version = "1.60.0"
 
 [features]
 default = ["jlink-quirks"]

riscv-semihosting/LICENSE-APACHE

@@ -1,201 +0,0 @@
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-
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riscv-semihosting/LICENSE-MIT

@@ -1,25 +0,0 @@
-Copyright (c) 2017 Jorge Aparicio
-
-Permission is hereby granted, free of charge, to any
-person obtaining a copy of this software and associated
-documentation files (the "Software"), to deal in the
-Software without restriction, including without
-limitation the rights to use, copy, modify, merge,
-publish, distribute, sublicense, and/or sell copies of
-the Software, and to permit persons to whom the Software
-is furnished to do so, subject to the following
-conditions:
-
-The above copyright notice and this permission notice
-shall be included in all copies or substantial portions
-of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
-ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
-TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
-SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
-IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-DEALINGS IN THE SOFTWARE.

riscv-semihosting/README.md

@@ -1,3 +1,6 @@
+[![crates.io](https://img.shields.io/crates/d/riscv-semihosting.svg)](https://crates.io/crates/riscv-semihosting)
+[![crates.io](https://img.shields.io/crates/v/riscv-semihosting.svg)](https://crates.io/crates/riscv-semihosting)
+
 # `riscv-semihosting`
 
 > Semihosting for RISC-V processors
@@ -10,10 +13,10 @@ to support the RISC-V Semihosting Specification as documented
 This crate can (almost) be used in exactly the same way as cortex-m-semihosting,
 simply by changing calls to `cortex_m_semihosting::*` to `riscv_semihosting::*`.
 Given this, the
-[cortex-m-semihosting documentation](https://docs.rs/cortex-m-semihosting) is
+[`cortex-m-semihosting documentation`](https://docs.rs/cortex-m-semihosting) is
 generally sufficient for using this library.
 
-A major difference between this library and cortex-m-semihosting is that there
+A major difference between this library and `cortex-m-semihosting` is that there
 are mandatory features to choose the privilege level at which the semihosting
 calls are executed. The "machine-mode" feature will cause the macros in `export`
 to execute the semihosting operation in an interrupt-free context, while
@@ -23,19 +26,24 @@ these two features will cause a compiler error.
 
 # Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.59.0 and up. It **won't**
+This crate is guaranteed to compile on stable Rust 1.60.0 and up. It **won't**
 compile with older versions.
 
 ## License
 
-Licensed under either of
+Copyright 2018-2023 [RISC-V team][team]
 
-- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or
-  http://www.apache.org/licenses/LICENSE-2.0)
-- MIT license ([LICENSE-MIT](../LICENSE-MIT) or
-  http://opensource.org/licenses/MIT)
+Permission to use, copy, modify, and/or distribute this software for any purpose
+with or without fee is hereby granted, provided that the above copyright notice
+and this permission notice appear in all copies.
 
-at your option.
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
+FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
+OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
+THIS SOFTWARE.
 
 ### Contribution