[package]
name = "riscv"
version = "0.10.1"
edition = "2021"
rust-version = "1.59"
repository = "https://github.com/rust-embedded/riscv"
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISC-V processors"
keywords = ["riscv", "register", "peripheral"]
license = "ISC"

[package.metadata.docs.rs]
all-features = true
default-target = "riscv64imac-unknown-none-elf"
targets = [
    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
    "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
]

[features]
critical-section-single-hart = ["critical-section/restore-state-bool"]
plic = ["volatile-register"]

[dependencies]
critical-section = "1.1.0"
embedded-hal = "0.2.6"
volatile-register = {version  = "0.2.1", optional = true}