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Low level access to RISC-V processors

Aborescence: 0a021ea9bc
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riscv
Román Cárdenas Rodríguez 0a021ea9bc Merge pull request #165 from rust-embedded/smode-riscv il y a 1 an
.github 0a021ea9bc Merge pull request #165 from rust-embedded/smode-riscv il y a 1 an
riscv 8e07693658 s-mode feature il y a 1 an
riscv-pac b68560da22 riscv-pac crate il y a 1 an
riscv-rt 045220785c Merge pull request #166 from mini-ninja-64/add-fpu-support il y a 1 an
.gitignore 4344b03e88 Remove bit_field dependency il y a 1 an
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) il y a 4 ans
Cargo.toml b68560da22 riscv-pac crate il y a 1 an
README.md fd0ecf0a93 forgot README il y a 1 an

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU registers access and intrinsics
  • [riscv-pac]: Common traits to be implemented by RISC-V PACs
  • riscv-rt: Startup code and interrupt handling

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.