Low level access to RISC-V processors

Román Cárdenas 20a912a0c0 vector-like exception handlers 1 ano atrás
.github 20a912a0c0 vector-like exception handlers 1 ano atrás
riscv 1e2f9862ef Additional updates to Rust 1.60.0 1 ano atrás
riscv-rt 20a912a0c0 vector-like exception handlers 1 ano atrás
.gitignore 4344b03e88 Remove bit_field dependency 1 ano atrás
CODE_OF_CONDUCT.md 4bd6d68552 Update link (riscv to risc-v) 4 anos atrás
Cargo.toml cd474dda9c Setting CI (WIP) 1 ano atrás
README.md 5407f3826e Addressing review 1 ano atrás

README.md

RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

  • riscv: CPU peripheral access and intrinsics
  • riscv-rt: Startup code and interrupt handling

This project is developed and maintained by the RISC-V team.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.