Low level access to RISC-V processors
Jakob Weisblat
8597f1c32d
Fix typo in register/misa.rs
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7 anni fa | |
|---|---|---|
| src | 7 anni fa | |
| .gitignore | 7 anni fa | |
| Cargo.toml | 7 anni fa | |
| README.md | 7 anni fa |
README.md
riscv
Low level access to RISCV processors
Implemented Peripherals
- plic
- clint
Implemented privileged ASM instructions
- ecall
- ebreak
- uret
- sret
- mret
- wfi
- sfence.vma
Implemented CSR's
User mode
- ustatus
- uie
- utvec
- uscratch
- uepc
- ucause
- utval
- uip
- fflags
- frm
- fcsr
- cycle
- time
- instret
- hpmcounter[3-31]
- cycleh
- timeh
- instreth
- hpmcounter[3-31]h
Supervisor mode
- sstatus
- sedeleg
- sideleg
- sie
- stvec
- scounteren
- sscratch
- sepc
- scause
- stval
- sip
- satp
Machine mode
- mvendorid
- marchid
- mimpid
- mhartid
- mstatus
- misa
- medeleg
- mideleg
- mie
- mtvec
- mcounteren
- mscratch
- mepc
- mcause
- mtval
- mip
- pmpcfg[0-3]
- pmpaddr[0-15]
- mcycle
- minstret
- mhpmcounter[3-31]
- mcycleh
- minstreth
- mhpmcounter[3-31]h
- mhpmevent[3-31]
- tselect
- tdata[1-3]
License
Copyright 2017 David Craven
Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.