Low level access to RISC-V processors
WangRunji
8776d30d3b
add S-Mode registers
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6 年之前 | |
|---|---|---|
| .github | 6 年之前 | |
| ci | 6 年之前 | |
| src | 6 年之前 | |
| .gitignore | 7 年之前 | |
| .travis.yml | 6 年之前 | |
| CODE_OF_CONDUCT.md | 6 年之前 | |
| Cargo.toml | 6 年之前 | |
| README.md | 6 年之前 |
README.md
riscv
Low level access to RISCV processors
This project is developed and maintained by the RISCV team.
Documentation
License
Copyright 2018 RISCV team
Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
Code of Conduct
Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISCV team, promises to intervene to uphold that code of conduct.